Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	15892901	1			T1	2		T2	134		T3	71
all_pins[1]	15892901	1			T1	2		T2	134		T3	71
all_pins[2]	15892901	1			T1	2		T2	134		T3	71

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47267774	1			T1	4		T2	399		T3	212
values[0x1]	410929	1			T1	2		T2	3		T3	1
transitions[0x0=>0x1]	408546	1			T1	1		T2	3		T3	1
transitions[0x1=>0x0]	408618	1			T1	2		T2	3		T3	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	15820442	1			T1	1		T2	131		T3	70
all_pins[0]	values[0x1]	72459	1			T1	1		T2	3		T3	1
all_pins[0]	transitions[0x0=>0x1]	72446	1			T1	1		T2	3		T3	1
all_pins[0]	transitions[0x1=>0x0]	4745	1			T51	17		T52	1		T35	22
all_pins[1]	values[0x0]	15888143	1			T1	2		T2	134		T3	71
all_pins[1]	values[0x1]	4758	1			T51	17		T52	1		T35	22
all_pins[1]	transitions[0x0=>0x1]	4473	1			T51	17		T52	1		T35	22
all_pins[1]	transitions[0x1=>0x0]	333427	1			T1	1		T14	109		T8	1
all_pins[2]	values[0x0]	15559189	1			T1	1		T2	134		T3	71
all_pins[2]	values[0x1]	333712	1			T1	1		T14	109		T8	1
all_pins[2]	transitions[0x0=>0x1]	331627	1			T14	109		T30	9254		T33	10290
all_pins[2]	transitions[0x1=>0x0]	70446	1			T1	1		T2	3		T3	1