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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.73 98.11 92.78 99.89 79.58 95.93 99.07 97.73


Total test records in report: 934
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T139 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.1028232055 Oct 12 06:27:48 AM UTC 24 Oct 12 06:27:53 AM UTC 24 104989548 ps
T789 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.513607949 Oct 12 06:27:53 AM UTC 24 Oct 12 06:27:55 AM UTC 24 45884311 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2509857255 Oct 12 06:27:51 AM UTC 24 Oct 12 06:27:55 AM UTC 24 64345396 ps
T790 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2984754446 Oct 12 06:27:51 AM UTC 24 Oct 12 06:27:55 AM UTC 24 132584164 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.441830899 Oct 12 06:27:52 AM UTC 24 Oct 12 06:27:55 AM UTC 24 24618519 ps
T791 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.2904978190 Oct 12 06:27:48 AM UTC 24 Oct 12 06:27:56 AM UTC 24 715498690 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3016302728 Oct 12 06:27:53 AM UTC 24 Oct 12 06:27:56 AM UTC 24 209773366 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.222904896 Oct 12 06:27:54 AM UTC 24 Oct 12 06:27:56 AM UTC 24 72133912 ps
T792 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.589171887 Oct 12 06:27:54 AM UTC 24 Oct 12 06:27:57 AM UTC 24 68340644 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2220553511 Oct 12 06:27:45 AM UTC 24 Oct 12 06:27:57 AM UTC 24 646091360 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.4219148135 Oct 12 06:27:55 AM UTC 24 Oct 12 06:27:57 AM UTC 24 15810285 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.365726898 Oct 12 06:27:45 AM UTC 24 Oct 12 06:27:57 AM UTC 24 944656195 ps
T793 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.2804679554 Oct 12 06:28:09 AM UTC 24 Oct 12 06:28:13 AM UTC 24 83516743 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1764046885 Oct 12 06:27:54 AM UTC 24 Oct 12 06:27:58 AM UTC 24 192108646 ps
T794 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.1819476277 Oct 12 06:27:56 AM UTC 24 Oct 12 06:27:59 AM UTC 24 23258403 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.353795989 Oct 12 06:27:56 AM UTC 24 Oct 12 06:27:59 AM UTC 24 16929612 ps
T796 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1149281783 Oct 12 06:27:56 AM UTC 24 Oct 12 06:28:00 AM UTC 24 140969503 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.543264768 Oct 12 06:27:57 AM UTC 24 Oct 12 06:28:00 AM UTC 24 227226422 ps
T797 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3048110769 Oct 12 06:27:59 AM UTC 24 Oct 12 06:28:01 AM UTC 24 22336408 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.2179704918 Oct 12 06:27:59 AM UTC 24 Oct 12 06:28:01 AM UTC 24 31333724 ps
T798 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2140680522 Oct 12 06:27:57 AM UTC 24 Oct 12 06:28:01 AM UTC 24 336056868 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.653467743 Oct 12 06:27:59 AM UTC 24 Oct 12 06:28:01 AM UTC 24 31019325 ps
T799 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.883724075 Oct 12 06:27:59 AM UTC 24 Oct 12 06:28:02 AM UTC 24 59560756 ps
T800 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.283393612 Oct 12 06:27:57 AM UTC 24 Oct 12 06:28:02 AM UTC 24 149257493 ps
T801 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.1805011160 Oct 12 06:28:00 AM UTC 24 Oct 12 06:28:03 AM UTC 24 18203318 ps
T802 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2815605622 Oct 12 06:27:39 AM UTC 24 Oct 12 06:28:03 AM UTC 24 1440115423 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.4093192357 Oct 12 06:28:00 AM UTC 24 Oct 12 06:28:03 AM UTC 24 20261715 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.2436635411 Oct 12 06:27:59 AM UTC 24 Oct 12 06:28:03 AM UTC 24 411021781 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1989264837 Oct 12 06:28:01 AM UTC 24 Oct 12 06:28:04 AM UTC 24 129412432 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.3661946229 Oct 12 06:27:50 AM UTC 24 Oct 12 06:28:05 AM UTC 24 8654957071 ps
T123 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2359308146 Oct 12 06:28:02 AM UTC 24 Oct 12 06:28:06 AM UTC 24 43519048 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.215402694 Oct 12 06:28:04 AM UTC 24 Oct 12 06:28:06 AM UTC 24 12745317 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.3470008321 Oct 12 06:28:04 AM UTC 24 Oct 12 06:28:06 AM UTC 24 59666736 ps
T804 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2178606412 Oct 12 06:28:02 AM UTC 24 Oct 12 06:28:07 AM UTC 24 57584302 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1074048446 Oct 12 06:28:04 AM UTC 24 Oct 12 06:28:07 AM UTC 24 55424104 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.152337893 Oct 12 06:28:03 AM UTC 24 Oct 12 06:28:07 AM UTC 24 63407268 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2536118040 Oct 12 06:28:02 AM UTC 24 Oct 12 06:28:07 AM UTC 24 78441763 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3364031816 Oct 12 06:28:04 AM UTC 24 Oct 12 06:28:07 AM UTC 24 56698064 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.568554921 Oct 12 06:28:05 AM UTC 24 Oct 12 06:28:08 AM UTC 24 19638250 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.2330950748 Oct 12 06:28:07 AM UTC 24 Oct 12 06:28:09 AM UTC 24 20719620 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3239006463 Oct 12 06:28:05 AM UTC 24 Oct 12 06:28:10 AM UTC 24 75016300 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2508855580 Oct 12 06:28:06 AM UTC 24 Oct 12 06:28:10 AM UTC 24 54349166 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.983763093 Oct 12 06:27:56 AM UTC 24 Oct 12 06:28:10 AM UTC 24 2265668314 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1245989600 Oct 12 06:28:09 AM UTC 24 Oct 12 06:28:11 AM UTC 24 524345074 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.1099913548 Oct 12 06:28:06 AM UTC 24 Oct 12 06:28:11 AM UTC 24 50252796 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.3821381165 Oct 12 06:28:01 AM UTC 24 Oct 12 06:28:12 AM UTC 24 519785867 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2365981917 Oct 12 06:28:08 AM UTC 24 Oct 12 06:28:12 AM UTC 24 43392530 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.3299665180 Oct 12 06:28:10 AM UTC 24 Oct 12 06:28:12 AM UTC 24 99797725 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2036666544 Oct 12 06:28:08 AM UTC 24 Oct 12 06:28:12 AM UTC 24 36422498 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.2176663970 Oct 12 06:28:10 AM UTC 24 Oct 12 06:28:13 AM UTC 24 31028025 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.942334971 Oct 12 06:28:07 AM UTC 24 Oct 12 06:28:13 AM UTC 24 1349673287 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1353758087 Oct 12 06:27:50 AM UTC 24 Oct 12 06:28:13 AM UTC 24 10648651288 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.67692208 Oct 12 06:28:01 AM UTC 24 Oct 12 06:28:15 AM UTC 24 666267292 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3232403889 Oct 12 06:28:09 AM UTC 24 Oct 12 06:28:13 AM UTC 24 713725044 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3334442123 Oct 12 06:28:11 AM UTC 24 Oct 12 06:28:14 AM UTC 24 42743480 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2757340764 Oct 12 06:28:11 AM UTC 24 Oct 12 06:28:14 AM UTC 24 23863494 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3290838221 Oct 12 06:28:11 AM UTC 24 Oct 12 06:28:14 AM UTC 24 131490256 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.651706203 Oct 12 06:28:12 AM UTC 24 Oct 12 06:28:15 AM UTC 24 190613954 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.2204770400 Oct 12 06:28:09 AM UTC 24 Oct 12 06:28:16 AM UTC 24 241204760 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.2815927223 Oct 12 06:28:13 AM UTC 24 Oct 12 06:28:16 AM UTC 24 29701316 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.2874857862 Oct 12 06:28:33 AM UTC 24 Oct 12 06:28:35 AM UTC 24 24432255 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3079515705 Oct 12 06:28:12 AM UTC 24 Oct 12 06:28:16 AM UTC 24 57861168 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.1373492259 Oct 12 06:28:14 AM UTC 24 Oct 12 06:28:16 AM UTC 24 98607064 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2313669998 Oct 12 06:28:14 AM UTC 24 Oct 12 06:28:17 AM UTC 24 95802242 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3527844587 Oct 12 06:28:14 AM UTC 24 Oct 12 06:28:17 AM UTC 24 104473613 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2837728652 Oct 12 06:28:15 AM UTC 24 Oct 12 06:28:17 AM UTC 24 67597590 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.1058457675 Oct 12 06:28:15 AM UTC 24 Oct 12 06:28:17 AM UTC 24 20902990 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3231884218 Oct 12 06:28:15 AM UTC 24 Oct 12 06:28:18 AM UTC 24 99508415 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2625329701 Oct 12 06:28:14 AM UTC 24 Oct 12 06:28:19 AM UTC 24 384957050 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2009085647 Oct 12 06:27:56 AM UTC 24 Oct 12 06:28:19 AM UTC 24 4378578690 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1238883415 Oct 12 06:28:12 AM UTC 24 Oct 12 06:28:19 AM UTC 24 998732685 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.585311904 Oct 12 06:28:16 AM UTC 24 Oct 12 06:28:19 AM UTC 24 31987226 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.1800551665 Oct 12 06:28:14 AM UTC 24 Oct 12 06:28:19 AM UTC 24 540474791 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1546169997 Oct 12 06:28:14 AM UTC 24 Oct 12 06:28:19 AM UTC 24 234212788 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2631455351 Oct 12 06:28:16 AM UTC 24 Oct 12 06:28:20 AM UTC 24 176986657 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2970717965 Oct 12 06:28:18 AM UTC 24 Oct 12 06:28:20 AM UTC 24 42810570 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.1901670233 Oct 12 06:28:16 AM UTC 24 Oct 12 06:28:20 AM UTC 24 26232109 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1935632248 Oct 12 06:28:18 AM UTC 24 Oct 12 06:28:20 AM UTC 24 69137729 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3296926054 Oct 12 06:28:15 AM UTC 24 Oct 12 06:28:20 AM UTC 24 212052874 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1164640165 Oct 12 06:28:18 AM UTC 24 Oct 12 06:28:21 AM UTC 24 52213473 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1559920284 Oct 12 06:28:16 AM UTC 24 Oct 12 06:28:21 AM UTC 24 371376326 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3700201750 Oct 12 06:28:18 AM UTC 24 Oct 12 06:28:21 AM UTC 24 70773718 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3053501699 Oct 12 06:28:18 AM UTC 24 Oct 12 06:28:22 AM UTC 24 469062128 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.302618812 Oct 12 06:28:16 AM UTC 24 Oct 12 06:28:22 AM UTC 24 135078112 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3111221030 Oct 12 06:28:20 AM UTC 24 Oct 12 06:28:22 AM UTC 24 20110749 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3409917922 Oct 12 06:28:20 AM UTC 24 Oct 12 06:28:23 AM UTC 24 20406867 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.1064716403 Oct 12 06:28:19 AM UTC 24 Oct 12 06:28:23 AM UTC 24 104119029 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.985818643 Oct 12 06:28:19 AM UTC 24 Oct 12 06:28:23 AM UTC 24 169791075 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4210330136 Oct 12 06:28:20 AM UTC 24 Oct 12 06:28:23 AM UTC 24 254145808 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1226158194 Oct 12 06:28:22 AM UTC 24 Oct 12 06:28:24 AM UTC 24 23329935 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1279377382 Oct 12 06:28:20 AM UTC 24 Oct 12 06:28:24 AM UTC 24 78584435 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1413252400 Oct 12 06:28:20 AM UTC 24 Oct 12 06:28:24 AM UTC 24 242964166 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1198060788 Oct 12 06:28:22 AM UTC 24 Oct 12 06:28:24 AM UTC 24 32280236 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3241436996 Oct 12 06:28:20 AM UTC 24 Oct 12 06:28:24 AM UTC 24 244450304 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3983887873 Oct 12 06:28:22 AM UTC 24 Oct 12 06:28:25 AM UTC 24 101813101 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2165949370 Oct 12 06:28:19 AM UTC 24 Oct 12 06:28:25 AM UTC 24 66925658 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3717491659 Oct 12 06:28:23 AM UTC 24 Oct 12 06:28:25 AM UTC 24 14432244 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1633053480 Oct 12 06:28:22 AM UTC 24 Oct 12 06:28:25 AM UTC 24 218003833 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.925411290 Oct 12 06:28:23 AM UTC 24 Oct 12 06:28:26 AM UTC 24 16276345 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.2286398298 Oct 12 06:28:22 AM UTC 24 Oct 12 06:28:26 AM UTC 24 478867674 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.138372528 Oct 12 06:28:22 AM UTC 24 Oct 12 06:28:26 AM UTC 24 127713426 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1659539339 Oct 12 06:28:22 AM UTC 24 Oct 12 06:28:26 AM UTC 24 109940662 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3727319294 Oct 12 06:28:22 AM UTC 24 Oct 12 06:28:26 AM UTC 24 128859783 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3365637704 Oct 12 06:28:20 AM UTC 24 Oct 12 06:28:28 AM UTC 24 477825908 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.2529871630 Oct 12 06:28:26 AM UTC 24 Oct 12 06:28:28 AM UTC 24 13587695 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.660869807 Oct 12 06:28:25 AM UTC 24 Oct 12 06:28:28 AM UTC 24 29771668 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.2952987002 Oct 12 06:28:25 AM UTC 24 Oct 12 06:28:28 AM UTC 24 301480859 ps
T187 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.2291395290 Oct 12 06:28:23 AM UTC 24 Oct 12 06:28:28 AM UTC 24 371361695 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2529924575 Oct 12 06:28:26 AM UTC 24 Oct 12 06:28:28 AM UTC 24 74186330 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1481566246 Oct 12 06:28:26 AM UTC 24 Oct 12 06:28:29 AM UTC 24 60071098 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.4019962574 Oct 12 06:28:27 AM UTC 24 Oct 12 06:28:30 AM UTC 24 19691559 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1982027323 Oct 12 06:28:24 AM UTC 24 Oct 12 06:28:30 AM UTC 24 124902697 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.120580046 Oct 12 06:28:27 AM UTC 24 Oct 12 06:28:30 AM UTC 24 29874419 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.626964012 Oct 12 06:28:26 AM UTC 24 Oct 12 06:28:30 AM UTC 24 162695522 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.788644739 Oct 12 06:28:28 AM UTC 24 Oct 12 06:28:30 AM UTC 24 72737537 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.970742248 Oct 12 06:28:31 AM UTC 24 Oct 12 06:28:35 AM UTC 24 58405248 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2723443738 Oct 12 06:28:27 AM UTC 24 Oct 12 06:28:31 AM UTC 24 108567625 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.682560331 Oct 12 06:28:26 AM UTC 24 Oct 12 06:28:31 AM UTC 24 311842998 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.2407090123 Oct 12 06:28:27 AM UTC 24 Oct 12 06:28:31 AM UTC 24 291778365 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3582193881 Oct 12 06:28:29 AM UTC 24 Oct 12 06:28:31 AM UTC 24 24550899 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.813603631 Oct 12 06:28:29 AM UTC 24 Oct 12 06:28:31 AM UTC 24 31709858 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1538964649 Oct 12 06:28:28 AM UTC 24 Oct 12 06:28:32 AM UTC 24 99462268 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.422103990 Oct 12 06:28:25 AM UTC 24 Oct 12 06:28:32 AM UTC 24 57676012 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2943272749 Oct 12 06:28:24 AM UTC 24 Oct 12 06:28:32 AM UTC 24 82422878 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3194756392 Oct 12 06:28:30 AM UTC 24 Oct 12 06:28:32 AM UTC 24 36424162 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1681987157 Oct 12 06:28:25 AM UTC 24 Oct 12 06:28:33 AM UTC 24 3656412048 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3055948544 Oct 12 06:28:29 AM UTC 24 Oct 12 06:28:33 AM UTC 24 87749067 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.883023414 Oct 12 06:28:30 AM UTC 24 Oct 12 06:28:33 AM UTC 24 79287454 ps
T192 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2158988552 Oct 12 06:28:27 AM UTC 24 Oct 12 06:28:34 AM UTC 24 396713626 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2127811181 Oct 12 06:28:31 AM UTC 24 Oct 12 06:28:34 AM UTC 24 17153303 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3687447931 Oct 12 06:28:32 AM UTC 24 Oct 12 06:28:34 AM UTC 24 77752737 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3482578208 Oct 12 06:28:29 AM UTC 24 Oct 12 06:28:34 AM UTC 24 114546517 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.175357294 Oct 12 06:28:30 AM UTC 24 Oct 12 06:28:34 AM UTC 24 139734380 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2415977720 Oct 12 06:28:32 AM UTC 24 Oct 12 06:28:34 AM UTC 24 37346928 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1831897040 Oct 12 06:28:32 AM UTC 24 Oct 12 06:28:35 AM UTC 24 403904351 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2896154298 Oct 12 06:28:29 AM UTC 24 Oct 12 06:28:36 AM UTC 24 350491223 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.786058402 Oct 12 06:28:31 AM UTC 24 Oct 12 06:28:36 AM UTC 24 77139208 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.430902419 Oct 12 06:28:33 AM UTC 24 Oct 12 06:28:36 AM UTC 24 17629072 ps
T188 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.806496584 Oct 12 06:28:31 AM UTC 24 Oct 12 06:28:36 AM UTC 24 123346761 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2599873614 Oct 12 06:28:32 AM UTC 24 Oct 12 06:28:36 AM UTC 24 545178637 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.4252695076 Oct 12 06:28:31 AM UTC 24 Oct 12 06:28:37 AM UTC 24 101485980 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2311325366 Oct 12 06:28:33 AM UTC 24 Oct 12 06:28:37 AM UTC 24 112941400 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.380244717 Oct 12 06:28:33 AM UTC 24 Oct 12 06:28:37 AM UTC 24 109631974 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.602011649 Oct 12 06:28:34 AM UTC 24 Oct 12 06:28:37 AM UTC 24 167700689 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.750014419 Oct 12 06:28:34 AM UTC 24 Oct 12 06:28:38 AM UTC 24 293780186 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2290986268 Oct 12 06:28:34 AM UTC 24 Oct 12 06:28:38 AM UTC 24 69599095 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.475011611 Oct 12 06:28:36 AM UTC 24 Oct 12 06:28:38 AM UTC 24 20912112 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2164328386 Oct 12 06:28:36 AM UTC 24 Oct 12 06:28:38 AM UTC 24 33349748 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.871414543 Oct 12 06:28:36 AM UTC 24 Oct 12 06:28:38 AM UTC 24 16432102 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1716621391 Oct 12 06:28:34 AM UTC 24 Oct 12 06:28:38 AM UTC 24 43320218 ps
T902 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1758666915 Oct 12 06:28:34 AM UTC 24 Oct 12 06:28:38 AM UTC 24 37666315 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1183723180 Oct 12 06:28:36 AM UTC 24 Oct 12 06:28:38 AM UTC 24 58057836 ps
T904 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3372850657 Oct 12 06:28:37 AM UTC 24 Oct 12 06:28:39 AM UTC 24 120909572 ps
T905 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.155338514 Oct 12 06:28:37 AM UTC 24 Oct 12 06:28:39 AM UTC 24 12127550 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2503952439 Oct 12 06:28:37 AM UTC 24 Oct 12 06:28:39 AM UTC 24 12737236 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.325818815 Oct 12 06:28:37 AM UTC 24 Oct 12 06:28:39 AM UTC 24 74794359 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1754786812 Oct 12 06:28:37 AM UTC 24 Oct 12 06:28:39 AM UTC 24 37129834 ps
T909 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2914116976 Oct 12 06:28:37 AM UTC 24 Oct 12 06:28:39 AM UTC 24 63071959 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.327606003 Oct 12 06:28:37 AM UTC 24 Oct 12 06:28:39 AM UTC 24 21795059 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.500956175 Oct 12 06:28:33 AM UTC 24 Oct 12 06:28:40 AM UTC 24 139779784 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3906953649 Oct 12 06:28:36 AM UTC 24 Oct 12 06:28:40 AM UTC 24 89696699 ps
T193 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.422327246 Oct 12 06:28:36 AM UTC 24 Oct 12 06:28:40 AM UTC 24 128299141 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2317285797 Oct 12 06:28:38 AM UTC 24 Oct 12 06:28:40 AM UTC 24 47430201 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2939306908 Oct 12 06:28:38 AM UTC 24 Oct 12 06:28:40 AM UTC 24 53640609 ps
T915 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.445500514 Oct 12 06:28:39 AM UTC 24 Oct 12 06:28:40 AM UTC 24 30024367 ps
T916 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.732630990 Oct 12 06:28:38 AM UTC 24 Oct 12 06:28:41 AM UTC 24 12911301 ps
T917 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.876358026 Oct 12 06:28:39 AM UTC 24 Oct 12 06:28:41 AM UTC 24 68850470 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1541634451 Oct 12 06:28:38 AM UTC 24 Oct 12 06:28:41 AM UTC 24 12898795 ps
T919 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1776671969 Oct 12 06:28:39 AM UTC 24 Oct 12 06:28:41 AM UTC 24 27060702 ps
T920 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1092582167 Oct 12 06:28:39 AM UTC 24 Oct 12 06:28:41 AM UTC 24 25006988 ps
T921 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3832634440 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 55487366 ps
T922 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.965404163 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 137074718 ps
T923 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.2579574943 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 14143430 ps
T924 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1125111390 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 69528072 ps
T925 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.3876915095 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 18005749 ps
T926 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3744874796 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 12197616 ps
T927 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.3833162244 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 18525151 ps
T928 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.975903281 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 27116127 ps
T929 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3142581240 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 52823890 ps
T930 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1115535033 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 38066328 ps
T931 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2183779150 Oct 12 06:28:40 AM UTC 24 Oct 12 06:28:42 AM UTC 24 13282704 ps
T932 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.636752637 Oct 12 06:28:42 AM UTC 24 Oct 12 06:28:44 AM UTC 24 15166923 ps
T933 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.2407884149 Oct 12 06:28:41 AM UTC 24 Oct 12 06:28:44 AM UTC 24 49246068 ps
T934 /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.1978156693 Oct 12 06:28:41 AM UTC 24 Oct 12 06:28:44 AM UTC 24 13327323 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload_invalid.2697000290
Short name T1
Test name
Test status
Simulation time 299468813 ps
CPU time 3.47 seconds
Started Oct 12 07:27:28 AM UTC 24
Finished Oct 12 07:27:32 AM UTC 24
Peak memory 237000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697000290 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload_invalid.2697000290 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_app.1221967157
Short name T51
Test name
Test status
Simulation time 7147833585 ps
CPU time 96.24 seconds
Started Oct 12 07:27:40 AM UTC 24
Finished Oct 12 07:29:18 AM UTC 24
Peak memory 262704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221967157 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1221967157 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.1912940168
Short name T138
Test name
Test status
Simulation time 371052187 ps
CPU time 4.32 seconds
Started Oct 12 06:27:43 AM UTC 24
Finished Oct 12 06:27:48 AM UTC 24
Peak memory 225780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912940168 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.1912940168 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.116975722
Short name T64
Test name
Test status
Simulation time 4305589165 ps
CPU time 78.02 seconds
Started Oct 12 07:27:24 AM UTC 24
Finished Oct 12 07:28:44 AM UTC 24
Peak memory 238148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116975722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.116975722 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.2533440364
Short name T43
Test name
Test status
Simulation time 6760453157 ps
CPU time 132.67 seconds
Started Oct 12 07:31:02 AM UTC 24
Finished Oct 12 07:33:17 AM UTC 24
Peak memory 300792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533440364 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2533440364 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.1014015652
Short name T29
Test name
Test status
Simulation time 11989195864 ps
CPU time 97.61 seconds
Started Oct 12 07:27:58 AM UTC 24
Finished Oct 12 07:29:38 AM UTC 24
Peak memory 264816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1014015652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_r
and_reset.1014015652 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.1394671733
Short name T40
Test name
Test status
Simulation time 1815778007 ps
CPU time 44.9 seconds
Started Oct 12 07:30:55 AM UTC 24
Finished Oct 12 07:31:41 AM UTC 24
Peak memory 252548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394671733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1394671733 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.513459341
Short name T90
Test name
Test status
Simulation time 269877234 ps
CPU time 1.96 seconds
Started Oct 12 07:47:40 AM UTC 24
Finished Oct 12 07:47:43 AM UTC 24
Peak memory 235912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513459341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.513459341 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.3125022139
Short name T4
Test name
Test status
Simulation time 3865407942 ps
CPU time 48.32 seconds
Started Oct 12 07:27:50 AM UTC 24
Finished Oct 12 07:28:40 AM UTC 24
Peak memory 236552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125022139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3125022139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload_invalid.2441168079
Short name T8
Test name
Test status
Simulation time 139883616 ps
CPU time 12.87 seconds
Started Oct 12 07:28:05 AM UTC 24
Finished Oct 12 07:28:19 AM UTC 24
Peak memory 237068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441168079 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload_invalid.2441168079 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1174769511
Short name T107
Test name
Test status
Simulation time 43887660 ps
CPU time 1.92 seconds
Started Oct 12 06:27:34 AM UTC 24
Finished Oct 12 06:27:37 AM UTC 24
Peak memory 225532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174769511 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.1174769511 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.3041228086
Short name T75
Test name
Test status
Simulation time 39242698327 ps
CPU time 302.59 seconds
Started Oct 12 07:32:09 AM UTC 24
Finished Oct 12 07:37:16 AM UTC 24
Peak memory 398104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041228086 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3041228086 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_error.733177802
Short name T20
Test name
Test status
Simulation time 17810213146 ps
CPU time 349.74 seconds
Started Oct 12 07:30:06 AM UTC 24
Finished Oct 12 07:36:01 AM UTC 24
Peak memory 352804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733177802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.733177802 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.767609528
Short name T141
Test name
Test status
Simulation time 23133703 ps
CPU time 1.18 seconds
Started Oct 12 06:27:38 AM UTC 24
Finished Oct 12 06:27:40 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767609528 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.767609528 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.3019278026
Short name T53
Test name
Test status
Simulation time 34818062 ps
CPU time 1.51 seconds
Started Oct 12 07:28:57 AM UTC 24
Finished Oct 12 07:28:59 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019278026 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3019278026 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.2844331488
Short name T73
Test name
Test status
Simulation time 1010384300 ps
CPU time 16.32 seconds
Started Oct 12 08:19:29 AM UTC 24
Finished Oct 12 08:19:47 AM UTC 24
Peak memory 248568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844331488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2844331488 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.2082398905
Short name T33
Test name
Test status
Simulation time 38951851232 ps
CPU time 200.75 seconds
Started Oct 12 07:28:44 AM UTC 24
Finished Oct 12 07:32:08 AM UTC 24
Peak memory 379800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082398905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2082398905 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.3478343697
Short name T47
Test name
Test status
Simulation time 49588276 ps
CPU time 1.32 seconds
Started Oct 12 07:27:50 AM UTC 24
Finished Oct 12 07:27:53 AM UTC 24
Peak memory 226752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478343697 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3478343697 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.478509692
Short name T17
Test name
Test status
Simulation time 126976513 ps
CPU time 1.95 seconds
Started Oct 12 07:28:58 AM UTC 24
Finished Oct 12 07:29:01 AM UTC 24
Peak memory 235848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478509692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.478509692 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.1945695637
Short name T56
Test name
Test status
Simulation time 40004841 ps
CPU time 2.31 seconds
Started Oct 12 07:49:07 AM UTC 24
Finished Oct 12 07:49:10 AM UTC 24
Peak memory 236488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945695637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1945695637 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1559920284
Short name T117
Test name
Test status
Simulation time 371376326 ps
CPU time 3.31 seconds
Started Oct 12 06:28:16 AM UTC 24
Finished Oct 12 06:28:21 AM UTC 24
Peak memory 227972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559920284 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.155
9920284 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.2315432928
Short name T89
Test name
Test status
Simulation time 135707279944 ps
CPU time 739.09 seconds
Started Oct 12 07:32:47 AM UTC 24
Finished Oct 12 07:45:15 AM UTC 24
Peak memory 510560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315432928 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2315432928 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.4075396114
Short name T151
Test name
Test status
Simulation time 37792833 ps
CPU time 1.79 seconds
Started Oct 12 06:27:43 AM UTC 24
Finished Oct 12 06:27:46 AM UTC 24
Peak memory 223840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075396114 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.4075396114 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.2601053522
Short name T74
Test name
Test status
Simulation time 1884416025 ps
CPU time 46 seconds
Started Oct 12 08:11:49 AM UTC 24
Finished Oct 12 08:12:37 AM UTC 24
Peak memory 264824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601053522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2601053522 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload_invalid.3575439985
Short name T16
Test name
Test status
Simulation time 106009511 ps
CPU time 4.08 seconds
Started Oct 12 08:11:12 AM UTC 24
Finished Oct 12 08:11:17 AM UTC 24
Peak memory 237068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575439985 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload_invalid.3575439985 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.3819681241
Short name T48
Test name
Test status
Simulation time 16498795 ps
CPU time 1.2 seconds
Started Oct 12 07:28:02 AM UTC 24
Finished Oct 12 07:28:05 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819681241 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.3819681241 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.1642997592
Short name T148
Test name
Test status
Simulation time 5488189415 ps
CPU time 185.09 seconds
Started Oct 12 07:27:33 AM UTC 24
Finished Oct 12 07:30:42 AM UTC 24
Peak memory 363104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642997592 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1642997592 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.1238883415
Short name T182
Test name
Test status
Simulation time 998732685 ps
CPU time 5.66 seconds
Started Oct 12 06:28:12 AM UTC 24
Finished Oct 12 06:28:19 AM UTC 24
Peak memory 225604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238883415 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.1238883415 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.88439540
Short name T87
Test name
Test status
Simulation time 35109904774 ps
CPU time 236.45 seconds
Started Oct 12 08:02:31 AM UTC 24
Finished Oct 12 08:06:31 AM UTC 24
Peak memory 379500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88439540 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.88439540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.2529871630
Short name T860
Test name
Test status
Simulation time 13587695 ps
CPU time 1.19 seconds
Started Oct 12 06:28:26 AM UTC 24
Finished Oct 12 06:28:28 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529871630 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.2529871630 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.2035845913
Short name T217
Test name
Test status
Simulation time 37701827317 ps
CPU time 475.28 seconds
Started Oct 12 07:28:28 AM UTC 24
Finished Oct 12 07:36:30 AM UTC 24
Peak memory 371340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035845913 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2035845913 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.1589249254
Short name T109
Test name
Test status
Simulation time 60699744 ps
CPU time 1.63 seconds
Started Oct 12 06:27:41 AM UTC 24
Finished Oct 12 06:27:44 AM UTC 24
Peak memory 228200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589249254 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.1589249254 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.2291395290
Short name T187
Test name
Test status
Simulation time 371361695 ps
CPU time 4.23 seconds
Started Oct 12 06:28:23 AM UTC 24
Finished Oct 12 06:28:28 AM UTC 24
Peak memory 225664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291395290 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.2291395290 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_error.1855972373
Short name T173
Test name
Test status
Simulation time 8330526987 ps
CPU time 214.23 seconds
Started Oct 12 07:40:23 AM UTC 24
Finished Oct 12 07:44:00 AM UTC 24
Peak memory 295524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855972373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1855972373 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.302618812
Short name T185
Test name
Test status
Simulation time 135078112 ps
CPU time 4.01 seconds
Started Oct 12 06:28:16 AM UTC 24
Finished Oct 12 06:28:22 AM UTC 24
Peak memory 225652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302618812 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.302618812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.3710795110
Short name T7
Test name
Test status
Simulation time 2478614935 ps
CPU time 6.61 seconds
Started Oct 12 07:27:46 AM UTC 24
Finished Oct 12 07:27:54 AM UTC 24
Peak memory 230128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710795110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3710795110 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1450544484
Short name T111
Test name
Test status
Simulation time 119358957 ps
CPU time 4.22 seconds
Started Oct 12 06:27:41 AM UTC 24
Finished Oct 12 06:27:47 AM UTC 24
Peak memory 225808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450544484 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.1450
544484 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.2904978190
Short name T791
Test name
Test status
Simulation time 715498690 ps
CPU time 6.86 seconds
Started Oct 12 06:27:48 AM UTC 24
Finished Oct 12 06:27:56 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904978190 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2904978190 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.3073998664
Short name T25
Test name
Test status
Simulation time 4054165824 ps
CPU time 53.71 seconds
Started Oct 12 07:27:48 AM UTC 24
Finished Oct 12 07:28:44 AM UTC 24
Peak memory 237992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073998664 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3073998664 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_error.814482646
Short name T36
Test name
Test status
Simulation time 27933571548 ps
CPU time 373.01 seconds
Started Oct 12 08:10:33 AM UTC 24
Finished Oct 12 08:16:51 AM UTC 24
Peak memory 543340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814482646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.814482646 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.1218448200
Short name T24
Test name
Test status
Simulation time 62389794586 ps
CPU time 431.93 seconds
Started Oct 12 07:27:55 AM UTC 24
Finished Oct 12 07:35:12 AM UTC 24
Peak memory 537324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218448200 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.1218448200 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.1801293405
Short name T783
Test name
Test status
Simulation time 76871537 ps
CPU time 4.87 seconds
Started Oct 12 06:27:39 AM UTC 24
Finished Oct 12 06:27:45 AM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801293405 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1801293405 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.2815605622
Short name T802
Test name
Test status
Simulation time 1440115423 ps
CPU time 22.56 seconds
Started Oct 12 06:27:39 AM UTC 24
Finished Oct 12 06:28:03 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815605622 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2815605622 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.2515840486
Short name T142
Test name
Test status
Simulation time 25733800 ps
CPU time 1.74 seconds
Started Oct 12 06:27:38 AM UTC 24
Finished Oct 12 06:27:41 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515840486 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2515840486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.325462508
Short name T145
Test name
Test status
Simulation time 144540445 ps
CPU time 3.86 seconds
Started Oct 12 06:27:41 AM UTC 24
Finished Oct 12 06:27:46 AM UTC 24
Peak memory 231784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=325462508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_r
w_with_rand_reset.325462508 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.772350395
Short name T194
Test name
Test status
Simulation time 87322472 ps
CPU time 1.29 seconds
Started Oct 12 06:27:39 AM UTC 24
Finished Oct 12 06:27:41 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772350395 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.772350395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.1514359767
Short name T780
Test name
Test status
Simulation time 26874869 ps
CPU time 1.78 seconds
Started Oct 12 06:27:36 AM UTC 24
Finished Oct 12 06:27:38 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514359767 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.1514359767 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.925503516
Short name T779
Test name
Test status
Simulation time 30195162 ps
CPU time 1.25 seconds
Started Oct 12 06:27:35 AM UTC 24
Finished Oct 12 06:27:38 AM UTC 24
Peak memory 223940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925503516 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.925503516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1811699620
Short name T781
Test name
Test status
Simulation time 38216657 ps
CPU time 2.34 seconds
Started Oct 12 06:27:40 AM UTC 24
Finished Oct 12 06:27:44 AM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811699620 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1811699620 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1446466484
Short name T108
Test name
Test status
Simulation time 63678070 ps
CPU time 2.46 seconds
Started Oct 12 06:27:34 AM UTC 24
Finished Oct 12 06:27:38 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446466484 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.1446
466484 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.2673988176
Short name T144
Test name
Test status
Simulation time 72890563 ps
CPU time 3.55 seconds
Started Oct 12 06:27:37 AM UTC 24
Finished Oct 12 06:27:41 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673988176 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2673988176 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.759030701
Short name T137
Test name
Test status
Simulation time 214117259 ps
CPU time 3.65 seconds
Started Oct 12 06:27:37 AM UTC 24
Finished Oct 12 06:27:41 AM UTC 24
Peak memory 225592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759030701 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.759030701 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.365726898
Short name T166
Test name
Test status
Simulation time 944656195 ps
CPU time 10.99 seconds
Started Oct 12 06:27:45 AM UTC 24
Finished Oct 12 06:27:57 AM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365726898 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.365726898 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2220553511
Short name T165
Test name
Test status
Simulation time 646091360 ps
CPU time 10.86 seconds
Started Oct 12 06:27:45 AM UTC 24
Finished Oct 12 06:27:57 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220553511 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2220553511 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2167301001
Short name T785
Test name
Test status
Simulation time 19836216 ps
CPU time 1.75 seconds
Started Oct 12 06:27:44 AM UTC 24
Finished Oct 12 06:27:47 AM UTC 24
Peak memory 223868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167301001 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2167301001 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3335034928
Short name T149
Test name
Test status
Simulation time 80826017 ps
CPU time 2.47 seconds
Started Oct 12 06:27:46 AM UTC 24
Finished Oct 12 06:27:50 AM UTC 24
Peak memory 231792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3335034928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_
rw_with_rand_reset.3335034928 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.2048237289
Short name T784
Test name
Test status
Simulation time 17835911 ps
CPU time 1.11 seconds
Started Oct 12 06:27:44 AM UTC 24
Finished Oct 12 06:27:46 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048237289 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2048237289 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.2737129659
Short name T174
Test name
Test status
Simulation time 33496789 ps
CPU time 1.23 seconds
Started Oct 12 06:27:43 AM UTC 24
Finished Oct 12 06:27:45 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737129659 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2737129659 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.1745556560
Short name T782
Test name
Test status
Simulation time 18220247 ps
CPU time 1.12 seconds
Started Oct 12 06:27:42 AM UTC 24
Finished Oct 12 06:27:44 AM UTC 24
Peak memory 223940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745556560 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1745556560 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1890248321
Short name T786
Test name
Test status
Simulation time 34849269 ps
CPU time 2.27 seconds
Started Oct 12 06:27:45 AM UTC 24
Finished Oct 12 06:27:49 AM UTC 24
Peak memory 225588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890248321 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.1890248321 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.812996650
Short name T146
Test name
Test status
Simulation time 289390319 ps
CPU time 4.49 seconds
Started Oct 12 06:27:43 AM UTC 24
Finished Oct 12 06:27:48 AM UTC 24
Peak memory 225780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812996650 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.812996650 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3053501699
Short name T841
Test name
Test status
Simulation time 469062128 ps
CPU time 2.87 seconds
Started Oct 12 06:28:18 AM UTC 24
Finished Oct 12 06:28:22 AM UTC 24
Peak memory 229744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3053501699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem
_rw_with_rand_reset.3053501699 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.1164640165
Short name T839
Test name
Test status
Simulation time 52213473 ps
CPU time 1.87 seconds
Started Oct 12 06:28:18 AM UTC 24
Finished Oct 12 06:28:21 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164640165 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1164640165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.2970717965
Short name T835
Test name
Test status
Simulation time 42810570 ps
CPU time 1.29 seconds
Started Oct 12 06:28:18 AM UTC 24
Finished Oct 12 06:28:20 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970717965 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2970717965 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3700201750
Short name T840
Test name
Test status
Simulation time 70773718 ps
CPU time 2.25 seconds
Started Oct 12 06:28:18 AM UTC 24
Finished Oct 12 06:28:21 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700201750 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.3700201750 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.585311904
Short name T119
Test name
Test status
Simulation time 31987226 ps
CPU time 1.59 seconds
Started Oct 12 06:28:16 AM UTC 24
Finished Oct 12 06:28:19 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585311904 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.585311904 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.1901670233
Short name T836
Test name
Test status
Simulation time 26232109 ps
CPU time 2.54 seconds
Started Oct 12 06:28:16 AM UTC 24
Finished Oct 12 06:28:20 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901670233 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1901670233 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1413252400
Short name T847
Test name
Test status
Simulation time 242964166 ps
CPU time 2.53 seconds
Started Oct 12 06:28:20 AM UTC 24
Finished Oct 12 06:28:24 AM UTC 24
Peak memory 231980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1413252400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem
_rw_with_rand_reset.1413252400 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.3409917922
Short name T843
Test name
Test status
Simulation time 20406867 ps
CPU time 1.49 seconds
Started Oct 12 06:28:20 AM UTC 24
Finished Oct 12 06:28:23 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409917922 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3409917922 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.3111221030
Short name T842
Test name
Test status
Simulation time 20110749 ps
CPU time 0.99 seconds
Started Oct 12 06:28:20 AM UTC 24
Finished Oct 12 06:28:22 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111221030 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3111221030 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3241436996
Short name T849
Test name
Test status
Simulation time 244450304 ps
CPU time 2.92 seconds
Started Oct 12 06:28:20 AM UTC 24
Finished Oct 12 06:28:24 AM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241436996 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.3241436996 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1935632248
Short name T837
Test name
Test status
Simulation time 69137729 ps
CPU time 1.33 seconds
Started Oct 12 06:28:18 AM UTC 24
Finished Oct 12 06:28:20 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935632248 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1935632248 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.985818643
Short name T844
Test name
Test status
Simulation time 169791075 ps
CPU time 3.06 seconds
Started Oct 12 06:28:19 AM UTC 24
Finished Oct 12 06:28:23 AM UTC 24
Peak memory 230156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985818643 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.9858
18643 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2165949370
Short name T851
Test name
Test status
Simulation time 66925658 ps
CPU time 4.38 seconds
Started Oct 12 06:28:19 AM UTC 24
Finished Oct 12 06:28:25 AM UTC 24
Peak memory 225956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165949370 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2165949370 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.1064716403
Short name T183
Test name
Test status
Simulation time 104119029 ps
CPU time 2.89 seconds
Started Oct 12 06:28:19 AM UTC 24
Finished Oct 12 06:28:23 AM UTC 24
Peak memory 225656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064716403 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.1064716403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.138372528
Short name T856
Test name
Test status
Simulation time 127713426 ps
CPU time 2.8 seconds
Started Oct 12 06:28:22 AM UTC 24
Finished Oct 12 06:28:26 AM UTC 24
Peak memory 231784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=138372528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_
rw_with_rand_reset.138372528 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.1198060788
Short name T848
Test name
Test status
Simulation time 32280236 ps
CPU time 1.59 seconds
Started Oct 12 06:28:22 AM UTC 24
Finished Oct 12 06:28:24 AM UTC 24
Peak memory 223936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198060788 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1198060788 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.1226158194
Short name T845
Test name
Test status
Simulation time 23329935 ps
CPU time 1.27 seconds
Started Oct 12 06:28:22 AM UTC 24
Finished Oct 12 06:28:24 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226158194 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1226158194 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1659539339
Short name T857
Test name
Test status
Simulation time 109940662 ps
CPU time 3.54 seconds
Started Oct 12 06:28:22 AM UTC 24
Finished Oct 12 06:28:26 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659539339 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.1659539339 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4210330136
Short name T118
Test name
Test status
Simulation time 254145808 ps
CPU time 1.76 seconds
Started Oct 12 06:28:20 AM UTC 24
Finished Oct 12 06:28:23 AM UTC 24
Peak memory 228348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210330136 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.4210330136 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1279377382
Short name T846
Test name
Test status
Simulation time 78584435 ps
CPU time 2.31 seconds
Started Oct 12 06:28:20 AM UTC 24
Finished Oct 12 06:28:24 AM UTC 24
Peak memory 230332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279377382 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.127
9377382 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.3365637704
Short name T859
Test name
Test status
Simulation time 477825908 ps
CPU time 5.93 seconds
Started Oct 12 06:28:20 AM UTC 24
Finished Oct 12 06:28:28 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365637704 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3365637704 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.2286398298
Short name T855
Test name
Test status
Simulation time 478867674 ps
CPU time 2.96 seconds
Started Oct 12 06:28:22 AM UTC 24
Finished Oct 12 06:28:26 AM UTC 24
Peak memory 225580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286398298 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2286398298 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2943272749
Short name T878
Test name
Test status
Simulation time 82422878 ps
CPU time 3.11 seconds
Started Oct 12 06:28:24 AM UTC 24
Finished Oct 12 06:28:32 AM UTC 24
Peak memory 231788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2943272749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem
_rw_with_rand_reset.2943272749 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3717491659
Short name T852
Test name
Test status
Simulation time 14432244 ps
CPU time 1.15 seconds
Started Oct 12 06:28:23 AM UTC 24
Finished Oct 12 06:28:25 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717491659 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3717491659 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.925411290
Short name T854
Test name
Test status
Simulation time 16276345 ps
CPU time 1.31 seconds
Started Oct 12 06:28:23 AM UTC 24
Finished Oct 12 06:28:26 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925411290 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.925411290 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1982027323
Short name T866
Test name
Test status
Simulation time 124902697 ps
CPU time 3.25 seconds
Started Oct 12 06:28:24 AM UTC 24
Finished Oct 12 06:28:30 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982027323 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.1982027323 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3983887873
Short name T850
Test name
Test status
Simulation time 101813101 ps
CPU time 1.64 seconds
Started Oct 12 06:28:22 AM UTC 24
Finished Oct 12 06:28:25 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983887873 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.3983887873 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1633053480
Short name T853
Test name
Test status
Simulation time 218003833 ps
CPU time 2.55 seconds
Started Oct 12 06:28:22 AM UTC 24
Finished Oct 12 06:28:25 AM UTC 24
Peak memory 230092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633053480 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.163
3053480 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.3727319294
Short name T858
Test name
Test status
Simulation time 128859783 ps
CPU time 3.35 seconds
Started Oct 12 06:28:22 AM UTC 24
Finished Oct 12 06:28:26 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727319294 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3727319294 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.682560331
Short name T872
Test name
Test status
Simulation time 311842998 ps
CPU time 3.36 seconds
Started Oct 12 06:28:26 AM UTC 24
Finished Oct 12 06:28:31 AM UTC 24
Peak memory 231792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=682560331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_
rw_with_rand_reset.682560331 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.1481566246
Short name T864
Test name
Test status
Simulation time 60071098 ps
CPU time 1.43 seconds
Started Oct 12 06:28:26 AM UTC 24
Finished Oct 12 06:28:29 AM UTC 24
Peak memory 223936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481566246 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1481566246 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.626964012
Short name T868
Test name
Test status
Simulation time 162695522 ps
CPU time 3.16 seconds
Started Oct 12 06:28:26 AM UTC 24
Finished Oct 12 06:28:30 AM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626964012 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.626964012 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.660869807
Short name T861
Test name
Test status
Simulation time 29771668 ps
CPU time 1.4 seconds
Started Oct 12 06:28:25 AM UTC 24
Finished Oct 12 06:28:28 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660869807 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.660869807 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.422103990
Short name T877
Test name
Test status
Simulation time 57676012 ps
CPU time 2.96 seconds
Started Oct 12 06:28:25 AM UTC 24
Finished Oct 12 06:28:32 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422103990 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.4221
03990 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.2952987002
Short name T862
Test name
Test status
Simulation time 301480859 ps
CPU time 2.52 seconds
Started Oct 12 06:28:25 AM UTC 24
Finished Oct 12 06:28:28 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952987002 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2952987002 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.1681987157
Short name T191
Test name
Test status
Simulation time 3656412048 ps
CPU time 6.83 seconds
Started Oct 12 06:28:25 AM UTC 24
Finished Oct 12 06:28:33 AM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681987157 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1681987157 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.788644739
Short name T869
Test name
Test status
Simulation time 72737537 ps
CPU time 1.79 seconds
Started Oct 12 06:28:28 AM UTC 24
Finished Oct 12 06:28:30 AM UTC 24
Peak memory 225924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=788644739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_
rw_with_rand_reset.788644739 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.120580046
Short name T867
Test name
Test status
Simulation time 29874419 ps
CPU time 1.32 seconds
Started Oct 12 06:28:27 AM UTC 24
Finished Oct 12 06:28:30 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120580046 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.120580046 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.4019962574
Short name T865
Test name
Test status
Simulation time 19691559 ps
CPU time 1.24 seconds
Started Oct 12 06:28:27 AM UTC 24
Finished Oct 12 06:28:30 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019962574 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.4019962574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1538964649
Short name T876
Test name
Test status
Simulation time 99462268 ps
CPU time 3.15 seconds
Started Oct 12 06:28:28 AM UTC 24
Finished Oct 12 06:28:32 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538964649 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.1538964649 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2529924575
Short name T863
Test name
Test status
Simulation time 74186330 ps
CPU time 1.18 seconds
Started Oct 12 06:28:26 AM UTC 24
Finished Oct 12 06:28:28 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529924575 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.2529924575 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2723443738
Short name T871
Test name
Test status
Simulation time 108567625 ps
CPU time 2.23 seconds
Started Oct 12 06:28:27 AM UTC 24
Finished Oct 12 06:28:31 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723443738 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.272
3443738 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.2407090123
Short name T873
Test name
Test status
Simulation time 291778365 ps
CPU time 2.35 seconds
Started Oct 12 06:28:27 AM UTC 24
Finished Oct 12 06:28:31 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407090123 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2407090123 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2158988552
Short name T192
Test name
Test status
Simulation time 396713626 ps
CPU time 5.13 seconds
Started Oct 12 06:28:27 AM UTC 24
Finished Oct 12 06:28:34 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158988552 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2158988552 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.175357294
Short name T885
Test name
Test status
Simulation time 139734380 ps
CPU time 2.97 seconds
Started Oct 12 06:28:30 AM UTC 24
Finished Oct 12 06:28:34 AM UTC 24
Peak memory 231788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=175357294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_
rw_with_rand_reset.175357294 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.3194756392
Short name T879
Test name
Test status
Simulation time 36424162 ps
CPU time 1.26 seconds
Started Oct 12 06:28:30 AM UTC 24
Finished Oct 12 06:28:32 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194756392 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.3194756392 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3582193881
Short name T874
Test name
Test status
Simulation time 24550899 ps
CPU time 0.84 seconds
Started Oct 12 06:28:29 AM UTC 24
Finished Oct 12 06:28:31 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582193881 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3582193881 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.883023414
Short name T881
Test name
Test status
Simulation time 79287454 ps
CPU time 2.3 seconds
Started Oct 12 06:28:30 AM UTC 24
Finished Oct 12 06:28:33 AM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883023414 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.883023414 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.813603631
Short name T875
Test name
Test status
Simulation time 31709858 ps
CPU time 1.07 seconds
Started Oct 12 06:28:29 AM UTC 24
Finished Oct 12 06:28:31 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813603631 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.813603631 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3055948544
Short name T880
Test name
Test status
Simulation time 87749067 ps
CPU time 3.21 seconds
Started Oct 12 06:28:29 AM UTC 24
Finished Oct 12 06:28:33 AM UTC 24
Peak memory 230040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055948544 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.305
5948544 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.3482578208
Short name T884
Test name
Test status
Simulation time 114546517 ps
CPU time 4.08 seconds
Started Oct 12 06:28:29 AM UTC 24
Finished Oct 12 06:28:34 AM UTC 24
Peak memory 225908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482578208 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3482578208 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.2896154298
Short name T888
Test name
Test status
Simulation time 350491223 ps
CPU time 5.53 seconds
Started Oct 12 06:28:29 AM UTC 24
Finished Oct 12 06:28:36 AM UTC 24
Peak memory 225812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896154298 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2896154298 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1831897040
Short name T887
Test name
Test status
Simulation time 403904351 ps
CPU time 2.48 seconds
Started Oct 12 06:28:32 AM UTC 24
Finished Oct 12 06:28:35 AM UTC 24
Peak memory 231868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1831897040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem
_rw_with_rand_reset.1831897040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3687447931
Short name T883
Test name
Test status
Simulation time 77752737 ps
CPU time 1.33 seconds
Started Oct 12 06:28:32 AM UTC 24
Finished Oct 12 06:28:34 AM UTC 24
Peak memory 223936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687447931 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3687447931 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2127811181
Short name T882
Test name
Test status
Simulation time 17153303 ps
CPU time 1.04 seconds
Started Oct 12 06:28:31 AM UTC 24
Finished Oct 12 06:28:34 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127811181 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2127811181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2599873614
Short name T891
Test name
Test status
Simulation time 545178637 ps
CPU time 3.64 seconds
Started Oct 12 06:28:32 AM UTC 24
Finished Oct 12 06:28:36 AM UTC 24
Peak memory 225656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599873614 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2599873614 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.970742248
Short name T870
Test name
Test status
Simulation time 58405248 ps
CPU time 2.3 seconds
Started Oct 12 06:28:31 AM UTC 24
Finished Oct 12 06:28:35 AM UTC 24
Peak memory 228008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970742248 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.970742248 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.786058402
Short name T889
Test name
Test status
Simulation time 77139208 ps
CPU time 3.26 seconds
Started Oct 12 06:28:31 AM UTC 24
Finished Oct 12 06:28:36 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786058402 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.7860
58402 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.4252695076
Short name T892
Test name
Test status
Simulation time 101485980 ps
CPU time 4.14 seconds
Started Oct 12 06:28:31 AM UTC 24
Finished Oct 12 06:28:37 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252695076 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.4252695076 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.806496584
Short name T188
Test name
Test status
Simulation time 123346761 ps
CPU time 3.73 seconds
Started Oct 12 06:28:31 AM UTC 24
Finished Oct 12 06:28:36 AM UTC 24
Peak memory 225588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806496584 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.806496584 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.750014419
Short name T896
Test name
Test status
Simulation time 293780186 ps
CPU time 2.32 seconds
Started Oct 12 06:28:34 AM UTC 24
Finished Oct 12 06:28:38 AM UTC 24
Peak memory 231788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=750014419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_
rw_with_rand_reset.750014419 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.430902419
Short name T890
Test name
Test status
Simulation time 17629072 ps
CPU time 1.72 seconds
Started Oct 12 06:28:33 AM UTC 24
Finished Oct 12 06:28:36 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430902419 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.430902419 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.2874857862
Short name T824
Test name
Test status
Simulation time 24432255 ps
CPU time 1.07 seconds
Started Oct 12 06:28:33 AM UTC 24
Finished Oct 12 06:28:35 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874857862 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2874857862 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1758666915
Short name T902
Test name
Test status
Simulation time 37666315 ps
CPU time 3.07 seconds
Started Oct 12 06:28:34 AM UTC 24
Finished Oct 12 06:28:38 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758666915 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.1758666915 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2415977720
Short name T886
Test name
Test status
Simulation time 37346928 ps
CPU time 1.47 seconds
Started Oct 12 06:28:32 AM UTC 24
Finished Oct 12 06:28:34 AM UTC 24
Peak memory 228288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415977720 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.2415977720 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2311325366
Short name T893
Test name
Test status
Simulation time 112941400 ps
CPU time 2.78 seconds
Started Oct 12 06:28:33 AM UTC 24
Finished Oct 12 06:28:37 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311325366 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.231
1325366 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.500956175
Short name T911
Test name
Test status
Simulation time 139779784 ps
CPU time 5.43 seconds
Started Oct 12 06:28:33 AM UTC 24
Finished Oct 12 06:28:40 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500956175 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.500956175 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.380244717
Short name T894
Test name
Test status
Simulation time 109631974 ps
CPU time 3.17 seconds
Started Oct 12 06:28:33 AM UTC 24
Finished Oct 12 06:28:37 AM UTC 24
Peak memory 225652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380244717 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.380244717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3906953649
Short name T912
Test name
Test status
Simulation time 89696699 ps
CPU time 2.87 seconds
Started Oct 12 06:28:36 AM UTC 24
Finished Oct 12 06:28:40 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3906953649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem
_rw_with_rand_reset.3906953649 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.871414543
Short name T900
Test name
Test status
Simulation time 16432102 ps
CPU time 1.53 seconds
Started Oct 12 06:28:36 AM UTC 24
Finished Oct 12 06:28:38 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871414543 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.871414543 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.475011611
Short name T898
Test name
Test status
Simulation time 20912112 ps
CPU time 1.26 seconds
Started Oct 12 06:28:36 AM UTC 24
Finished Oct 12 06:28:38 AM UTC 24
Peak memory 223704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475011611 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.475011611 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1183723180
Short name T903
Test name
Test status
Simulation time 58057836 ps
CPU time 1.83 seconds
Started Oct 12 06:28:36 AM UTC 24
Finished Oct 12 06:28:38 AM UTC 24
Peak memory 223992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183723180 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.1183723180 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.602011649
Short name T895
Test name
Test status
Simulation time 167700689 ps
CPU time 2.14 seconds
Started Oct 12 06:28:34 AM UTC 24
Finished Oct 12 06:28:37 AM UTC 24
Peak memory 228056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602011649 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.602011649 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2290986268
Short name T897
Test name
Test status
Simulation time 69599095 ps
CPU time 2.46 seconds
Started Oct 12 06:28:34 AM UTC 24
Finished Oct 12 06:28:38 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290986268 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.229
0986268 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.1716621391
Short name T901
Test name
Test status
Simulation time 43320218 ps
CPU time 3 seconds
Started Oct 12 06:28:34 AM UTC 24
Finished Oct 12 06:28:38 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716621391 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.1716621391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.422327246
Short name T193
Test name
Test status
Simulation time 128299141 ps
CPU time 3.32 seconds
Started Oct 12 06:28:36 AM UTC 24
Finished Oct 12 06:28:40 AM UTC 24
Peak memory 225372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422327246 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.422327246 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.3661946229
Short name T168
Test name
Test status
Simulation time 8654957071 ps
CPU time 14.07 seconds
Started Oct 12 06:27:50 AM UTC 24
Finished Oct 12 06:28:05 AM UTC 24
Peak memory 225812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661946229 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3661946229 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1353758087
Short name T818
Test name
Test status
Simulation time 10648651288 ps
CPU time 21.48 seconds
Started Oct 12 06:27:50 AM UTC 24
Finished Oct 12 06:28:13 AM UTC 24
Peak memory 225892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353758087 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1353758087 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.3222886618
Short name T163
Test name
Test status
Simulation time 100760070 ps
CPU time 1.35 seconds
Started Oct 12 06:27:49 AM UTC 24
Finished Oct 12 06:27:51 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222886618 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3222886618 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.2984754446
Short name T790
Test name
Test status
Simulation time 132584164 ps
CPU time 2.75 seconds
Started Oct 12 06:27:51 AM UTC 24
Finished Oct 12 06:27:55 AM UTC 24
Peak memory 231796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2984754446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_
rw_with_rand_reset.2984754446 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.1453694035
Short name T788
Test name
Test status
Simulation time 68028612 ps
CPU time 1.45 seconds
Started Oct 12 06:27:50 AM UTC 24
Finished Oct 12 06:27:52 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453694035 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1453694035 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.3931940530
Short name T177
Test name
Test status
Simulation time 16347697 ps
CPU time 1.3 seconds
Started Oct 12 06:27:49 AM UTC 24
Finished Oct 12 06:27:51 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931940530 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.3931940530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.2160890775
Short name T152
Test name
Test status
Simulation time 155868595 ps
CPU time 2.36 seconds
Started Oct 12 06:27:48 AM UTC 24
Finished Oct 12 06:27:51 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160890775 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.2160890775 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.2754916608
Short name T787
Test name
Test status
Simulation time 18114878 ps
CPU time 1.07 seconds
Started Oct 12 06:27:48 AM UTC 24
Finished Oct 12 06:27:50 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754916608 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.2754916608 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2509857255
Short name T164
Test name
Test status
Simulation time 64345396 ps
CPU time 2.76 seconds
Started Oct 12 06:27:51 AM UTC 24
Finished Oct 12 06:27:55 AM UTC 24
Peak memory 225644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509857255 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.2509857255 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3227749323
Short name T113
Test name
Test status
Simulation time 163284958 ps
CPU time 1.93 seconds
Started Oct 12 06:27:46 AM UTC 24
Finished Oct 12 06:27:49 AM UTC 24
Peak memory 228244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227749323 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.3227749323 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2695240840
Short name T122
Test name
Test status
Simulation time 104579776 ps
CPU time 3.09 seconds
Started Oct 12 06:27:47 AM UTC 24
Finished Oct 12 06:27:51 AM UTC 24
Peak memory 230312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695240840 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.2695
240840 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.1028232055
Short name T139
Test name
Test status
Simulation time 104989548 ps
CPU time 3.79 seconds
Started Oct 12 06:27:48 AM UTC 24
Finished Oct 12 06:27:53 AM UTC 24
Peak memory 225592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028232055 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.1028232055 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.2164328386
Short name T899
Test name
Test status
Simulation time 33349748 ps
CPU time 1.11 seconds
Started Oct 12 06:28:36 AM UTC 24
Finished Oct 12 06:28:38 AM UTC 24
Peak memory 223920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164328386 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2164328386 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.155338514
Short name T905
Test name
Test status
Simulation time 12127550 ps
CPU time 1.1 seconds
Started Oct 12 06:28:37 AM UTC 24
Finished Oct 12 06:28:39 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155338514 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.155338514 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2914116976
Short name T909
Test name
Test status
Simulation time 63071959 ps
CPU time 1.32 seconds
Started Oct 12 06:28:37 AM UTC 24
Finished Oct 12 06:28:39 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914116976 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2914116976 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2503952439
Short name T906
Test name
Test status
Simulation time 12737236 ps
CPU time 1.04 seconds
Started Oct 12 06:28:37 AM UTC 24
Finished Oct 12 06:28:39 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503952439 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2503952439 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3372850657
Short name T904
Test name
Test status
Simulation time 120909572 ps
CPU time 0.93 seconds
Started Oct 12 06:28:37 AM UTC 24
Finished Oct 12 06:28:39 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372850657 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3372850657 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1754786812
Short name T908
Test name
Test status
Simulation time 37129834 ps
CPU time 1.12 seconds
Started Oct 12 06:28:37 AM UTC 24
Finished Oct 12 06:28:39 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754786812 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1754786812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.327606003
Short name T910
Test name
Test status
Simulation time 21795059 ps
CPU time 1.25 seconds
Started Oct 12 06:28:37 AM UTC 24
Finished Oct 12 06:28:39 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327606003 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.327606003 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.325818815
Short name T907
Test name
Test status
Simulation time 74794359 ps
CPU time 1.02 seconds
Started Oct 12 06:28:37 AM UTC 24
Finished Oct 12 06:28:39 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325818815 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.325818815 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2939306908
Short name T914
Test name
Test status
Simulation time 53640609 ps
CPU time 1.02 seconds
Started Oct 12 06:28:38 AM UTC 24
Finished Oct 12 06:28:40 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939306908 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2939306908 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2317285797
Short name T913
Test name
Test status
Simulation time 47430201 ps
CPU time 0.96 seconds
Started Oct 12 06:28:38 AM UTC 24
Finished Oct 12 06:28:40 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317285797 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2317285797 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.983763093
Short name T811
Test name
Test status
Simulation time 2265668314 ps
CPU time 12.2 seconds
Started Oct 12 06:27:56 AM UTC 24
Finished Oct 12 06:28:10 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983763093 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.983763093 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2009085647
Short name T831
Test name
Test status
Simulation time 4378578690 ps
CPU time 20.87 seconds
Started Oct 12 06:27:56 AM UTC 24
Finished Oct 12 06:28:19 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009085647 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2009085647 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.1819476277
Short name T794
Test name
Test status
Simulation time 23258403 ps
CPU time 1.54 seconds
Started Oct 12 06:27:56 AM UTC 24
Finished Oct 12 06:27:59 AM UTC 24
Peak memory 223868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819476277 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1819476277 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.283393612
Short name T800
Test name
Test status
Simulation time 149257493 ps
CPU time 3.58 seconds
Started Oct 12 06:27:57 AM UTC 24
Finished Oct 12 06:28:02 AM UTC 24
Peak memory 227372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=283393612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_r
w_with_rand_reset.283393612 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.353795989
Short name T795
Test name
Test status
Simulation time 16929612 ps
CPU time 1.66 seconds
Started Oct 12 06:27:56 AM UTC 24
Finished Oct 12 06:27:59 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353795989 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.353795989 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.4219148135
Short name T178
Test name
Test status
Simulation time 15810285 ps
CPU time 1.28 seconds
Started Oct 12 06:27:55 AM UTC 24
Finished Oct 12 06:27:57 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219148135 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.4219148135 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.222904896
Short name T153
Test name
Test status
Simulation time 72133912 ps
CPU time 1.68 seconds
Started Oct 12 06:27:54 AM UTC 24
Finished Oct 12 06:27:56 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222904896 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.222904896 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.513607949
Short name T789
Test name
Test status
Simulation time 45884311 ps
CPU time 1.17 seconds
Started Oct 12 06:27:53 AM UTC 24
Finished Oct 12 06:27:55 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513607949 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.513607949 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1149281783
Short name T796
Test name
Test status
Simulation time 140969503 ps
CPU time 2.61 seconds
Started Oct 12 06:27:56 AM UTC 24
Finished Oct 12 06:28:00 AM UTC 24
Peak memory 225844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149281783 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.1149281783 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.441830899
Short name T110
Test name
Test status
Simulation time 24618519 ps
CPU time 1.83 seconds
Started Oct 12 06:27:52 AM UTC 24
Finished Oct 12 06:27:55 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441830899 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.441830899 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3016302728
Short name T112
Test name
Test status
Simulation time 209773366 ps
CPU time 2.7 seconds
Started Oct 12 06:27:53 AM UTC 24
Finished Oct 12 06:27:56 AM UTC 24
Peak memory 229452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016302728 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.3016
302728 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.589171887
Short name T792
Test name
Test status
Simulation time 68340644 ps
CPU time 2.1 seconds
Started Oct 12 06:27:54 AM UTC 24
Finished Oct 12 06:27:57 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589171887 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.589171887 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1764046885
Short name T181
Test name
Test status
Simulation time 192108646 ps
CPU time 3.39 seconds
Started Oct 12 06:27:54 AM UTC 24
Finished Oct 12 06:27:58 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764046885 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1764046885 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1541634451
Short name T918
Test name
Test status
Simulation time 12898795 ps
CPU time 1.19 seconds
Started Oct 12 06:28:38 AM UTC 24
Finished Oct 12 06:28:41 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541634451 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1541634451 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.732630990
Short name T916
Test name
Test status
Simulation time 12911301 ps
CPU time 1.07 seconds
Started Oct 12 06:28:38 AM UTC 24
Finished Oct 12 06:28:41 AM UTC 24
Peak memory 223828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732630990 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.732630990 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.1776671969
Short name T919
Test name
Test status
Simulation time 27060702 ps
CPU time 1.08 seconds
Started Oct 12 06:28:39 AM UTC 24
Finished Oct 12 06:28:41 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776671969 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.1776671969 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.445500514
Short name T915
Test name
Test status
Simulation time 30024367 ps
CPU time 0.99 seconds
Started Oct 12 06:28:39 AM UTC 24
Finished Oct 12 06:28:40 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445500514 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.445500514 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.876358026
Short name T917
Test name
Test status
Simulation time 68850470 ps
CPU time 0.95 seconds
Started Oct 12 06:28:39 AM UTC 24
Finished Oct 12 06:28:41 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876358026 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.876358026 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1092582167
Short name T920
Test name
Test status
Simulation time 25006988 ps
CPU time 1.07 seconds
Started Oct 12 06:28:39 AM UTC 24
Finished Oct 12 06:28:41 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092582167 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1092582167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.1125111390
Short name T924
Test name
Test status
Simulation time 69528072 ps
CPU time 1.25 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125111390 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.1125111390 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.3832634440
Short name T921
Test name
Test status
Simulation time 55487366 ps
CPU time 0.89 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832634440 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.3832634440 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.965404163
Short name T922
Test name
Test status
Simulation time 137074718 ps
CPU time 1.05 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 223832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965404163 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.965404163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.2579574943
Short name T923
Test name
Test status
Simulation time 14143430 ps
CPU time 1.05 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579574943 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.2579574943 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.3821381165
Short name T814
Test name
Test status
Simulation time 519785867 ps
CPU time 9.16 seconds
Started Oct 12 06:28:01 AM UTC 24
Finished Oct 12 06:28:12 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821381165 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3821381165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.67692208
Short name T819
Test name
Test status
Simulation time 666267292 ps
CPU time 12.18 seconds
Started Oct 12 06:28:01 AM UTC 24
Finished Oct 12 06:28:15 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67692208 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.67692208 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.4093192357
Short name T167
Test name
Test status
Simulation time 20261715 ps
CPU time 1.52 seconds
Started Oct 12 06:28:00 AM UTC 24
Finished Oct 12 06:28:03 AM UTC 24
Peak memory 223672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093192357 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.4093192357 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2536118040
Short name T807
Test name
Test status
Simulation time 78441763 ps
CPU time 3.47 seconds
Started Oct 12 06:28:02 AM UTC 24
Finished Oct 12 06:28:07 AM UTC 24
Peak memory 231796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2536118040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_
rw_with_rand_reset.2536118040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.1805011160
Short name T801
Test name
Test status
Simulation time 18203318 ps
CPU time 1.31 seconds
Started Oct 12 06:28:00 AM UTC 24
Finished Oct 12 06:28:03 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805011160 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1805011160 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.2179704918
Short name T169
Test name
Test status
Simulation time 31333724 ps
CPU time 1.13 seconds
Started Oct 12 06:27:59 AM UTC 24
Finished Oct 12 06:28:01 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179704918 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2179704918 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.653467743
Short name T154
Test name
Test status
Simulation time 31019325 ps
CPU time 1.77 seconds
Started Oct 12 06:27:59 AM UTC 24
Finished Oct 12 06:28:01 AM UTC 24
Peak memory 224052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653467743 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.653467743 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3048110769
Short name T797
Test name
Test status
Simulation time 22336408 ps
CPU time 1.02 seconds
Started Oct 12 06:27:59 AM UTC 24
Finished Oct 12 06:28:01 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048110769 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3048110769 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1989264837
Short name T170
Test name
Test status
Simulation time 129412432 ps
CPU time 1.96 seconds
Started Oct 12 06:28:01 AM UTC 24
Finished Oct 12 06:28:04 AM UTC 24
Peak memory 223756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989264837 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.1989264837 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.543264768
Short name T114
Test name
Test status
Simulation time 227226422 ps
CPU time 1.7 seconds
Started Oct 12 06:27:57 AM UTC 24
Finished Oct 12 06:28:00 AM UTC 24
Peak memory 223728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543264768 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.543264768 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2140680522
Short name T798
Test name
Test status
Simulation time 336056868 ps
CPU time 2.67 seconds
Started Oct 12 06:27:57 AM UTC 24
Finished Oct 12 06:28:01 AM UTC 24
Peak memory 230252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140680522 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.2140
680522 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.883724075
Short name T799
Test name
Test status
Simulation time 59560756 ps
CPU time 2.11 seconds
Started Oct 12 06:27:59 AM UTC 24
Finished Oct 12 06:28:02 AM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883724075 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.883724075 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.2436635411
Short name T189
Test name
Test status
Simulation time 411021781 ps
CPU time 3.53 seconds
Started Oct 12 06:27:59 AM UTC 24
Finished Oct 12 06:28:03 AM UTC 24
Peak memory 225720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436635411 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.2436635411 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.3744874796
Short name T926
Test name
Test status
Simulation time 12197616 ps
CPU time 1.07 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744874796 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.3744874796 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.975903281
Short name T928
Test name
Test status
Simulation time 27116127 ps
CPU time 1.13 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975903281 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.975903281 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.3833162244
Short name T927
Test name
Test status
Simulation time 18525151 ps
CPU time 1.12 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833162244 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.3833162244 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.3876915095
Short name T925
Test name
Test status
Simulation time 18005749 ps
CPU time 1.02 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876915095 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3876915095 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.3142581240
Short name T929
Test name
Test status
Simulation time 52823890 ps
CPU time 1.03 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142581240 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3142581240 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1115535033
Short name T930
Test name
Test status
Simulation time 38066328 ps
CPU time 1.06 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115535033 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1115535033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2183779150
Short name T931
Test name
Test status
Simulation time 13282704 ps
CPU time 0.97 seconds
Started Oct 12 06:28:40 AM UTC 24
Finished Oct 12 06:28:42 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183779150 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2183779150 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.1978156693
Short name T934
Test name
Test status
Simulation time 13327323 ps
CPU time 1.29 seconds
Started Oct 12 06:28:41 AM UTC 24
Finished Oct 12 06:28:44 AM UTC 24
Peak memory 223816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978156693 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1978156693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.2407884149
Short name T933
Test name
Test status
Simulation time 49246068 ps
CPU time 1.12 seconds
Started Oct 12 06:28:41 AM UTC 24
Finished Oct 12 06:28:44 AM UTC 24
Peak memory 224076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407884149 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2407884149 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.636752637
Short name T932
Test name
Test status
Simulation time 15166923 ps
CPU time 0.99 seconds
Started Oct 12 06:28:42 AM UTC 24
Finished Oct 12 06:28:44 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636752637 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.636752637 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3239006463
Short name T810
Test name
Test status
Simulation time 75016300 ps
CPU time 3.34 seconds
Started Oct 12 06:28:05 AM UTC 24
Finished Oct 12 06:28:10 AM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3239006463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_
rw_with_rand_reset.3239006463 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.3470008321
Short name T803
Test name
Test status
Simulation time 59666736 ps
CPU time 1.31 seconds
Started Oct 12 06:28:04 AM UTC 24
Finished Oct 12 06:28:06 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470008321 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3470008321 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.215402694
Short name T175
Test name
Test status
Simulation time 12745317 ps
CPU time 1.19 seconds
Started Oct 12 06:28:04 AM UTC 24
Finished Oct 12 06:28:06 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215402694 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.215402694 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1074048446
Short name T805
Test name
Test status
Simulation time 55424104 ps
CPU time 2.01 seconds
Started Oct 12 06:28:04 AM UTC 24
Finished Oct 12 06:28:07 AM UTC 24
Peak memory 223756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074048446 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.1074048446 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2359308146
Short name T123
Test name
Test status
Simulation time 43519048 ps
CPU time 2.1 seconds
Started Oct 12 06:28:02 AM UTC 24
Finished Oct 12 06:28:06 AM UTC 24
Peak memory 227988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359308146 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.2359308146 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2178606412
Short name T804
Test name
Test status
Simulation time 57584302 ps
CPU time 3.27 seconds
Started Oct 12 06:28:02 AM UTC 24
Finished Oct 12 06:28:07 AM UTC 24
Peak memory 230124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178606412 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.2178
606412 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.152337893
Short name T806
Test name
Test status
Simulation time 63407268 ps
CPU time 3.18 seconds
Started Oct 12 06:28:03 AM UTC 24
Finished Oct 12 06:28:07 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152337893 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.152337893 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3364031816
Short name T190
Test name
Test status
Simulation time 56698064 ps
CPU time 2.71 seconds
Started Oct 12 06:28:04 AM UTC 24
Finished Oct 12 06:28:07 AM UTC 24
Peak memory 225652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364031816 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.3364031816 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2365981917
Short name T815
Test name
Test status
Simulation time 43392530 ps
CPU time 2.52 seconds
Started Oct 12 06:28:08 AM UTC 24
Finished Oct 12 06:28:12 AM UTC 24
Peak memory 229804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2365981917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_
rw_with_rand_reset.2365981917 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.2330950748
Short name T809
Test name
Test status
Simulation time 20719620 ps
CPU time 1.06 seconds
Started Oct 12 06:28:07 AM UTC 24
Finished Oct 12 06:28:09 AM UTC 24
Peak memory 224120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330950748 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.2330950748 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.388077574
Short name T140
Test name
Test status
Simulation time 14841301 ps
CPU time 1.25 seconds
Started Oct 12 06:28:07 AM UTC 24
Finished Oct 12 06:28:09 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388077574 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.388077574 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2036666544
Short name T816
Test name
Test status
Simulation time 36422498 ps
CPU time 2.76 seconds
Started Oct 12 06:28:08 AM UTC 24
Finished Oct 12 06:28:12 AM UTC 24
Peak memory 225584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036666544 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.2036666544 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.568554921
Short name T808
Test name
Test status
Simulation time 19638250 ps
CPU time 1.35 seconds
Started Oct 12 06:28:05 AM UTC 24
Finished Oct 12 06:28:08 AM UTC 24
Peak memory 226308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568554921 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.568554921 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.2508855580
Short name T115
Test name
Test status
Simulation time 54349166 ps
CPU time 2.5 seconds
Started Oct 12 06:28:06 AM UTC 24
Finished Oct 12 06:28:10 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508855580 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.2508
855580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.1099913548
Short name T813
Test name
Test status
Simulation time 50252796 ps
CPU time 4.31 seconds
Started Oct 12 06:28:06 AM UTC 24
Finished Oct 12 06:28:11 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099913548 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1099913548 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.942334971
Short name T186
Test name
Test status
Simulation time 1349673287 ps
CPU time 4.27 seconds
Started Oct 12 06:28:07 AM UTC 24
Finished Oct 12 06:28:13 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942334971 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.942334971 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2757340764
Short name T821
Test name
Test status
Simulation time 23863494 ps
CPU time 1.61 seconds
Started Oct 12 06:28:11 AM UTC 24
Finished Oct 12 06:28:14 AM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2757340764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_
rw_with_rand_reset.2757340764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.2176663970
Short name T817
Test name
Test status
Simulation time 31028025 ps
CPU time 1.64 seconds
Started Oct 12 06:28:10 AM UTC 24
Finished Oct 12 06:28:13 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176663970 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2176663970 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.3299665180
Short name T176
Test name
Test status
Simulation time 99797725 ps
CPU time 1.24 seconds
Started Oct 12 06:28:10 AM UTC 24
Finished Oct 12 06:28:12 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299665180 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3299665180 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3334442123
Short name T820
Test name
Test status
Simulation time 42743480 ps
CPU time 1.67 seconds
Started Oct 12 06:28:11 AM UTC 24
Finished Oct 12 06:28:14 AM UTC 24
Peak memory 223756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334442123 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3334442123 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1245989600
Short name T812
Test name
Test status
Simulation time 524345074 ps
CPU time 1.73 seconds
Started Oct 12 06:28:09 AM UTC 24
Finished Oct 12 06:28:11 AM UTC 24
Peak memory 226156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245989600 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.1245989600 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3232403889
Short name T116
Test name
Test status
Simulation time 713725044 ps
CPU time 3.39 seconds
Started Oct 12 06:28:09 AM UTC 24
Finished Oct 12 06:28:13 AM UTC 24
Peak memory 230248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232403889 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.3232
403889 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.2804679554
Short name T793
Test name
Test status
Simulation time 83516743 ps
CPU time 3.54 seconds
Started Oct 12 06:28:09 AM UTC 24
Finished Oct 12 06:28:13 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804679554 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2804679554 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.2204770400
Short name T184
Test name
Test status
Simulation time 241204760 ps
CPU time 5.91 seconds
Started Oct 12 06:28:09 AM UTC 24
Finished Oct 12 06:28:16 AM UTC 24
Peak memory 225784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204770400 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.2204770400 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2625329701
Short name T830
Test name
Test status
Simulation time 384957050 ps
CPU time 3.69 seconds
Started Oct 12 06:28:14 AM UTC 24
Finished Oct 12 06:28:19 AM UTC 24
Peak memory 232048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2625329701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_
rw_with_rand_reset.2625329701 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.1373492259
Short name T825
Test name
Test status
Simulation time 98607064 ps
CPU time 1.81 seconds
Started Oct 12 06:28:14 AM UTC 24
Finished Oct 12 06:28:16 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373492259 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1373492259 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.2815927223
Short name T823
Test name
Test status
Simulation time 29701316 ps
CPU time 1.12 seconds
Started Oct 12 06:28:13 AM UTC 24
Finished Oct 12 06:28:16 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815927223 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.2815927223 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3527844587
Short name T827
Test name
Test status
Simulation time 104473613 ps
CPU time 2.26 seconds
Started Oct 12 06:28:14 AM UTC 24
Finished Oct 12 06:28:17 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527844587 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.3527844587 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3290838221
Short name T120
Test name
Test status
Simulation time 131490256 ps
CPU time 1.83 seconds
Started Oct 12 06:28:11 AM UTC 24
Finished Oct 12 06:28:14 AM UTC 24
Peak memory 228260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290838221 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.3290838221 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3079515705
Short name T121
Test name
Test status
Simulation time 57861168 ps
CPU time 2.67 seconds
Started Oct 12 06:28:12 AM UTC 24
Finished Oct 12 06:28:16 AM UTC 24
Peak memory 225956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079515705 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.3079
515705 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.651706203
Short name T822
Test name
Test status
Simulation time 190613954 ps
CPU time 1.95 seconds
Started Oct 12 06:28:12 AM UTC 24
Finished Oct 12 06:28:15 AM UTC 24
Peak memory 224056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651706203 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.651706203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2631455351
Short name T834
Test name
Test status
Simulation time 176986657 ps
CPU time 2.48 seconds
Started Oct 12 06:28:16 AM UTC 24
Finished Oct 12 06:28:20 AM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2631455351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_
rw_with_rand_reset.2631455351 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.2837728652
Short name T828
Test name
Test status
Simulation time 67597590 ps
CPU time 1.16 seconds
Started Oct 12 06:28:15 AM UTC 24
Finished Oct 12 06:28:17 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837728652 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2837728652 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.1058457675
Short name T179
Test name
Test status
Simulation time 20902990 ps
CPU time 1.23 seconds
Started Oct 12 06:28:15 AM UTC 24
Finished Oct 12 06:28:17 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058457675 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1058457675 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3231884218
Short name T829
Test name
Test status
Simulation time 99508415 ps
CPU time 1.94 seconds
Started Oct 12 06:28:15 AM UTC 24
Finished Oct 12 06:28:18 AM UTC 24
Peak memory 223756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231884218 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.3231884218 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2313669998
Short name T826
Test name
Test status
Simulation time 95802242 ps
CPU time 1.69 seconds
Started Oct 12 06:28:14 AM UTC 24
Finished Oct 12 06:28:17 AM UTC 24
Peak memory 228184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313669998 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.2313669998 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1546169997
Short name T833
Test name
Test status
Simulation time 234212788 ps
CPU time 4.22 seconds
Started Oct 12 06:28:14 AM UTC 24
Finished Oct 12 06:28:19 AM UTC 24
Peak memory 230152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546169997 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.1546
169997 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.1800551665
Short name T832
Test name
Test status
Simulation time 540474791 ps
CPU time 4.11 seconds
Started Oct 12 06:28:14 AM UTC 24
Finished Oct 12 06:28:19 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800551665 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.1800551665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3296926054
Short name T838
Test name
Test status
Simulation time 212052874 ps
CPU time 4.26 seconds
Started Oct 12 06:28:15 AM UTC 24
Finished Oct 12 06:28:20 AM UTC 24
Peak memory 225600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296926054 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.3296926054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.1214816589
Short name T35
Test name
Test status
Simulation time 8531834038 ps
CPU time 197.3 seconds
Started Oct 12 07:27:41 AM UTC 24
Finished Oct 12 07:31:01 AM UTC 24
Peak memory 293460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214816589 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1214816589 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.3671245585
Short name T156
Test name
Test status
Simulation time 46731335262 ps
CPU time 717.39 seconds
Started Oct 12 07:27:28 AM UTC 24
Finished Oct 12 07:39:34 AM UTC 24
Peak memory 256616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671245585 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.3671245585 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.2380581091
Short name T11
Test name
Test status
Simulation time 4212324877 ps
CPU time 114.12 seconds
Started Oct 12 07:27:41 AM UTC 24
Finished Oct 12 07:29:37 AM UTC 24
Peak memory 299624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380581091 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2380581091 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_error.3664066692
Short name T14
Test name
Test status
Simulation time 4328919313 ps
CPU time 20.88 seconds
Started Oct 12 07:27:43 AM UTC 24
Finished Oct 12 07:28:05 AM UTC 24
Peak memory 254568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664066692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3664066692 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.2628523053
Short name T9
Test name
Test status
Simulation time 104269033 ps
CPU time 1.94 seconds
Started Oct 12 07:27:54 AM UTC 24
Finished Oct 12 07:27:57 AM UTC 24
Peak memory 233912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628523053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2628523053 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.1377468434
Short name T728
Test name
Test status
Simulation time 184988734880 ps
CPU time 4370.37 seconds
Started Oct 12 07:27:25 AM UTC 24
Finished Oct 12 08:41:00 AM UTC 24
Peak memory 4541040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377468434 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.1377468434 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.72818180
Short name T30
Test name
Test status
Simulation time 6098582314 ps
CPU time 218.94 seconds
Started Oct 12 07:27:43 AM UTC 24
Finished Oct 12 07:31:26 AM UTC 24
Peak memory 289716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72818180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.72818180 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.1272382196
Short name T18
Test name
Test status
Simulation time 15723559036 ps
CPU time 72.92 seconds
Started Oct 12 07:28:00 AM UTC 24
Finished Oct 12 07:29:15 AM UTC 24
Peak memory 290540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272382196 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1272382196 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.827835939
Short name T150
Test name
Test status
Simulation time 58437403702 ps
CPU time 215.14 seconds
Started Oct 12 07:27:26 AM UTC 24
Finished Oct 12 07:31:05 AM UTC 24
Peak memory 377464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827835939 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.827835939 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.623284044
Short name T2
Test name
Test status
Simulation time 281840131 ps
CPU time 4.86 seconds
Started Oct 12 07:27:35 AM UTC 24
Finished Oct 12 07:27:40 AM UTC 24
Peak memory 232616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623284044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.623284044 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.849530675
Short name T3
Test name
Test status
Simulation time 50702210 ps
CPU time 2.8 seconds
Started Oct 12 07:27:39 AM UTC 24
Finished Oct 12 07:27:42 AM UTC 24
Peak memory 232420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849530675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.849530675 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.1549047403
Short name T387
Test name
Test status
Simulation time 84783043939 ps
CPU time 1925.15 seconds
Started Oct 12 07:27:28 AM UTC 24
Finished Oct 12 07:59:55 AM UTC 24
Peak memory 1173968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549047403 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1549047403 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.3648235457
Short name T522
Test name
Test status
Simulation time 120027272899 ps
CPU time 2871.27 seconds
Started Oct 12 07:27:29 AM UTC 24
Finished Oct 12 08:15:53 AM UTC 24
Peak memory 3043792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648235457 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3648235457 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1759710448
Short name T46
Test name
Test status
Simulation time 1233326476 ps
CPU time 35.79 seconds
Started Oct 12 07:27:29 AM UTC 24
Finished Oct 12 07:28:07 AM UTC 24
Peak memory 232372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759710448 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1759710448 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.221008471
Short name T311
Test name
Test status
Simulation time 123377504372 ps
CPU time 1375.81 seconds
Started Oct 12 07:27:29 AM UTC 24
Finished Oct 12 07:50:41 AM UTC 24
Peak memory 1692100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221008471 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.221008471 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.2551861424
Short name T454
Test name
Test status
Simulation time 163497756968 ps
CPU time 2437.67 seconds
Started Oct 12 07:27:30 AM UTC 24
Finished Oct 12 08:08:36 AM UTC 24
Peak memory 1364428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551861424 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2551861424 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.2417693550
Short name T130
Test name
Test status
Simulation time 43414914 ps
CPU time 1.32 seconds
Started Oct 12 07:29:02 AM UTC 24
Finished Oct 12 07:29:05 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417693550 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2417693550 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_app.4062310720
Short name T28
Test name
Test status
Simulation time 54764819555 ps
CPU time 426.81 seconds
Started Oct 12 07:28:39 AM UTC 24
Finished Oct 12 07:35:52 AM UTC 24
Peak memory 510548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062310720 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.4062310720 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.3591977803
Short name T101
Test name
Test status
Simulation time 6238874841 ps
CPU time 179.1 seconds
Started Oct 12 07:28:41 AM UTC 24
Finished Oct 12 07:31:43 AM UTC 24
Peak memory 363104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591977803 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.3591977803 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.85175047
Short name T160
Test name
Test status
Simulation time 11258279664 ps
CPU time 1136.77 seconds
Started Oct 12 07:28:06 AM UTC 24
Finished Oct 12 07:47:18 AM UTC 24
Peak memory 256632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85175047 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.85175047 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.2553068805
Short name T84
Test name
Test status
Simulation time 67044894 ps
CPU time 1.62 seconds
Started Oct 12 07:28:57 AM UTC 24
Finished Oct 12 07:28:59 AM UTC 24
Peak memory 230076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553068805 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2553068805 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.3727354657
Short name T5
Test name
Test status
Simulation time 1702074065 ps
CPU time 12.67 seconds
Started Oct 12 07:28:57 AM UTC 24
Finished Oct 12 07:29:11 AM UTC 24
Peak memory 234500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727354657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3727354657 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.4286694496
Short name T13
Test name
Test status
Simulation time 22422266231 ps
CPU time 126.75 seconds
Started Oct 12 07:28:44 AM UTC 24
Finished Oct 12 07:30:53 AM UTC 24
Peak memory 326332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286694496 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.4286694496 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_error.2997974475
Short name T19
Test name
Test status
Simulation time 10243622911 ps
CPU time 366.71 seconds
Started Oct 12 07:28:51 AM UTC 24
Finished Oct 12 07:35:02 AM UTC 24
Peak memory 518896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997974475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2997974475 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.841435508
Short name T32
Test name
Test status
Simulation time 816558509 ps
CPU time 16.17 seconds
Started Oct 12 07:28:54 AM UTC 24
Finished Oct 12 07:29:11 AM UTC 24
Peak memory 230068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841435508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.841435508 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.2832933642
Short name T412
Test name
Test status
Simulation time 18532997141 ps
CPU time 2122.23 seconds
Started Oct 12 07:28:04 AM UTC 24
Finished Oct 12 08:03:50 AM UTC 24
Peak memory 1307376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832933642 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.2832933642 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.3598348897
Short name T42
Test name
Test status
Simulation time 29352091884 ps
CPU time 135.24 seconds
Started Oct 12 07:29:00 AM UTC 24
Finished Oct 12 07:31:18 AM UTC 24
Peak memory 317160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598348897 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3598348897 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.4275408731
Short name T26
Test name
Test status
Simulation time 13116967104 ps
CPU time 327.88 seconds
Started Oct 12 07:28:05 AM UTC 24
Finished Oct 12 07:33:38 AM UTC 24
Peak memory 330292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275408731 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.4275408731 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.1958671728
Short name T31
Test name
Test status
Simulation time 1662806097 ps
CPU time 14.3 seconds
Started Oct 12 07:28:03 AM UTC 24
Finished Oct 12 07:28:19 AM UTC 24
Peak memory 234540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958671728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1958671728 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.905718520
Short name T88
Test name
Test status
Simulation time 68898496068 ps
CPU time 2378.3 seconds
Started Oct 12 07:28:59 AM UTC 24
Finished Oct 12 08:09:05 AM UTC 24
Peak memory 1139836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905718520 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.905718520 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.3455152195
Short name T49
Test name
Test status
Simulation time 209387620 ps
CPU time 3.36 seconds
Started Oct 12 07:28:28 AM UTC 24
Finished Oct 12 07:28:33 AM UTC 24
Peak memory 232392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455152195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.3455152195 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.746539855
Short name T50
Test name
Test status
Simulation time 78657800 ps
CPU time 3.91 seconds
Started Oct 12 07:28:33 AM UTC 24
Finished Oct 12 07:28:38 AM UTC 24
Peak memory 232516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746539855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.746539855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.597995738
Short name T65
Test name
Test status
Simulation time 2342926866 ps
CPU time 43.63 seconds
Started Oct 12 07:28:07 AM UTC 24
Finished Oct 12 07:28:53 AM UTC 24
Peak memory 262768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597995738 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.597995738 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.3029145199
Short name T55
Test name
Test status
Simulation time 9285707059 ps
CPU time 43.71 seconds
Started Oct 12 07:28:12 AM UTC 24
Finished Oct 12 07:28:57 AM UTC 24
Peak memory 260400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029145199 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.3029145199 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.369628686
Short name T414
Test name
Test status
Simulation time 91028846275 ps
CPU time 2123.17 seconds
Started Oct 12 07:28:12 AM UTC 24
Finished Oct 12 08:03:59 AM UTC 24
Peak memory 2312540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369628686 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.369628686 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.201409386
Short name T67
Test name
Test status
Simulation time 4557130832 ps
CPU time 28.56 seconds
Started Oct 12 07:28:20 AM UTC 24
Finished Oct 12 07:28:50 AM UTC 24
Peak memory 236464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201409386 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.201409386 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.3422175187
Short name T490
Test name
Test status
Simulation time 21265596186 ps
CPU time 2627.63 seconds
Started Oct 12 07:28:21 AM UTC 24
Finished Oct 12 08:12:38 AM UTC 24
Peak memory 1368528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422175187 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3422175187 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.2421120424
Short name T268
Test name
Test status
Simulation time 17545734 ps
CPU time 1.31 seconds
Started Oct 12 07:45:35 AM UTC 24
Finished Oct 12 07:45:38 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421120424 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2421120424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_app.4033922144
Short name T313
Test name
Test status
Simulation time 21870283611 ps
CPU time 335.97 seconds
Started Oct 12 07:45:08 AM UTC 24
Finished Oct 12 07:50:48 AM UTC 24
Peak memory 340556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033922144 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.4033922144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.3050355938
Short name T305
Test name
Test status
Simulation time 5863759074 ps
CPU time 275.71 seconds
Started Oct 12 07:45:01 AM UTC 24
Finished Oct 12 07:49:41 AM UTC 24
Peak memory 252596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050355938 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.3050355938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.3567600802
Short name T265
Test name
Test status
Simulation time 128911247 ps
CPU time 1.85 seconds
Started Oct 12 07:45:24 AM UTC 24
Finished Oct 12 07:45:28 AM UTC 24
Peak memory 230080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567600802 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3567600802 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.1212098515
Short name T267
Test name
Test status
Simulation time 57192007 ps
CPU time 1.51 seconds
Started Oct 12 07:45:29 AM UTC 24
Finished Oct 12 07:45:31 AM UTC 24
Peak memory 226748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212098515 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1212098515 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.4046064724
Short name T319
Test name
Test status
Simulation time 43756765087 ps
CPU time 397.06 seconds
Started Oct 12 07:45:11 AM UTC 24
Finished Oct 12 07:51:54 AM UTC 24
Peak memory 338444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046064724 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.4046064724 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_error.348813949
Short name T296
Test name
Test status
Simulation time 4775602428 ps
CPU time 211.54 seconds
Started Oct 12 07:45:14 AM UTC 24
Finished Oct 12 07:48:49 AM UTC 24
Peak memory 373352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348813949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.348813949 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.124254644
Short name T269
Test name
Test status
Simulation time 18885437613 ps
CPU time 32.36 seconds
Started Oct 12 07:45:16 AM UTC 24
Finished Oct 12 07:45:50 AM UTC 24
Peak memory 232124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124254644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.124254644 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.3500335463
Short name T125
Test name
Test status
Simulation time 89571449 ps
CPU time 2.24 seconds
Started Oct 12 07:45:31 AM UTC 24
Finished Oct 12 07:45:34 AM UTC 24
Peak memory 234404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500335463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.3500335463 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.3330979689
Short name T745
Test name
Test status
Simulation time 28884696722 ps
CPU time 3639.09 seconds
Started Oct 12 07:44:32 AM UTC 24
Finished Oct 12 08:45:53 AM UTC 24
Peak memory 1979112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330979689 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.3330979689 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.3612768181
Short name T315
Test name
Test status
Simulation time 9546008057 ps
CPU time 399.28 seconds
Started Oct 12 07:44:35 AM UTC 24
Finished Oct 12 07:51:19 AM UTC 24
Peak memory 375392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612768181 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3612768181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload_invalid.638532023
Short name T261
Test name
Test status
Simulation time 124087418 ps
CPU time 3.04 seconds
Started Oct 12 07:44:56 AM UTC 24
Finished Oct 12 07:45:00 AM UTC 24
Peak memory 237072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638532023 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload_invalid.638532023 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.3936915025
Short name T266
Test name
Test status
Simulation time 2057071700 ps
CPU time 58.53 seconds
Started Oct 12 07:44:29 AM UTC 24
Finished Oct 12 07:45:30 AM UTC 24
Peak memory 236672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936915025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3936915025 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.396227270
Short name T161
Test name
Test status
Simulation time 14512903704 ps
CPU time 183.94 seconds
Started Oct 12 07:45:32 AM UTC 24
Finished Oct 12 07:48:39 AM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396227270 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.396227270 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.3417030764
Short name T281
Test name
Test status
Simulation time 33466529 ps
CPU time 1.25 seconds
Started Oct 12 07:47:11 AM UTC 24
Finished Oct 12 07:47:14 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417030764 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.3417030764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_app.958831602
Short name T328
Test name
Test status
Simulation time 14350563235 ps
CPU time 417.92 seconds
Started Oct 12 07:46:25 AM UTC 24
Finished Oct 12 07:53:29 AM UTC 24
Peak memory 471660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958831602 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.958831602 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.1736838070
Short name T369
Test name
Test status
Simulation time 35412032170 ps
CPU time 673.17 seconds
Started Oct 12 07:46:20 AM UTC 24
Finished Oct 12 07:57:42 AM UTC 24
Peak memory 254640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736838070 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.1736838070 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.948819819
Short name T286
Test name
Test status
Simulation time 10266132822 ps
CPU time 39.67 seconds
Started Oct 12 07:46:57 AM UTC 24
Finished Oct 12 07:47:38 AM UTC 24
Peak memory 237988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948819819 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.948819819 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.670378420
Short name T279
Test name
Test status
Simulation time 26145687 ps
CPU time 1.56 seconds
Started Oct 12 07:47:08 AM UTC 24
Finished Oct 12 07:47:11 AM UTC 24
Peak memory 226752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670378420 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.670378420 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.1934292769
Short name T318
Test name
Test status
Simulation time 55739256045 ps
CPU time 307.66 seconds
Started Oct 12 07:46:35 AM UTC 24
Finished Oct 12 07:51:47 AM UTC 24
Peak memory 324392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934292769 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1934292769 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_error.2075486479
Short name T290
Test name
Test status
Simulation time 768597598 ps
CPU time 56 seconds
Started Oct 12 07:46:45 AM UTC 24
Finished Oct 12 07:47:42 AM UTC 24
Peak memory 266920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075486479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2075486479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.3193173258
Short name T276
Test name
Test status
Simulation time 3983378470 ps
CPU time 12.86 seconds
Started Oct 12 07:46:55 AM UTC 24
Finished Oct 12 07:47:09 AM UTC 24
Peak memory 230068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193173258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3193173258 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.1329520546
Short name T282
Test name
Test status
Simulation time 755163654 ps
CPU time 7.25 seconds
Started Oct 12 07:47:10 AM UTC 24
Finished Oct 12 07:47:19 AM UTC 24
Peak memory 244720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329520546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1329520546 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.1105533465
Short name T751
Test name
Test status
Simulation time 269034526418 ps
CPU time 3691.96 seconds
Started Oct 12 07:45:51 AM UTC 24
Finished Oct 12 08:48:04 AM UTC 24
Peak memory 1854048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105533465 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.1105533465 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.4103235196
Short name T277
Test name
Test status
Simulation time 16979061012 ps
CPU time 59.73 seconds
Started Oct 12 07:46:08 AM UTC 24
Finished Oct 12 07:47:10 AM UTC 24
Peak memory 287316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103235196 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.4103235196 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload_invalid.3585883271
Short name T272
Test name
Test status
Simulation time 270275930 ps
CPU time 7.73 seconds
Started Oct 12 07:46:16 AM UTC 24
Finished Oct 12 07:46:25 AM UTC 24
Peak memory 236908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585883271 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload_invalid.3585883271 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.3608975524
Short name T275
Test name
Test status
Simulation time 9805252197 ps
CPU time 85.29 seconds
Started Oct 12 07:45:39 AM UTC 24
Finished Oct 12 07:47:07 AM UTC 24
Peak memory 238148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608975524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.3608975524 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.1837166063
Short name T360
Test name
Test status
Simulation time 7471663832 ps
CPU time 593.21 seconds
Started Oct 12 07:47:10 AM UTC 24
Finished Oct 12 07:57:11 AM UTC 24
Peak memory 320452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837166063 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1837166063 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.2213357256
Short name T291
Test name
Test status
Simulation time 127459547 ps
CPU time 1.31 seconds
Started Oct 12 07:47:43 AM UTC 24
Finished Oct 12 07:47:45 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213357256 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2213357256 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_app.2424936470
Short name T354
Test name
Test status
Simulation time 52392369697 ps
CPU time 522.96 seconds
Started Oct 12 07:47:19 AM UTC 24
Finished Oct 12 07:56:09 AM UTC 24
Peak memory 547632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424936470 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.2424936470 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.3175474210
Short name T431
Test name
Test status
Simulation time 48992945866 ps
CPU time 1116.72 seconds
Started Oct 12 07:47:16 AM UTC 24
Finished Oct 12 08:06:07 AM UTC 24
Peak memory 266792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175474210 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3175474210 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.1502982558
Short name T287
Test name
Test status
Simulation time 2416972862 ps
CPU time 5.75 seconds
Started Oct 12 07:47:33 AM UTC 24
Finished Oct 12 07:47:40 AM UTC 24
Peak memory 230208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502982558 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1502982558 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.1744157213
Short name T288
Test name
Test status
Simulation time 16683855 ps
CPU time 1.55 seconds
Started Oct 12 07:47:38 AM UTC 24
Finished Oct 12 07:47:41 AM UTC 24
Peak memory 226748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744157213 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1744157213 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.3136095838
Short name T79
Test name
Test status
Simulation time 17333812970 ps
CPU time 151.51 seconds
Started Oct 12 07:47:19 AM UTC 24
Finished Oct 12 07:49:54 AM UTC 24
Peak memory 320056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136095838 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3136095838 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_error.1450462159
Short name T295
Test name
Test status
Simulation time 3151673725 ps
CPU time 67.9 seconds
Started Oct 12 07:47:24 AM UTC 24
Finished Oct 12 07:48:34 AM UTC 24
Peak memory 297512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450462159 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1450462159 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.1630179268
Short name T285
Test name
Test status
Simulation time 882424202 ps
CPU time 6.26 seconds
Started Oct 12 07:47:25 AM UTC 24
Finished Oct 12 07:47:33 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630179268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.1630179268 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.1323566053
Short name T343
Test name
Test status
Simulation time 30071437481 ps
CPU time 455.51 seconds
Started Oct 12 07:47:14 AM UTC 24
Finished Oct 12 07:54:56 AM UTC 24
Peak memory 780908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323566053 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.1323566053 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.2617467811
Short name T283
Test name
Test status
Simulation time 225339415 ps
CPU time 7.06 seconds
Started Oct 12 07:47:14 AM UTC 24
Finished Oct 12 07:47:23 AM UTC 24
Peak memory 237304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617467811 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2617467811 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload_invalid.3726500907
Short name T284
Test name
Test status
Simulation time 622547832 ps
CPU time 6.99 seconds
Started Oct 12 07:47:16 AM UTC 24
Finished Oct 12 07:47:24 AM UTC 24
Peak memory 234884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726500907 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload_invalid.3726500907 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.1135281110
Short name T294
Test name
Test status
Simulation time 14537309665 ps
CPU time 79.64 seconds
Started Oct 12 07:47:12 AM UTC 24
Finished Oct 12 07:48:34 AM UTC 24
Peak memory 238120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135281110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.1135281110 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.454038078
Short name T397
Test name
Test status
Simulation time 22483698479 ps
CPU time 812.91 seconds
Started Oct 12 07:47:41 AM UTC 24
Finished Oct 12 08:01:25 AM UTC 24
Peak memory 365500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454038078 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.454038078 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.2531088558
Short name T301
Test name
Test status
Simulation time 192917362 ps
CPU time 1.36 seconds
Started Oct 12 07:49:11 AM UTC 24
Finished Oct 12 07:49:13 AM UTC 24
Peak memory 227944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531088558 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2531088558 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_app.3154759489
Short name T297
Test name
Test status
Simulation time 572580181 ps
CPU time 22.06 seconds
Started Oct 12 07:48:35 AM UTC 24
Finished Oct 12 07:48:59 AM UTC 24
Peak memory 240168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154759489 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3154759489 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.3684373428
Short name T417
Test name
Test status
Simulation time 22141744243 ps
CPU time 939.57 seconds
Started Oct 12 07:48:18 AM UTC 24
Finished Oct 12 08:04:08 AM UTC 24
Peak memory 264744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684373428 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.3684373428 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.3624702529
Short name T298
Test name
Test status
Simulation time 45454267 ps
CPU time 1.51 seconds
Started Oct 12 07:49:00 AM UTC 24
Finished Oct 12 07:49:02 AM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624702529 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3624702529 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.4129875858
Short name T299
Test name
Test status
Simulation time 17559011 ps
CPU time 1.43 seconds
Started Oct 12 07:49:03 AM UTC 24
Finished Oct 12 07:49:05 AM UTC 24
Peak memory 228608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129875858 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.4129875858 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.3816349832
Short name T333
Test name
Test status
Simulation time 112865286369 ps
CPU time 345.31 seconds
Started Oct 12 07:48:35 AM UTC 24
Finished Oct 12 07:54:25 AM UTC 24
Peak memory 469632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816349832 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3816349832 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_error.1194716015
Short name T350
Test name
Test status
Simulation time 16251292723 ps
CPU time 430.89 seconds
Started Oct 12 07:48:40 AM UTC 24
Finished Oct 12 07:55:57 AM UTC 24
Peak memory 580176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194716015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.1194716015 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.4274958165
Short name T300
Test name
Test status
Simulation time 1348785509 ps
CPU time 14.81 seconds
Started Oct 12 07:48:50 AM UTC 24
Finished Oct 12 07:49:06 AM UTC 24
Peak memory 230192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274958165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.4274958165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.2161862565
Short name T336
Test name
Test status
Simulation time 34823829562 ps
CPU time 406.88 seconds
Started Oct 12 07:47:45 AM UTC 24
Finished Oct 12 07:54:37 AM UTC 24
Peak memory 692828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161862565 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.2161862565 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.2978788514
Short name T332
Test name
Test status
Simulation time 5369924985 ps
CPU time 392.96 seconds
Started Oct 12 07:47:46 AM UTC 24
Finished Oct 12 07:54:24 AM UTC 24
Peak memory 379568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978788514 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2978788514 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload_invalid.1131338907
Short name T293
Test name
Test status
Simulation time 255768360 ps
CPU time 5.26 seconds
Started Oct 12 07:48:11 AM UTC 24
Finished Oct 12 07:48:17 AM UTC 24
Peak memory 235080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131338907 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload_invalid.1131338907 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.900507872
Short name T292
Test name
Test status
Simulation time 865781099 ps
CPU time 24.9 seconds
Started Oct 12 07:47:44 AM UTC 24
Finished Oct 12 07:48:10 AM UTC 24
Peak memory 238200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900507872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.900507872 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.298408163
Short name T335
Test name
Test status
Simulation time 16577387862 ps
CPU time 323.16 seconds
Started Oct 12 07:49:08 AM UTC 24
Finished Oct 12 07:54:36 AM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298408163 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.298408163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.2041168534
Short name T314
Test name
Test status
Simulation time 21136092 ps
CPU time 1.32 seconds
Started Oct 12 07:50:48 AM UTC 24
Finished Oct 12 07:50:51 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041168534 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.2041168534 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_app.685920628
Short name T358
Test name
Test status
Simulation time 19004364302 ps
CPU time 421.25 seconds
Started Oct 12 07:49:41 AM UTC 24
Finished Oct 12 07:56:48 AM UTC 24
Peak memory 459288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685920628 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.685920628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.1651490172
Short name T448
Test name
Test status
Simulation time 33220085850 ps
CPU time 1110.96 seconds
Started Oct 12 07:49:38 AM UTC 24
Finished Oct 12 08:08:23 AM UTC 24
Peak memory 262832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651490172 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.1651490172 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.4204721637
Short name T309
Test name
Test status
Simulation time 79325992 ps
CPU time 1.78 seconds
Started Oct 12 07:50:29 AM UTC 24
Finished Oct 12 07:50:32 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204721637 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.4204721637 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.1161854861
Short name T310
Test name
Test status
Simulation time 23953713 ps
CPU time 1.57 seconds
Started Oct 12 07:50:33 AM UTC 24
Finished Oct 12 07:50:36 AM UTC 24
Peak memory 227288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161854861 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1161854861 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.3324905360
Short name T330
Test name
Test status
Simulation time 57359785603 ps
CPU time 236 seconds
Started Oct 12 07:49:55 AM UTC 24
Finished Oct 12 07:53:54 AM UTC 24
Peak memory 361068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324905360 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3324905360 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_error.2363818272
Short name T342
Test name
Test status
Simulation time 8241124295 ps
CPU time 285.32 seconds
Started Oct 12 07:50:05 AM UTC 24
Finished Oct 12 07:54:54 AM UTC 24
Peak memory 408300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363818272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.2363818272 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.184692703
Short name T308
Test name
Test status
Simulation time 444596315 ps
CPU time 2.43 seconds
Started Oct 12 07:50:25 AM UTC 24
Finished Oct 12 07:50:28 AM UTC 24
Peak memory 229796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184692703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.184692703 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.2011730594
Short name T312
Test name
Test status
Simulation time 404264067 ps
CPU time 9.19 seconds
Started Oct 12 07:50:37 AM UTC 24
Finished Oct 12 07:50:48 AM UTC 24
Peak memory 248908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011730594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2011730594 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.1297026943
Short name T502
Test name
Test status
Simulation time 34637587063 ps
CPU time 1442.3 seconds
Started Oct 12 07:49:18 AM UTC 24
Finished Oct 12 08:13:37 AM UTC 24
Peak memory 1817336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297026943 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.1297026943 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.4203671344
Short name T331
Test name
Test status
Simulation time 12930731863 ps
CPU time 287.2 seconds
Started Oct 12 07:49:21 AM UTC 24
Finished Oct 12 07:54:12 AM UTC 24
Peak memory 471592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203671344 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.4203671344 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload_invalid.3516250846
Short name T304
Test name
Test status
Simulation time 40293196 ps
CPU time 2.75 seconds
Started Oct 12 07:49:33 AM UTC 24
Finished Oct 12 07:49:37 AM UTC 24
Peak memory 234824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516250846 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload_invalid.3516250846 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.1193103333
Short name T306
Test name
Test status
Simulation time 1537581699 ps
CPU time 48.31 seconds
Started Oct 12 07:49:14 AM UTC 24
Finished Oct 12 07:50:04 AM UTC 24
Peak memory 238068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193103333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1193103333 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.2117768975
Short name T482
Test name
Test status
Simulation time 38461549361 ps
CPU time 1240.73 seconds
Started Oct 12 07:50:42 AM UTC 24
Finished Oct 12 08:11:38 AM UTC 24
Peak memory 1014776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117768975 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2117768975 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.967750268
Short name T326
Test name
Test status
Simulation time 21983947 ps
CPU time 1.27 seconds
Started Oct 12 07:52:58 AM UTC 24
Finished Oct 12 07:53:00 AM UTC 24
Peak memory 228664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967750268 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.967750268 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_app.2929422074
Short name T323
Test name
Test status
Simulation time 32176430931 ps
CPU time 56.56 seconds
Started Oct 12 07:51:48 AM UTC 24
Finished Oct 12 07:52:46 AM UTC 24
Peak memory 262768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929422074 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2929422074 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.2458315806
Short name T554
Test name
Test status
Simulation time 26806429733 ps
CPU time 1612.39 seconds
Started Oct 12 07:51:33 AM UTC 24
Finished Oct 12 08:18:44 AM UTC 24
Peak memory 258672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458315806 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2458315806 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.1898599254
Short name T325
Test name
Test status
Simulation time 650451435 ps
CPU time 16.65 seconds
Started Oct 12 07:52:40 AM UTC 24
Finished Oct 12 07:52:58 AM UTC 24
Peak memory 246532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898599254 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1898599254 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.506504917
Short name T324
Test name
Test status
Simulation time 74450383 ps
CPU time 1.81 seconds
Started Oct 12 07:52:48 AM UTC 24
Finished Oct 12 07:52:50 AM UTC 24
Peak memory 230072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506504917 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.506504917 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.3218095157
Short name T385
Test name
Test status
Simulation time 14004931501 ps
CPU time 469.39 seconds
Started Oct 12 07:51:54 AM UTC 24
Finished Oct 12 07:59:50 AM UTC 24
Peak memory 504500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218095157 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3218095157 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_error.1851053583
Short name T380
Test name
Test status
Simulation time 5070163895 ps
CPU time 399.73 seconds
Started Oct 12 07:51:55 AM UTC 24
Finished Oct 12 07:58:40 AM UTC 24
Peak memory 369256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851053583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1851053583 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.945435590
Short name T322
Test name
Test status
Simulation time 8419559308 ps
CPU time 19.74 seconds
Started Oct 12 07:52:17 AM UTC 24
Finished Oct 12 07:52:38 AM UTC 24
Peak memory 230204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945435590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.945435590 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.3485363755
Short name T91
Test name
Test status
Simulation time 36782334 ps
CPU time 1.34 seconds
Started Oct 12 07:52:52 AM UTC 24
Finished Oct 12 07:52:54 AM UTC 24
Peak memory 233860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485363755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3485363755 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.3345941807
Short name T479
Test name
Test status
Simulation time 146773755913 ps
CPU time 1210.87 seconds
Started Oct 12 07:50:52 AM UTC 24
Finished Oct 12 08:11:17 AM UTC 24
Peak memory 1681996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345941807 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.3345941807 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.713142244
Short name T396
Test name
Test status
Simulation time 22326533186 ps
CPU time 582.24 seconds
Started Oct 12 07:51:20 AM UTC 24
Finished Oct 12 08:01:10 AM UTC 24
Peak memory 643836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713142244 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.713142244 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload_invalid.4290432207
Short name T317
Test name
Test status
Simulation time 189521954 ps
CPU time 5.24 seconds
Started Oct 12 07:51:26 AM UTC 24
Finished Oct 12 07:51:32 AM UTC 24
Peak memory 238620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290432207 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload_invalid.4290432207 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.4037604484
Short name T316
Test name
Test status
Simulation time 2950780664 ps
CPU time 33.72 seconds
Started Oct 12 07:50:49 AM UTC 24
Finished Oct 12 07:51:25 AM UTC 24
Peak memory 238168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037604484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.4037604484 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.3498189880
Short name T364
Test name
Test status
Simulation time 11961140171 ps
CPU time 265.3 seconds
Started Oct 12 07:52:55 AM UTC 24
Finished Oct 12 07:57:24 AM UTC 24
Peak memory 336900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498189880 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.3498189880 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.1801665505
Short name T341
Test name
Test status
Simulation time 52525635 ps
CPU time 1.31 seconds
Started Oct 12 07:54:40 AM UTC 24
Finished Oct 12 07:54:43 AM UTC 24
Peak memory 227584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801665505 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1801665505 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_app.2146721681
Short name T374
Test name
Test status
Simulation time 4937740014 ps
CPU time 258.76 seconds
Started Oct 12 07:53:56 AM UTC 24
Finished Oct 12 07:58:18 AM UTC 24
Peak memory 322148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146721681 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2146721681 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.2456012963
Short name T368
Test name
Test status
Simulation time 3914256413 ps
CPU time 226.3 seconds
Started Oct 12 07:53:50 AM UTC 24
Finished Oct 12 07:57:40 AM UTC 24
Peak memory 252652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456012963 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.2456012963 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2044130466
Short name T338
Test name
Test status
Simulation time 72539387 ps
CPU time 1.7 seconds
Started Oct 12 07:54:37 AM UTC 24
Finished Oct 12 07:54:40 AM UTC 24
Peak memory 230132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044130466 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2044130466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.2871609946
Short name T337
Test name
Test status
Simulation time 21818202 ps
CPU time 1.51 seconds
Started Oct 12 07:54:37 AM UTC 24
Finished Oct 12 07:54:40 AM UTC 24
Peak memory 226748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871609946 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2871609946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.2276949836
Short name T373
Test name
Test status
Simulation time 7500859159 ps
CPU time 239.81 seconds
Started Oct 12 07:54:13 AM UTC 24
Finished Oct 12 07:58:17 AM UTC 24
Peak memory 315988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276949836 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2276949836 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_error.628692850
Short name T408
Test name
Test status
Simulation time 13768364114 ps
CPU time 499.59 seconds
Started Oct 12 07:54:25 AM UTC 24
Finished Oct 12 08:02:51 AM UTC 24
Peak memory 608868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628692850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.628692850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.815459779
Short name T339
Test name
Test status
Simulation time 3152159935 ps
CPU time 13.62 seconds
Started Oct 12 07:54:26 AM UTC 24
Finished Oct 12 07:54:41 AM UTC 24
Peak memory 232176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815459779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.815459779 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.2379413988
Short name T340
Test name
Test status
Simulation time 41714761 ps
CPU time 2.66 seconds
Started Oct 12 07:54:38 AM UTC 24
Finished Oct 12 07:54:42 AM UTC 24
Peak memory 236488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379413988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2379413988 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.4157228271
Short name T461
Test name
Test status
Simulation time 8825190692 ps
CPU time 958.02 seconds
Started Oct 12 07:53:23 AM UTC 24
Finished Oct 12 08:09:33 AM UTC 24
Peak memory 721564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157228271 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.4157228271 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.3370265033
Short name T353
Test name
Test status
Simulation time 5265700538 ps
CPU time 153.58 seconds
Started Oct 12 07:53:30 AM UTC 24
Finished Oct 12 07:56:07 AM UTC 24
Peak memory 352868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370265033 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3370265033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload_invalid.4171056860
Short name T329
Test name
Test status
Simulation time 199403386 ps
CPU time 8.95 seconds
Started Oct 12 07:53:38 AM UTC 24
Finished Oct 12 07:53:49 AM UTC 24
Peak memory 238500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171056860 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload_invalid.4171056860 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.2250432457
Short name T327
Test name
Test status
Simulation time 640612926 ps
CPU time 20.21 seconds
Started Oct 12 07:53:01 AM UTC 24
Finished Oct 12 07:53:22 AM UTC 24
Peak memory 234592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250432457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2250432457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.2579530190
Short name T434
Test name
Test status
Simulation time 14426461812 ps
CPU time 687.24 seconds
Started Oct 12 07:54:40 AM UTC 24
Finished Oct 12 08:06:16 AM UTC 24
Peak memory 369660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579530190 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2579530190 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.3119130696
Short name T352
Test name
Test status
Simulation time 60916646 ps
CPU time 1.28 seconds
Started Oct 12 07:56:02 AM UTC 24
Finished Oct 12 07:56:04 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119130696 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3119130696 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_app.1421743769
Short name T359
Test name
Test status
Simulation time 20145197772 ps
CPU time 120.57 seconds
Started Oct 12 07:55:05 AM UTC 24
Finished Oct 12 07:57:08 AM UTC 24
Peak memory 311856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421743769 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1421743769 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.3203548503
Short name T357
Test name
Test status
Simulation time 1957746578 ps
CPU time 100.23 seconds
Started Oct 12 07:54:57 AM UTC 24
Finished Oct 12 07:56:39 AM UTC 24
Peak memory 238116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203548503 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3203548503 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.2185191892
Short name T349
Test name
Test status
Simulation time 113085700 ps
CPU time 1.64 seconds
Started Oct 12 07:55:53 AM UTC 24
Finished Oct 12 07:55:56 AM UTC 24
Peak memory 230068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185191892 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2185191892 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.2947707167
Short name T351
Test name
Test status
Simulation time 32313387 ps
CPU time 1.88 seconds
Started Oct 12 07:55:58 AM UTC 24
Finished Oct 12 07:56:01 AM UTC 24
Peak memory 230072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947707167 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.2947707167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.2717702930
Short name T361
Test name
Test status
Simulation time 4688997232 ps
CPU time 118.52 seconds
Started Oct 12 07:55:12 AM UTC 24
Finished Oct 12 07:57:13 AM UTC 24
Peak memory 316008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717702930 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2717702930 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_error.4052736807
Short name T347
Test name
Test status
Simulation time 102991152 ps
CPU time 4.04 seconds
Started Oct 12 07:55:43 AM UTC 24
Finished Oct 12 07:55:49 AM UTC 24
Peak memory 234232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052736807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.4052736807 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.3830469900
Short name T348
Test name
Test status
Simulation time 188337710 ps
CPU time 2.29 seconds
Started Oct 12 07:55:49 AM UTC 24
Finished Oct 12 07:55:53 AM UTC 24
Peak memory 229916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830469900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3830469900 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.655902915
Short name T62
Test name
Test status
Simulation time 42800271 ps
CPU time 2.17 seconds
Started Oct 12 07:55:58 AM UTC 24
Finished Oct 12 07:56:01 AM UTC 24
Peak memory 234320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655902915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.655902915 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.869374320
Short name T573
Test name
Test status
Simulation time 13112396334 ps
CPU time 1559.35 seconds
Started Oct 12 07:54:43 AM UTC 24
Finished Oct 12 08:21:00 AM UTC 24
Peak memory 1024588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869374320 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.869374320 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.2875275358
Short name T372
Test name
Test status
Simulation time 7254610392 ps
CPU time 206.94 seconds
Started Oct 12 07:54:44 AM UTC 24
Finished Oct 12 07:58:14 AM UTC 24
Peak memory 381480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875275358 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2875275358 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload_invalid.1386438250
Short name T344
Test name
Test status
Simulation time 121262869 ps
CPU time 7.82 seconds
Started Oct 12 07:54:55 AM UTC 24
Finished Oct 12 07:55:04 AM UTC 24
Peak memory 236988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386438250 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload_invalid.1386438250 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.390320482
Short name T345
Test name
Test status
Simulation time 938780933 ps
CPU time 28.95 seconds
Started Oct 12 07:54:42 AM UTC 24
Finished Oct 12 07:55:12 AM UTC 24
Peak memory 238260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390320482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.390320482 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.3218321329
Short name T472
Test name
Test status
Simulation time 22202042282 ps
CPU time 863.8 seconds
Started Oct 12 07:56:02 AM UTC 24
Finished Oct 12 08:10:37 AM UTC 24
Peak memory 744444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218321329 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3218321329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.4213700033
Short name T366
Test name
Test status
Simulation time 169703417 ps
CPU time 1.43 seconds
Started Oct 12 07:57:29 AM UTC 24
Finished Oct 12 07:57:32 AM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213700033 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.4213700033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_app.2522468799
Short name T401
Test name
Test status
Simulation time 18326257238 ps
CPU time 306.63 seconds
Started Oct 12 07:56:40 AM UTC 24
Finished Oct 12 08:01:51 AM UTC 24
Peak memory 451156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522468799 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2522468799 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.3883595485
Short name T390
Test name
Test status
Simulation time 5368284342 ps
CPU time 206.59 seconds
Started Oct 12 07:56:29 AM UTC 24
Finished Oct 12 07:59:59 AM UTC 24
Peak memory 244196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883595485 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3883595485 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.2546781980
Short name T362
Test name
Test status
Simulation time 156229122 ps
CPU time 4.5 seconds
Started Oct 12 07:57:14 AM UTC 24
Finished Oct 12 07:57:19 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546781980 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2546781980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.2790009121
Short name T363
Test name
Test status
Simulation time 39593088 ps
CPU time 1.45 seconds
Started Oct 12 07:57:20 AM UTC 24
Finished Oct 12 07:57:22 AM UTC 24
Peak memory 228608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790009121 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2790009121 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.3357940234
Short name T393
Test name
Test status
Simulation time 16422956838 ps
CPU time 208.1 seconds
Started Oct 12 07:56:49 AM UTC 24
Finished Oct 12 08:00:21 AM UTC 24
Peak memory 289556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357940234 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3357940234 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_error.3176844518
Short name T419
Test name
Test status
Simulation time 34866063582 ps
CPU time 432.55 seconds
Started Oct 12 07:57:09 AM UTC 24
Finished Oct 12 08:04:27 AM UTC 24
Peak memory 588444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176844518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3176844518 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.2843597646
Short name T365
Test name
Test status
Simulation time 4358306693 ps
CPU time 15.51 seconds
Started Oct 12 07:57:12 AM UTC 24
Finished Oct 12 07:57:28 AM UTC 24
Peak memory 230260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843597646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2843597646 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.2008776379
Short name T371
Test name
Test status
Simulation time 354888048 ps
CPU time 25.99 seconds
Started Oct 12 07:57:23 AM UTC 24
Finished Oct 12 07:57:51 AM UTC 24
Peak memory 250620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008776379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2008776379 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.327056133
Short name T527
Test name
Test status
Simulation time 36454554759 ps
CPU time 1180.26 seconds
Started Oct 12 07:56:07 AM UTC 24
Finished Oct 12 08:16:01 AM UTC 24
Peak memory 1587816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327056133 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.327056133 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.136122013
Short name T404
Test name
Test status
Simulation time 52315222896 ps
CPU time 354.64 seconds
Started Oct 12 07:56:10 AM UTC 24
Finished Oct 12 08:02:10 AM UTC 24
Peak memory 498292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136122013 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.136122013 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload_invalid.1793896728
Short name T356
Test name
Test status
Simulation time 442530215 ps
CPU time 8.92 seconds
Started Oct 12 07:56:18 AM UTC 24
Finished Oct 12 07:56:28 AM UTC 24
Peak memory 237232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793896728 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload_invalid.1793896728 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.968804217
Short name T355
Test name
Test status
Simulation time 237401896 ps
CPU time 11.65 seconds
Started Oct 12 07:56:05 AM UTC 24
Finished Oct 12 07:56:18 AM UTC 24
Peak memory 237552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968804217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.968804217 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.2971667678
Short name T86
Test name
Test status
Simulation time 14150052478 ps
CPU time 286.36 seconds
Started Oct 12 07:57:25 AM UTC 24
Finished Oct 12 08:02:16 AM UTC 24
Peak memory 303708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971667678 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2971667678 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.2816693001
Short name T379
Test name
Test status
Simulation time 14439870 ps
CPU time 1.28 seconds
Started Oct 12 07:58:37 AM UTC 24
Finished Oct 12 07:58:39 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816693001 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2816693001 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_app.1460053017
Short name T386
Test name
Test status
Simulation time 4463791953 ps
CPU time 119.75 seconds
Started Oct 12 07:57:50 AM UTC 24
Finished Oct 12 07:59:52 AM UTC 24
Peak memory 324136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460053017 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.1460053017 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.3123916154
Short name T518
Test name
Test status
Simulation time 20286365424 ps
CPU time 1071.49 seconds
Started Oct 12 07:57:44 AM UTC 24
Finished Oct 12 08:15:48 AM UTC 24
Peak memory 264880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123916154 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3123916154 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.3284248680
Short name T383
Test name
Test status
Simulation time 897488107 ps
CPU time 49.79 seconds
Started Oct 12 07:58:19 AM UTC 24
Finished Oct 12 07:59:11 AM UTC 24
Peak memory 248172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284248680 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3284248680 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.3253215466
Short name T376
Test name
Test status
Simulation time 23403991 ps
CPU time 1.53 seconds
Started Oct 12 07:58:21 AM UTC 24
Finished Oct 12 07:58:24 AM UTC 24
Peak memory 226748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253215466 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3253215466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.1162214104
Short name T381
Test name
Test status
Simulation time 1442129738 ps
CPU time 57.08 seconds
Started Oct 12 07:57:52 AM UTC 24
Finished Oct 12 07:58:51 AM UTC 24
Peak memory 254564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162214104 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.1162214104 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_error.2221869190
Short name T406
Test name
Test status
Simulation time 68866176238 ps
CPU time 250.76 seconds
Started Oct 12 07:58:15 AM UTC 24
Finished Oct 12 08:02:30 AM UTC 24
Peak memory 418404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221869190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2221869190 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.300977931
Short name T378
Test name
Test status
Simulation time 6078889022 ps
CPU time 17.11 seconds
Started Oct 12 07:58:17 AM UTC 24
Finished Oct 12 07:58:36 AM UTC 24
Peak memory 232304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300977931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.300977931 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.3567341728
Short name T377
Test name
Test status
Simulation time 114706850 ps
CPU time 2.53 seconds
Started Oct 12 07:58:24 AM UTC 24
Finished Oct 12 07:58:28 AM UTC 24
Peak memory 234500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567341728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.3567341728 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.1962463915
Short name T696
Test name
Test status
Simulation time 52667739690 ps
CPU time 2292.85 seconds
Started Oct 12 07:57:36 AM UTC 24
Finished Oct 12 08:36:15 AM UTC 24
Peak memory 2662964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962463915 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.1962463915 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.2515227338
Short name T395
Test name
Test status
Simulation time 4185401335 ps
CPU time 176.45 seconds
Started Oct 12 07:57:37 AM UTC 24
Finished Oct 12 08:00:36 AM UTC 24
Peak memory 342628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515227338 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2515227338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload_invalid.3240312346
Short name T370
Test name
Test status
Simulation time 91507167 ps
CPU time 6.85 seconds
Started Oct 12 07:57:41 AM UTC 24
Finished Oct 12 07:57:49 AM UTC 24
Peak memory 238520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240312346 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload_invalid.3240312346 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.3557807717
Short name T367
Test name
Test status
Simulation time 152743414 ps
CPU time 1.94 seconds
Started Oct 12 07:57:32 AM UTC 24
Finished Oct 12 07:57:35 AM UTC 24
Peak memory 232120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557807717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3557807717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.995376623
Short name T455
Test name
Test status
Simulation time 19466014543 ps
CPU time 600.2 seconds
Started Oct 12 07:58:29 AM UTC 24
Finished Oct 12 08:08:37 AM UTC 24
Peak memory 551908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995376623 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.995376623 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.3976767787
Short name T131
Test name
Test status
Simulation time 15975769 ps
CPU time 1.32 seconds
Started Oct 12 07:31:05 AM UTC 24
Finished Oct 12 07:31:08 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976767787 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3976767787 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_app.1734447890
Short name T180
Test name
Test status
Simulation time 24938725098 ps
CPU time 357.77 seconds
Started Oct 12 07:29:39 AM UTC 24
Finished Oct 12 07:35:42 AM UTC 24
Peak memory 510768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734447890 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1734447890 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.1477049605
Short name T12
Test name
Test status
Simulation time 1371598345 ps
CPU time 28.46 seconds
Started Oct 12 07:29:40 AM UTC 24
Finished Oct 12 07:30:10 AM UTC 24
Peak memory 254424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477049605 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1477049605 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.108377874
Short name T155
Test name
Test status
Simulation time 49971411147 ps
CPU time 483.34 seconds
Started Oct 12 07:29:14 AM UTC 24
Finished Oct 12 07:37:23 AM UTC 24
Peak memory 248496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108377874 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.108377874 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2007163416
Short name T106
Test name
Test status
Simulation time 669695605 ps
CPU time 37.44 seconds
Started Oct 12 07:30:16 AM UTC 24
Finished Oct 12 07:30:55 AM UTC 24
Peak memory 237764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007163416 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2007163416 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.3997464121
Short name T203
Test name
Test status
Simulation time 6994953299 ps
CPU time 53.28 seconds
Started Oct 12 07:30:18 AM UTC 24
Finished Oct 12 07:31:14 AM UTC 24
Peak memory 237884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997464121 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3997464121 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.1981604836
Short name T102
Test name
Test status
Simulation time 19953648615 ps
CPU time 69.29 seconds
Started Oct 12 07:30:43 AM UTC 24
Finished Oct 12 07:31:54 AM UTC 24
Peak memory 236584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981604836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.1981604836 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.2863698014
Short name T52
Test name
Test status
Simulation time 2723848215 ps
CPU time 20.65 seconds
Started Oct 12 07:29:43 AM UTC 24
Finished Oct 12 07:30:05 AM UTC 24
Peak memory 246844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863698014 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.2863698014 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.3205252001
Short name T132
Test name
Test status
Simulation time 605968837 ps
CPU time 4.28 seconds
Started Oct 12 07:30:10 AM UTC 24
Finished Oct 12 07:30:16 AM UTC 24
Peak memory 232056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205252001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3205252001 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.3902022406
Short name T535
Test name
Test status
Simulation time 138448666237 ps
CPU time 2848.09 seconds
Started Oct 12 07:29:06 AM UTC 24
Finished Oct 12 08:17:03 AM UTC 24
Peak memory 3299948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902022406 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.3902022406 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.826930744
Short name T23
Test name
Test status
Simulation time 23957062687 ps
CPU time 228.36 seconds
Started Oct 12 07:29:58 AM UTC 24
Finished Oct 12 07:33:50 AM UTC 24
Peak memory 359356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826930744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.826930744 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.1043950759
Short name T22
Test name
Test status
Simulation time 1526965913 ps
CPU time 153.37 seconds
Started Oct 12 07:29:12 AM UTC 24
Finished Oct 12 07:31:48 AM UTC 24
Peak memory 274984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043950759 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1043950759 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload_invalid.3471653211
Short name T10
Test name
Test status
Simulation time 308999706 ps
CPU time 4.65 seconds
Started Oct 12 07:29:12 AM UTC 24
Finished Oct 12 07:29:18 AM UTC 24
Peak memory 236908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471653211 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload_invalid.3471653211 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.1011537297
Short name T66
Test name
Test status
Simulation time 2647016667 ps
CPU time 28.13 seconds
Started Oct 12 07:29:04 AM UTC 24
Finished Oct 12 07:29:33 AM UTC 24
Peak memory 236660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011537297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.1011537297 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.3367957948
Short name T158
Test name
Test status
Simulation time 18820043615 ps
CPU time 792.5 seconds
Started Oct 12 07:30:56 AM UTC 24
Finished Oct 12 07:44:18 AM UTC 24
Peak memory 582244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367957948 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3367957948 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.1063533032
Short name T34
Test name
Test status
Simulation time 6718988579 ps
CPU time 108.93 seconds
Started Oct 12 07:31:00 AM UTC 24
Finished Oct 12 07:32:51 AM UTC 24
Peak memory 283700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1063533032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_r
and_reset.1063533032 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.774470491
Short name T135
Test name
Test status
Simulation time 152210846 ps
CPU time 4.68 seconds
Started Oct 12 07:29:34 AM UTC 24
Finished Oct 12 07:29:39 AM UTC 24
Peak memory 232580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774470491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.774470491 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.2081111145
Short name T54
Test name
Test status
Simulation time 43067778 ps
CPU time 3.55 seconds
Started Oct 12 07:29:38 AM UTC 24
Finished Oct 12 07:29:42 AM UTC 24
Peak memory 232448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081111145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.2081111145 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.61201245
Short name T147
Test name
Test status
Simulation time 6385415421 ps
CPU time 61.04 seconds
Started Oct 12 07:29:15 AM UTC 24
Finished Oct 12 07:30:18 AM UTC 24
Peak memory 264784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61201245 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.61201245 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.479988448
Short name T532
Test name
Test status
Simulation time 154781399921 ps
CPU time 2813.44 seconds
Started Oct 12 07:29:16 AM UTC 24
Finished Oct 12 08:16:40 AM UTC 24
Peak memory 3088976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479988448 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.479988448 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.244741899
Short name T136
Test name
Test status
Simulation time 8507173982 ps
CPU time 37.86 seconds
Started Oct 12 07:29:18 AM UTC 24
Finished Oct 12 07:29:57 AM UTC 24
Peak memory 244256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244741899 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.244741899 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.3052900036
Short name T321
Test name
Test status
Simulation time 10053659044 ps
CPU time 1361.18 seconds
Started Oct 12 07:29:19 AM UTC 24
Finished Oct 12 07:52:17 AM UTC 24
Peak memory 727500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052900036 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3052900036 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.2599200184
Short name T197
Test name
Test status
Simulation time 31390087410 ps
CPU time 320.15 seconds
Started Oct 12 07:29:23 AM UTC 24
Finished Oct 12 07:34:48 AM UTC 24
Peak memory 285160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599200184 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.2599200184 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.4010382584
Short name T551
Test name
Test status
Simulation time 505561453443 ps
CPU time 2896.1 seconds
Started Oct 12 07:29:31 AM UTC 24
Finished Oct 12 08:18:20 AM UTC 24
Peak memory 3137928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010382584 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.4010382584 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.2515243850
Short name T391
Test name
Test status
Simulation time 29034441 ps
CPU time 1.39 seconds
Started Oct 12 08:00:00 AM UTC 24
Finished Oct 12 08:00:02 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515243850 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2515243850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_app.1290183530
Short name T439
Test name
Test status
Simulation time 66019507942 ps
CPU time 477.65 seconds
Started Oct 12 07:59:11 AM UTC 24
Finished Oct 12 08:07:16 AM UTC 24
Peak memory 528976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290183530 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1290183530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.1137039841
Short name T427
Test name
Test status
Simulation time 14081231102 ps
CPU time 399.45 seconds
Started Oct 12 07:58:58 AM UTC 24
Finished Oct 12 08:05:43 AM UTC 24
Peak memory 254700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137039841 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.1137039841 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2649449041
Short name T424
Test name
Test status
Simulation time 6341417665 ps
CPU time 349.55 seconds
Started Oct 12 07:59:34 AM UTC 24
Finished Oct 12 08:05:29 AM UTC 24
Peak memory 324196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649449041 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2649449041 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_error.645161911
Short name T429
Test name
Test status
Simulation time 16414816590 ps
CPU time 354.71 seconds
Started Oct 12 07:59:51 AM UTC 24
Finished Oct 12 08:05:50 AM UTC 24
Peak memory 367340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645161911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.645161911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.2231042649
Short name T389
Test name
Test status
Simulation time 1161055346 ps
CPU time 5 seconds
Started Oct 12 07:59:53 AM UTC 24
Finished Oct 12 07:59:59 AM UTC 24
Peak memory 230056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231042649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.2231042649 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.3633495741
Short name T59
Test name
Test status
Simulation time 1890890699 ps
CPU time 56.66 seconds
Started Oct 12 07:59:56 AM UTC 24
Finished Oct 12 08:00:54 AM UTC 24
Peak memory 266500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633495741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.3633495741 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.2058738695
Short name T732
Test name
Test status
Simulation time 73195385970 ps
CPU time 2551.88 seconds
Started Oct 12 07:58:42 AM UTC 24
Finished Oct 12 08:41:42 AM UTC 24
Peak memory 2908780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058738695 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.2058738695 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.1598913174
Short name T388
Test name
Test status
Simulation time 8698639647 ps
CPU time 66.68 seconds
Started Oct 12 07:58:47 AM UTC 24
Finished Oct 12 07:59:56 AM UTC 24
Peak memory 268952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598913174 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1598913174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload_invalid.3919694488
Short name T382
Test name
Test status
Simulation time 464217202 ps
CPU time 5.14 seconds
Started Oct 12 07:58:51 AM UTC 24
Finished Oct 12 07:58:57 AM UTC 24
Peak memory 237124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919694488 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload_invalid.3919694488 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.2452305357
Short name T384
Test name
Test status
Simulation time 9694492791 ps
CPU time 51.73 seconds
Started Oct 12 07:58:40 AM UTC 24
Finished Oct 12 07:59:33 AM UTC 24
Peak memory 234496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452305357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2452305357 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.3565369716
Short name T563
Test name
Test status
Simulation time 90661017409 ps
CPU time 1158.26 seconds
Started Oct 12 07:59:56 AM UTC 24
Finished Oct 12 08:19:28 AM UTC 24
Peak memory 1335892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565369716 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.3565369716 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.487308074
Short name T402
Test name
Test status
Simulation time 79375073 ps
CPU time 1.32 seconds
Started Oct 12 08:01:52 AM UTC 24
Finished Oct 12 08:01:55 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487308074 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.487308074 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_app.3189493686
Short name T423
Test name
Test status
Simulation time 11423184254 ps
CPU time 248.46 seconds
Started Oct 12 08:00:37 AM UTC 24
Finished Oct 12 08:04:49 AM UTC 24
Peak memory 418540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189493686 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3189493686 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.3984604395
Short name T444
Test name
Test status
Simulation time 87008318622 ps
CPU time 431.68 seconds
Started Oct 12 08:00:26 AM UTC 24
Finished Oct 12 08:07:44 AM UTC 24
Peak memory 254504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984604395 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3984604395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.3034708665
Short name T433
Test name
Test status
Simulation time 13330427267 ps
CPU time 311.9 seconds
Started Oct 12 08:00:55 AM UTC 24
Finished Oct 12 08:06:11 AM UTC 24
Peak memory 442984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034708665 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.3034708665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_error.414523235
Short name T447
Test name
Test status
Simulation time 50814355252 ps
CPU time 425.38 seconds
Started Oct 12 08:01:10 AM UTC 24
Finished Oct 12 08:08:21 AM UTC 24
Peak memory 564016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414523235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.414523235 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.865709648
Short name T398
Test name
Test status
Simulation time 1451093107 ps
CPU time 5.32 seconds
Started Oct 12 08:01:26 AM UTC 24
Finished Oct 12 08:01:33 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865709648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.865709648 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.989634499
Short name T399
Test name
Test status
Simulation time 67880306 ps
CPU time 1.86 seconds
Started Oct 12 08:01:33 AM UTC 24
Finished Oct 12 08:01:36 AM UTC 24
Peak memory 235964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989634499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.989634499 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.3223897685
Short name T654
Test name
Test status
Simulation time 298190827654 ps
CPU time 1891.06 seconds
Started Oct 12 08:00:06 AM UTC 24
Finished Oct 12 08:31:59 AM UTC 24
Peak memory 2233020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223897685 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.3223897685 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.4189587458
Short name T416
Test name
Test status
Simulation time 5135903263 ps
CPU time 226.18 seconds
Started Oct 12 08:00:17 AM UTC 24
Finished Oct 12 08:04:07 AM UTC 24
Peak memory 295596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189587458 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.4189587458 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload_invalid.3140673163
Short name T394
Test name
Test status
Simulation time 134667381 ps
CPU time 3.57 seconds
Started Oct 12 08:00:21 AM UTC 24
Finished Oct 12 08:00:26 AM UTC 24
Peak memory 236704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140673163 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload_invalid.3140673163 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.2890878771
Short name T400
Test name
Test status
Simulation time 3611288096 ps
CPU time 108.62 seconds
Started Oct 12 08:00:00 AM UTC 24
Finished Oct 12 08:01:51 AM UTC 24
Peak memory 238236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890878771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2890878771 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.1998063427
Short name T548
Test name
Test status
Simulation time 9093242650 ps
CPU time 984.16 seconds
Started Oct 12 08:01:37 AM UTC 24
Finished Oct 12 08:18:13 AM UTC 24
Peak memory 735824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998063427 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.1998063427 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.1843798232
Short name T411
Test name
Test status
Simulation time 10982268 ps
CPU time 1.27 seconds
Started Oct 12 08:03:06 AM UTC 24
Finished Oct 12 08:03:08 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843798232 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1843798232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_app.1937892523
Short name T415
Test name
Test status
Simulation time 5708264891 ps
CPU time 97.14 seconds
Started Oct 12 08:02:22 AM UTC 24
Finished Oct 12 08:04:02 AM UTC 24
Peak memory 260632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937892523 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1937892523 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.4193033971
Short name T450
Test name
Test status
Simulation time 19913785393 ps
CPU time 366.74 seconds
Started Oct 12 08:02:17 AM UTC 24
Finished Oct 12 08:08:29 AM UTC 24
Peak memory 242412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193033971 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.4193033971 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_error.3291179221
Short name T407
Test name
Test status
Simulation time 116732363 ps
CPU time 13.62 seconds
Started Oct 12 08:02:31 AM UTC 24
Finished Oct 12 08:02:46 AM UTC 24
Peak memory 250412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291179221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3291179221 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.4013288832
Short name T410
Test name
Test status
Simulation time 1206940055 ps
CPU time 15.86 seconds
Started Oct 12 08:02:47 AM UTC 24
Finished Oct 12 08:03:04 AM UTC 24
Peak memory 232052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013288832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.4013288832 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.2053544616
Short name T409
Test name
Test status
Simulation time 46934379 ps
CPU time 2.1 seconds
Started Oct 12 08:02:52 AM UTC 24
Finished Oct 12 08:02:55 AM UTC 24
Peak memory 236592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053544616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2053544616 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.3052909899
Short name T638
Test name
Test status
Simulation time 40982683516 ps
CPU time 1602.11 seconds
Started Oct 12 08:01:56 AM UTC 24
Finished Oct 12 08:28:56 AM UTC 24
Peak memory 2046504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052909899 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.3052909899 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.1303956054
Short name T469
Test name
Test status
Simulation time 44310464227 ps
CPU time 498.73 seconds
Started Oct 12 08:01:57 AM UTC 24
Finished Oct 12 08:10:22 AM UTC 24
Peak memory 649796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303956054 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1303956054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload_invalid.3275472356
Short name T405
Test name
Test status
Simulation time 419411528 ps
CPU time 9.29 seconds
Started Oct 12 08:02:11 AM UTC 24
Finished Oct 12 08:02:21 AM UTC 24
Peak memory 236908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275472356 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload_invalid.3275472356 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.4189703977
Short name T403
Test name
Test status
Simulation time 19505128 ps
CPU time 2.06 seconds
Started Oct 12 08:01:52 AM UTC 24
Finished Oct 12 08:01:56 AM UTC 24
Peak memory 232408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189703977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.4189703977 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.970613511
Short name T549
Test name
Test status
Simulation time 31358089665 ps
CPU time 908.3 seconds
Started Oct 12 08:02:56 AM UTC 24
Finished Oct 12 08:18:15 AM UTC 24
Peak memory 879772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970613511 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.970613511 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.3533356454
Short name T422
Test name
Test status
Simulation time 38589991 ps
CPU time 1.25 seconds
Started Oct 12 08:04:36 AM UTC 24
Finished Oct 12 08:04:38 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533356454 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3533356454 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_app.2204473933
Short name T440
Test name
Test status
Simulation time 15152345213 ps
CPU time 186.06 seconds
Started Oct 12 08:04:08 AM UTC 24
Finished Oct 12 08:07:17 AM UTC 24
Peak memory 391840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204473933 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.2204473933 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.1341593389
Short name T494
Test name
Test status
Simulation time 16173804387 ps
CPU time 533.6 seconds
Started Oct 12 08:04:02 AM UTC 24
Finished Oct 12 08:13:03 AM UTC 24
Peak memory 244328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341593389 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.1341593389 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.565985582
Short name T420
Test name
Test status
Simulation time 2016671131 ps
CPU time 19.79 seconds
Started Oct 12 08:04:09 AM UTC 24
Finished Oct 12 08:04:30 AM UTC 24
Peak memory 248364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565985582 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.565985582 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_error.3356558372
Short name T428
Test name
Test status
Simulation time 37331268120 ps
CPU time 97.06 seconds
Started Oct 12 08:04:10 AM UTC 24
Finished Oct 12 08:05:49 AM UTC 24
Peak memory 303728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356558372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3356558372 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.2333538004
Short name T421
Test name
Test status
Simulation time 163032372 ps
CPU time 3.52 seconds
Started Oct 12 08:04:28 AM UTC 24
Finished Oct 12 08:04:32 AM UTC 24
Peak memory 232108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333538004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2333538004 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.2176953622
Short name T60
Test name
Test status
Simulation time 169803632 ps
CPU time 2.15 seconds
Started Oct 12 08:04:32 AM UTC 24
Finished Oct 12 08:04:35 AM UTC 24
Peak memory 236360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176953622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2176953622 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.1420519223
Short name T614
Test name
Test status
Simulation time 25089860780 ps
CPU time 1321.69 seconds
Started Oct 12 08:03:52 AM UTC 24
Finished Oct 12 08:26:09 AM UTC 24
Peak memory 975444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420519223 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.1420519223 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.3632489653
Short name T457
Test name
Test status
Simulation time 31072746540 ps
CPU time 286.75 seconds
Started Oct 12 08:03:52 AM UTC 24
Finished Oct 12 08:08:43 AM UTC 24
Peak memory 457448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632489653 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3632489653 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload_invalid.1793062566
Short name T418
Test name
Test status
Simulation time 195474423 ps
CPU time 7.23 seconds
Started Oct 12 08:04:00 AM UTC 24
Finished Oct 12 08:04:08 AM UTC 24
Peak memory 237008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793062566 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload_invalid.1793062566 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.1705150869
Short name T413
Test name
Test status
Simulation time 2800864241 ps
CPU time 41.03 seconds
Started Oct 12 08:03:09 AM UTC 24
Finished Oct 12 08:03:51 AM UTC 24
Peak memory 238180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705150869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1705150869 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.2160826141
Short name T515
Test name
Test status
Simulation time 7967494587 ps
CPU time 660.38 seconds
Started Oct 12 08:04:33 AM UTC 24
Finished Oct 12 08:15:42 AM UTC 24
Peak memory 529480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160826141 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2160826141 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.2606338015
Short name T432
Test name
Test status
Simulation time 13760795 ps
CPU time 1.28 seconds
Started Oct 12 08:06:07 AM UTC 24
Finished Oct 12 08:06:10 AM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606338015 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2606338015 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_app.1031699391
Short name T435
Test name
Test status
Simulation time 809538260 ps
CPU time 48 seconds
Started Oct 12 08:05:43 AM UTC 24
Finished Oct 12 08:06:32 AM UTC 24
Peak memory 244400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031699391 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1031699391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.3931087621
Short name T635
Test name
Test status
Simulation time 34612842307 ps
CPU time 1367.48 seconds
Started Oct 12 08:05:34 AM UTC 24
Finished Oct 12 08:28:37 AM UTC 24
Peak memory 272936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931087621 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3931087621 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.2367653945
Short name T481
Test name
Test status
Simulation time 16711146552 ps
CPU time 348.54 seconds
Started Oct 12 08:05:44 AM UTC 24
Finished Oct 12 08:11:37 AM UTC 24
Peak memory 440928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367653945 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.2367653945 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_error.3889939412
Short name T520
Test name
Test status
Simulation time 51504765870 ps
CPU time 595.04 seconds
Started Oct 12 08:05:50 AM UTC 24
Finished Oct 12 08:15:53 AM UTC 24
Peak memory 582384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889939412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3889939412 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.1911547410
Short name T430
Test name
Test status
Simulation time 2309816202 ps
CPU time 9.38 seconds
Started Oct 12 08:05:51 AM UTC 24
Finished Oct 12 08:06:02 AM UTC 24
Peak memory 230320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911547410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1911547410 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.3828722627
Short name T61
Test name
Test status
Simulation time 40527959 ps
CPU time 2 seconds
Started Oct 12 08:06:02 AM UTC 24
Finished Oct 12 08:06:05 AM UTC 24
Peak memory 235904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828722627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.3828722627 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3208427757
Short name T733
Test name
Test status
Simulation time 197341747353 ps
CPU time 2188.11 seconds
Started Oct 12 08:04:50 AM UTC 24
Finished Oct 12 08:41:42 AM UTC 24
Peak memory 2538092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208427757 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3208427757 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.1803518463
Short name T500
Test name
Test status
Simulation time 21402023837 ps
CPU time 494.01 seconds
Started Oct 12 08:05:14 AM UTC 24
Finished Oct 12 08:13:35 AM UTC 24
Peak memory 381480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803518463 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1803518463 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload_invalid.4074756178
Short name T425
Test name
Test status
Simulation time 129140518 ps
CPU time 2.16 seconds
Started Oct 12 08:05:30 AM UTC 24
Finished Oct 12 08:05:33 AM UTC 24
Peak memory 234824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074756178 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload_invalid.4074756178 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.2692531769
Short name T426
Test name
Test status
Simulation time 3025096955 ps
CPU time 61.63 seconds
Started Oct 12 08:04:39 AM UTC 24
Finished Oct 12 08:05:42 AM UTC 24
Peak memory 238216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692531769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2692531769 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.3754368695
Short name T644
Test name
Test status
Simulation time 44085728783 ps
CPU time 1435.73 seconds
Started Oct 12 08:06:06 AM UTC 24
Finished Oct 12 08:30:19 AM UTC 24
Peak memory 648120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754368695 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3754368695 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.1268616896
Short name T441
Test name
Test status
Simulation time 41519401 ps
CPU time 1.29 seconds
Started Oct 12 08:07:21 AM UTC 24
Finished Oct 12 08:07:23 AM UTC 24
Peak memory 227104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268616896 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1268616896 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_app.1237761406
Short name T451
Test name
Test status
Simulation time 4367001242 ps
CPU time 113 seconds
Started Oct 12 08:06:35 AM UTC 24
Finished Oct 12 08:08:30 AM UTC 24
Peak memory 305772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237761406 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1237761406 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.2330465199
Short name T467
Test name
Test status
Simulation time 7823239020 ps
CPU time 196.43 seconds
Started Oct 12 08:06:34 AM UTC 24
Finished Oct 12 08:09:53 AM UTC 24
Peak memory 238236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330465199 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2330465199 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.3143241803
Short name T478
Test name
Test status
Simulation time 9664721945 ps
CPU time 255.8 seconds
Started Oct 12 08:06:42 AM UTC 24
Finished Oct 12 08:11:02 AM UTC 24
Peak memory 324312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143241803 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3143241803 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_error.2740972352
Short name T501
Test name
Test status
Simulation time 5239782196 ps
CPU time 404.61 seconds
Started Oct 12 08:06:46 AM UTC 24
Finished Oct 12 08:13:36 AM UTC 24
Peak memory 385836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740972352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2740972352 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.2958677261
Short name T442
Test name
Test status
Simulation time 1160477139 ps
CPU time 15.51 seconds
Started Oct 12 08:07:13 AM UTC 24
Finished Oct 12 08:07:30 AM UTC 24
Peak memory 232108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958677261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.2958677261 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.791002254
Short name T57
Test name
Test status
Simulation time 227087852 ps
CPU time 2.01 seconds
Started Oct 12 08:07:16 AM UTC 24
Finished Oct 12 08:07:20 AM UTC 24
Peak memory 234512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791002254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.791002254 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.3365915079
Short name T737
Test name
Test status
Simulation time 19776066491 ps
CPU time 2195.02 seconds
Started Oct 12 08:06:12 AM UTC 24
Finished Oct 12 08:43:14 AM UTC 24
Peak memory 1366620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365915079 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.3365915079 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.398848343
Short name T491
Test name
Test status
Simulation time 44849730502 ps
CPU time 387.71 seconds
Started Oct 12 08:06:17 AM UTC 24
Finished Oct 12 08:12:49 AM UTC 24
Peak memory 486008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398848343 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.398848343 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload_invalid.3090159935
Short name T438
Test name
Test status
Simulation time 138706319 ps
CPU time 11.01 seconds
Started Oct 12 08:06:33 AM UTC 24
Finished Oct 12 08:06:45 AM UTC 24
Peak memory 236848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090159935 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload_invalid.3090159935 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.3981520628
Short name T443
Test name
Test status
Simulation time 22812850605 ps
CPU time 87.62 seconds
Started Oct 12 08:06:10 AM UTC 24
Finished Oct 12 08:07:40 AM UTC 24
Peak memory 238192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981520628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3981520628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.3090317061
Short name T496
Test name
Test status
Simulation time 47073312351 ps
CPU time 347.74 seconds
Started Oct 12 08:07:19 AM UTC 24
Finished Oct 12 08:13:11 AM UTC 24
Peak memory 352876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090317061 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3090317061 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.584995765
Short name T453
Test name
Test status
Simulation time 16718037 ps
CPU time 1.34 seconds
Started Oct 12 08:08:34 AM UTC 24
Finished Oct 12 08:08:36 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584995765 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.584995765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_app.208090296
Short name T449
Test name
Test status
Simulation time 917953184 ps
CPU time 23.27 seconds
Started Oct 12 08:08:03 AM UTC 24
Finished Oct 12 08:08:28 AM UTC 24
Peak memory 238120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208090296 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.208090296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.2079005935
Short name T516
Test name
Test status
Simulation time 41322507349 ps
CPU time 460.69 seconds
Started Oct 12 08:07:56 AM UTC 24
Finished Oct 12 08:15:43 AM UTC 24
Peak memory 254560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079005935 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2079005935 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.4080849464
Short name T487
Test name
Test status
Simulation time 5165751131 ps
CPU time 217.33 seconds
Started Oct 12 08:08:21 AM UTC 24
Finished Oct 12 08:12:02 AM UTC 24
Peak memory 307796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080849464 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.4080849464 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_error.2055372230
Short name T460
Test name
Test status
Simulation time 9120914535 ps
CPU time 51.57 seconds
Started Oct 12 08:08:23 AM UTC 24
Finished Oct 12 08:09:17 AM UTC 24
Peak memory 281196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055372230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2055372230 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.3574083527
Short name T456
Test name
Test status
Simulation time 2917756306 ps
CPU time 9.96 seconds
Started Oct 12 08:08:29 AM UTC 24
Finished Oct 12 08:08:40 AM UTC 24
Peak memory 232124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574083527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3574083527 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.1347429074
Short name T452
Test name
Test status
Simulation time 530686289 ps
CPU time 2.64 seconds
Started Oct 12 08:08:30 AM UTC 24
Finished Oct 12 08:08:33 AM UTC 24
Peak memory 236416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347429074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.1347429074 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.2483912240
Short name T770
Test name
Test status
Simulation time 81900525340 ps
CPU time 4019.06 seconds
Started Oct 12 08:07:31 AM UTC 24
Finished Oct 12 09:15:13 AM UTC 24
Peak memory 3893952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483912240 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.2483912240 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.1206180320
Short name T524
Test name
Test status
Simulation time 17541975588 ps
CPU time 487.73 seconds
Started Oct 12 08:07:41 AM UTC 24
Finished Oct 12 08:15:55 AM UTC 24
Peak memory 602860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206180320 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1206180320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload_invalid.1034686620
Short name T445
Test name
Test status
Simulation time 227778054 ps
CPU time 8.8 seconds
Started Oct 12 08:07:45 AM UTC 24
Finished Oct 12 08:07:55 AM UTC 24
Peak memory 236940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034686620 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload_invalid.1034686620 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.1153032973
Short name T459
Test name
Test status
Simulation time 2018309938 ps
CPU time 85.1 seconds
Started Oct 12 08:07:24 AM UTC 24
Finished Oct 12 08:08:51 AM UTC 24
Peak memory 234424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153032973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1153032973 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.519934970
Short name T741
Test name
Test status
Simulation time 48583282027 ps
CPU time 2128.47 seconds
Started Oct 12 08:08:31 AM UTC 24
Finished Oct 12 08:44:24 AM UTC 24
Peak memory 1006572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519934970 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.519934970 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.1140279628
Short name T465
Test name
Test status
Simulation time 88986854 ps
CPU time 1.29 seconds
Started Oct 12 08:09:38 AM UTC 24
Finished Oct 12 08:09:40 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140279628 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.1140279628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_app.599932581
Short name T473
Test name
Test status
Simulation time 19601790567 ps
CPU time 118.29 seconds
Started Oct 12 08:08:44 AM UTC 24
Finished Oct 12 08:10:45 AM UTC 24
Peak memory 315952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599932581 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.599932581 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.1813023564
Short name T667
Test name
Test status
Simulation time 129209108565 ps
CPU time 1473.42 seconds
Started Oct 12 08:08:44 AM UTC 24
Finished Oct 12 08:33:35 AM UTC 24
Peak memory 273104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813023564 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1813023564 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3290285736
Short name T526
Test name
Test status
Simulation time 57839099851 ps
CPU time 422.72 seconds
Started Oct 12 08:08:51 AM UTC 24
Finished Oct 12 08:16:00 AM UTC 24
Peak memory 486056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290285736 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3290285736 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_error.3601460009
Short name T470
Test name
Test status
Simulation time 14320223778 ps
CPU time 77.11 seconds
Started Oct 12 08:09:07 AM UTC 24
Finished Oct 12 08:10:26 AM UTC 24
Peak memory 285288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601460009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3601460009 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.1965636243
Short name T462
Test name
Test status
Simulation time 4793525462 ps
CPU time 16.3 seconds
Started Oct 12 08:09:18 AM UTC 24
Finished Oct 12 08:09:35 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965636243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1965636243 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.3509966306
Short name T464
Test name
Test status
Simulation time 151708729 ps
CPU time 2.42 seconds
Started Oct 12 08:09:34 AM UTC 24
Finished Oct 12 08:09:37 AM UTC 24
Peak memory 236352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509966306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.3509966306 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.1153252848
Short name T761
Test name
Test status
Simulation time 29116568878 ps
CPU time 2869.07 seconds
Started Oct 12 08:08:37 AM UTC 24
Finished Oct 12 08:56:58 AM UTC 24
Peak memory 1720940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153252848 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.1153252848 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.3020449777
Short name T503
Test name
Test status
Simulation time 104346848309 ps
CPU time 304.15 seconds
Started Oct 12 08:08:38 AM UTC 24
Finished Oct 12 08:13:46 AM UTC 24
Peak memory 471648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020449777 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3020449777 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload_invalid.114265311
Short name T458
Test name
Test status
Simulation time 21924423 ps
CPU time 2.18 seconds
Started Oct 12 08:08:40 AM UTC 24
Finished Oct 12 08:08:43 AM UTC 24
Peak memory 234420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114265311 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload_invalid.114265311 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.3275802603
Short name T463
Test name
Test status
Simulation time 4716118994 ps
CPU time 58.49 seconds
Started Oct 12 08:08:37 AM UTC 24
Finished Oct 12 08:09:37 AM UTC 24
Peak memory 238160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275802603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3275802603 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.4280499601
Short name T480
Test name
Test status
Simulation time 3941308069 ps
CPU time 99.97 seconds
Started Oct 12 08:09:36 AM UTC 24
Finished Oct 12 08:11:18 AM UTC 24
Peak memory 254564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280499601 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.4280499601 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.2651811285
Short name T476
Test name
Test status
Simulation time 80496335 ps
CPU time 1.32 seconds
Started Oct 12 08:10:52 AM UTC 24
Finished Oct 12 08:10:55 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651811285 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2651811285 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_app.1331647908
Short name T471
Test name
Test status
Simulation time 674186860 ps
CPU time 8.02 seconds
Started Oct 12 08:10:23 AM UTC 24
Finished Oct 12 08:10:32 AM UTC 24
Peak memory 234464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331647908 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1331647908 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.693741312
Short name T702
Test name
Test status
Simulation time 28456266906 ps
CPU time 1594.17 seconds
Started Oct 12 08:10:00 AM UTC 24
Finished Oct 12 08:36:53 AM UTC 24
Peak memory 281200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693741312 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.693741312 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.689447908
Short name T521
Test name
Test status
Simulation time 49750166470 ps
CPU time 320.44 seconds
Started Oct 12 08:10:28 AM UTC 24
Finished Oct 12 08:15:53 AM UTC 24
Peak memory 447092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689447908 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.689447908 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.2217270825
Short name T475
Test name
Test status
Simulation time 1877082167 ps
CPU time 12.12 seconds
Started Oct 12 08:10:38 AM UTC 24
Finished Oct 12 08:10:51 AM UTC 24
Peak memory 232048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217270825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.2217270825 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.197649665
Short name T474
Test name
Test status
Simulation time 53033193 ps
CPU time 2.51 seconds
Started Oct 12 08:10:46 AM UTC 24
Finished Oct 12 08:10:50 AM UTC 24
Peak memory 236560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197649665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.197649665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.550480511
Short name T666
Test name
Test status
Simulation time 13372574399 ps
CPU time 1409.69 seconds
Started Oct 12 08:09:41 AM UTC 24
Finished Oct 12 08:33:27 AM UTC 24
Peak memory 1016480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550480511 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.550480511 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.970597226
Short name T498
Test name
Test status
Simulation time 10171435049 ps
CPU time 204.65 seconds
Started Oct 12 08:09:50 AM UTC 24
Finished Oct 12 08:13:18 AM UTC 24
Peak memory 307760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970597226 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.970597226 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload_invalid.2432105717
Short name T468
Test name
Test status
Simulation time 74221316 ps
CPU time 3.98 seconds
Started Oct 12 08:09:54 AM UTC 24
Finished Oct 12 08:09:59 AM UTC 24
Peak memory 237188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432105717 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload_invalid.2432105717 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.2206594682
Short name T484
Test name
Test status
Simulation time 21976977348 ps
CPU time 128.89 seconds
Started Oct 12 08:09:38 AM UTC 24
Finished Oct 12 08:11:49 AM UTC 24
Peak memory 240228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206594682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2206594682 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.4001208497
Short name T721
Test name
Test status
Simulation time 287419092366 ps
CPU time 1656.18 seconds
Started Oct 12 08:10:50 AM UTC 24
Finished Oct 12 08:38:45 AM UTC 24
Peak memory 685212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001208497 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.4001208497 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.1538137516
Short name T486
Test name
Test status
Simulation time 16258981 ps
CPU time 1.28 seconds
Started Oct 12 08:11:58 AM UTC 24
Finished Oct 12 08:12:00 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538137516 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1538137516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_app.3844277422
Short name T488
Test name
Test status
Simulation time 7540451356 ps
CPU time 65.18 seconds
Started Oct 12 08:11:18 AM UTC 24
Finished Oct 12 08:12:25 AM UTC 24
Peak memory 268904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844277422 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.3844277422 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.3858842679
Short name T642
Test name
Test status
Simulation time 101671227726 ps
CPU time 1083.76 seconds
Started Oct 12 08:11:18 AM UTC 24
Finished Oct 12 08:29:35 AM UTC 24
Peak memory 268852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858842679 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3858842679 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.1405886635
Short name T545
Test name
Test status
Simulation time 19925714514 ps
CPU time 391.09 seconds
Started Oct 12 08:11:19 AM UTC 24
Finished Oct 12 08:17:56 AM UTC 24
Peak memory 328300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405886635 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1405886635 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_error.2792818479
Short name T528
Test name
Test status
Simulation time 13529102389 ps
CPU time 270.88 seconds
Started Oct 12 08:11:38 AM UTC 24
Finished Oct 12 08:16:13 AM UTC 24
Peak memory 330280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792818479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.2792818479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.1701473685
Short name T483
Test name
Test status
Simulation time 1940471179 ps
CPU time 7.84 seconds
Started Oct 12 08:11:39 AM UTC 24
Finished Oct 12 08:11:48 AM UTC 24
Peak memory 230060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701473685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.1701473685 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.57750534
Short name T759
Test name
Test status
Simulation time 57405708321 ps
CPU time 2635.95 seconds
Started Oct 12 08:11:00 AM UTC 24
Finished Oct 12 08:55:26 AM UTC 24
Peak memory 2789936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57750534 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.57750534 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.3888270305
Short name T534
Test name
Test status
Simulation time 206350964515 ps
CPU time 350.2 seconds
Started Oct 12 08:11:02 AM UTC 24
Finished Oct 12 08:16:57 AM UTC 24
Peak memory 494316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888270305 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3888270305 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.1688504581
Short name T485
Test name
Test status
Simulation time 7929888536 ps
CPU time 58.77 seconds
Started Oct 12 08:10:56 AM UTC 24
Finished Oct 12 08:11:57 AM UTC 24
Peak memory 238180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688504581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1688504581 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.518283457
Short name T661
Test name
Test status
Simulation time 202201566934 ps
CPU time 1235.59 seconds
Started Oct 12 08:11:51 AM UTC 24
Finished Oct 12 08:32:40 AM UTC 24
Peak memory 598976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518283457 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.518283457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.448066506
Short name T207
Test name
Test status
Simulation time 118266681 ps
CPU time 1.33 seconds
Started Oct 12 07:32:52 AM UTC 24
Finished Oct 12 07:32:54 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448066506 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.448066506 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_app.3379569136
Short name T227
Test name
Test status
Simulation time 51859755040 ps
CPU time 442.41 seconds
Started Oct 12 07:32:08 AM UTC 24
Finished Oct 12 07:39:36 AM UTC 24
Peak memory 490124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379569136 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3379569136 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.3704700634
Short name T124
Test name
Test status
Simulation time 6633890901 ps
CPU time 104.25 seconds
Started Oct 12 07:32:08 AM UTC 24
Finished Oct 12 07:33:54 AM UTC 24
Peak memory 293428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704700634 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.3704700634 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.2380618768
Short name T159
Test name
Test status
Simulation time 17430129347 ps
CPU time 928.93 seconds
Started Oct 12 07:31:34 AM UTC 24
Finished Oct 12 07:47:14 AM UTC 24
Peak memory 250412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380618768 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.2380618768 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.3737707317
Short name T80
Test name
Test status
Simulation time 379726301 ps
CPU time 1.97 seconds
Started Oct 12 07:32:36 AM UTC 24
Finished Oct 12 07:32:39 AM UTC 24
Peak memory 230076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737707317 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3737707317 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.3202769744
Short name T85
Test name
Test status
Simulation time 18646331 ps
CPU time 1.39 seconds
Started Oct 12 07:32:40 AM UTC 24
Finished Oct 12 07:32:43 AM UTC 24
Peak memory 226752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202769744 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.3202769744 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.808751980
Short name T6
Test name
Test status
Simulation time 43385181637 ps
CPU time 69.47 seconds
Started Oct 12 07:32:44 AM UTC 24
Finished Oct 12 07:33:55 AM UTC 24
Peak memory 238164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808751980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.808751980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_error.2501882532
Short name T71
Test name
Test status
Simulation time 18610215878 ps
CPU time 403.97 seconds
Started Oct 12 07:32:13 AM UTC 24
Finished Oct 12 07:39:03 AM UTC 24
Peak memory 359004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501882532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2501882532 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.3540464631
Short name T206
Test name
Test status
Simulation time 1424098690 ps
CPU time 13.94 seconds
Started Oct 12 07:32:33 AM UTC 24
Finished Oct 12 07:32:48 AM UTC 24
Peak memory 230008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540464631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3540464631 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.3419764059
Short name T44
Test name
Test status
Simulation time 70305691 ps
CPU time 2.33 seconds
Started Oct 12 07:32:44 AM UTC 24
Finished Oct 12 07:32:47 AM UTC 24
Peak memory 236428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419764059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3419764059 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.1794240573
Short name T764
Test name
Test status
Simulation time 132982768608 ps
CPU time 5237.67 seconds
Started Oct 12 07:31:14 AM UTC 24
Finished Oct 12 08:59:29 AM UTC 24
Peak memory 4799112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794240573 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.1794240573 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.1873461772
Short name T96
Test name
Test status
Simulation time 17180202156 ps
CPU time 265.7 seconds
Started Oct 12 07:32:10 AM UTC 24
Finished Oct 12 07:36:40 AM UTC 24
Peak memory 322452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873461772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1873461772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.914456744
Short name T133
Test name
Test status
Simulation time 12519479940 ps
CPU time 54.9 seconds
Started Oct 12 07:32:49 AM UTC 24
Finished Oct 12 07:33:45 AM UTC 24
Peak memory 280384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914456744 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.914456744 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.3410073374
Short name T27
Test name
Test status
Simulation time 2756611249 ps
CPU time 219.65 seconds
Started Oct 12 07:31:19 AM UTC 24
Finished Oct 12 07:35:03 AM UTC 24
Peak memory 305768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410073374 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3410073374 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload_invalid.1804718654
Short name T15
Test name
Test status
Simulation time 118132727 ps
CPU time 9.81 seconds
Started Oct 12 07:31:26 AM UTC 24
Finished Oct 12 07:31:38 AM UTC 24
Peak memory 236876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804718654 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload_invalid.1804718654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.1269316114
Short name T201
Test name
Test status
Simulation time 15702221209 ps
CPU time 95.46 seconds
Started Oct 12 07:31:08 AM UTC 24
Finished Oct 12 07:32:46 AM UTC 24
Peak memory 238284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269316114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1269316114 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all_with_rand_reset.1602736899
Short name T93
Test name
Test status
Simulation time 2357011698 ps
CPU time 80.97 seconds
Started Oct 12 07:32:48 AM UTC 24
Finished Oct 12 07:34:11 AM UTC 24
Peak memory 293580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1602736899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_r
and_reset.1602736899 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.210148467
Short name T103
Test name
Test status
Simulation time 427783619 ps
CPU time 4.84 seconds
Started Oct 12 07:31:55 AM UTC 24
Finished Oct 12 07:32:01 AM UTC 24
Peak memory 232424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210148467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.210148467 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.1802566954
Short name T104
Test name
Test status
Simulation time 238322191 ps
CPU time 3.67 seconds
Started Oct 12 07:32:03 AM UTC 24
Finished Oct 12 07:32:07 AM UTC 24
Peak memory 232388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802566954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.1802566954 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.1317308402
Short name T205
Test name
Test status
Simulation time 5837965880 ps
CPU time 62.18 seconds
Started Oct 12 07:31:39 AM UTC 24
Finished Oct 12 07:32:43 AM UTC 24
Peak memory 264736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317308402 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1317308402 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.1378144192
Short name T512
Test name
Test status
Simulation time 61800555436 ps
CPU time 2578 seconds
Started Oct 12 07:31:42 AM UTC 24
Finished Oct 12 08:15:09 AM UTC 24
Peak memory 3037776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378144192 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1378144192 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.3097722181
Short name T204
Test name
Test status
Simulation time 38299963888 ps
CPU time 46.92 seconds
Started Oct 12 07:31:44 AM UTC 24
Finished Oct 12 07:32:33 AM UTC 24
Peak memory 244220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097722181 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3097722181 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.2164590978
Short name T105
Test name
Test status
Simulation time 1294877073 ps
CPU time 23 seconds
Started Oct 12 07:31:48 AM UTC 24
Finished Oct 12 07:32:12 AM UTC 24
Peak memory 232428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164590978 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2164590978 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3579611673
Short name T497
Test name
Test status
Simulation time 77423788602 ps
CPU time 2454.09 seconds
Started Oct 12 07:31:49 AM UTC 24
Finished Oct 12 08:13:13 AM UTC 24
Peak memory 1343948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579611673 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3579611673 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.4118447184
Short name T436
Test name
Test status
Simulation time 17020281852 ps
CPU time 2055.21 seconds
Started Oct 12 07:31:55 AM UTC 24
Finished Oct 12 08:06:34 AM UTC 24
Peak memory 1130960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118447184 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.4118447184 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.3304478275
Short name T495
Test name
Test status
Simulation time 12852102 ps
CPU time 1.25 seconds
Started Oct 12 08:13:04 AM UTC 24
Finished Oct 12 08:13:06 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304478275 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3304478275 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_app.3858296022
Short name T561
Test name
Test status
Simulation time 44301978413 ps
CPU time 375.41 seconds
Started Oct 12 08:12:37 AM UTC 24
Finished Oct 12 08:18:59 AM UTC 24
Peak memory 500280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858296022 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3858296022 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.23188282
Short name T615
Test name
Test status
Simulation time 70282161220 ps
CPU time 815.97 seconds
Started Oct 12 08:12:28 AM UTC 24
Finished Oct 12 08:26:14 AM UTC 24
Peak memory 260724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23188282 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.23188282 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.1767467151
Short name T565
Test name
Test status
Simulation time 14934588004 ps
CPU time 418.82 seconds
Started Oct 12 08:12:38 AM UTC 24
Finished Oct 12 08:19:42 AM UTC 24
Peak memory 518756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767467151 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1767467151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_error.2356121181
Short name T538
Test name
Test status
Simulation time 61454100667 ps
CPU time 277.65 seconds
Started Oct 12 08:12:40 AM UTC 24
Finished Oct 12 08:17:21 AM UTC 24
Peak memory 453160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356121181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2356121181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.21181946
Short name T492
Test name
Test status
Simulation time 105581446 ps
CPU time 2.58 seconds
Started Oct 12 08:12:51 AM UTC 24
Finished Oct 12 08:12:54 AM UTC 24
Peak memory 229976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21181946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.21181946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.4070007851
Short name T493
Test name
Test status
Simulation time 93247207 ps
CPU time 2.11 seconds
Started Oct 12 08:12:55 AM UTC 24
Finished Oct 12 08:12:58 AM UTC 24
Peak memory 234368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070007851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.4070007851 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.2097420607
Short name T775
Test name
Test status
Simulation time 130621174918 ps
CPU time 5049.41 seconds
Started Oct 12 08:12:03 AM UTC 24
Finished Oct 12 09:37:06 AM UTC 24
Peak memory 4782796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097420607 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.2097420607 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.3350078349
Short name T582
Test name
Test status
Simulation time 92385398137 ps
CPU time 568.27 seconds
Started Oct 12 08:12:04 AM UTC 24
Finished Oct 12 08:21:40 AM UTC 24
Peak memory 633388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350078349 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3350078349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload_invalid.3289618013
Short name T489
Test name
Test status
Simulation time 1020248933 ps
CPU time 9.81 seconds
Started Oct 12 08:12:26 AM UTC 24
Finished Oct 12 08:12:37 AM UTC 24
Peak memory 236880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289618013 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload_invalid.3289618013 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.45287830
Short name T668
Test name
Test status
Simulation time 57012895468 ps
CPU time 1222.46 seconds
Started Oct 12 08:12:59 AM UTC 24
Finished Oct 12 08:33:36 AM UTC 24
Peak memory 1354464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45287830 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.45287830 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.2473232986
Short name T507
Test name
Test status
Simulation time 43656548 ps
CPU time 1.27 seconds
Started Oct 12 08:14:15 AM UTC 24
Finished Oct 12 08:14:18 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473232986 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.2473232986 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_app.356596187
Short name T510
Test name
Test status
Simulation time 868304452 ps
CPU time 64.76 seconds
Started Oct 12 08:13:37 AM UTC 24
Finished Oct 12 08:14:43 AM UTC 24
Peak memory 254456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356596187 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.356596187 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.268855306
Short name T558
Test name
Test status
Simulation time 9361754720 ps
CPU time 322.5 seconds
Started Oct 12 08:13:26 AM UTC 24
Finished Oct 12 08:18:54 AM UTC 24
Peak memory 244208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268855306 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.268855306 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.3781835936
Short name T508
Test name
Test status
Simulation time 9459499977 ps
CPU time 55.08 seconds
Started Oct 12 08:13:37 AM UTC 24
Finished Oct 12 08:14:33 AM UTC 24
Peak memory 262708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781835936 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3781835936 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_error.2190099653
Short name T562
Test name
Test status
Simulation time 4704180147 ps
CPU time 329.44 seconds
Started Oct 12 08:13:38 AM UTC 24
Finished Oct 12 08:19:12 AM UTC 24
Peak memory 336488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190099653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2190099653 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.792094950
Short name T504
Test name
Test status
Simulation time 652674094 ps
CPU time 8.31 seconds
Started Oct 12 08:13:47 AM UTC 24
Finished Oct 12 08:13:56 AM UTC 24
Peak memory 230008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792094950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.792094950 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.3263050961
Short name T505
Test name
Test status
Simulation time 523514219 ps
CPU time 2 seconds
Started Oct 12 08:13:57 AM UTC 24
Finished Oct 12 08:14:00 AM UTC 24
Peak memory 235904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263050961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.3263050961 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.1370477716
Short name T744
Test name
Test status
Simulation time 170008850376 ps
CPU time 1923.45 seconds
Started Oct 12 08:13:12 AM UTC 24
Finished Oct 12 08:45:37 AM UTC 24
Peak memory 2157160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370477716 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.1370477716 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.2451568457
Short name T559
Test name
Test status
Simulation time 13916689097 ps
CPU time 335.83 seconds
Started Oct 12 08:13:14 AM UTC 24
Finished Oct 12 08:18:55 AM UTC 24
Peak memory 528932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451568457 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2451568457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload_invalid.4159538052
Short name T499
Test name
Test status
Simulation time 246095090 ps
CPU time 5.39 seconds
Started Oct 12 08:13:19 AM UTC 24
Finished Oct 12 08:13:26 AM UTC 24
Peak memory 237268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159538052 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload_invalid.4159538052 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.1609162633
Short name T506
Test name
Test status
Simulation time 2882770262 ps
CPU time 65.12 seconds
Started Oct 12 08:13:07 AM UTC 24
Finished Oct 12 08:14:14 AM UTC 24
Peak memory 238184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609162633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.1609162633 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.1678734226
Short name T589
Test name
Test status
Simulation time 12466981321 ps
CPU time 477.55 seconds
Started Oct 12 08:14:01 AM UTC 24
Finished Oct 12 08:22:05 AM UTC 24
Peak memory 334840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678734226 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1678734226 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.1649717302
Short name T519
Test name
Test status
Simulation time 17568314 ps
CPU time 1.32 seconds
Started Oct 12 08:15:49 AM UTC 24
Finished Oct 12 08:15:52 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649717302 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1649717302 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_app.412778853
Short name T593
Test name
Test status
Simulation time 7844932822 ps
CPU time 442.69 seconds
Started Oct 12 08:15:10 AM UTC 24
Finished Oct 12 08:22:39 AM UTC 24
Peak memory 359076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412778853 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.412778853 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.3455036732
Short name T740
Test name
Test status
Simulation time 143128431763 ps
CPU time 1741.5 seconds
Started Oct 12 08:14:57 AM UTC 24
Finished Oct 12 08:44:18 AM UTC 24
Peak memory 283312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455036732 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3455036732 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.1173673765
Short name T537
Test name
Test status
Simulation time 64621068579 ps
CPU time 103.62 seconds
Started Oct 12 08:15:35 AM UTC 24
Finished Oct 12 08:17:21 AM UTC 24
Peak memory 309840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173673765 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.1173673765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_error.226954390
Short name T585
Test name
Test status
Simulation time 27089980279 ps
CPU time 366.54 seconds
Started Oct 12 08:15:38 AM UTC 24
Finished Oct 12 08:21:50 AM UTC 24
Peak memory 510576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226954390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.226954390 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.2367074060
Short name T523
Test name
Test status
Simulation time 1670995395 ps
CPU time 10.51 seconds
Started Oct 12 08:15:43 AM UTC 24
Finished Oct 12 08:15:55 AM UTC 24
Peak memory 229992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367074060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2367074060 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.2003399913
Short name T517
Test name
Test status
Simulation time 48351830 ps
CPU time 1.93 seconds
Started Oct 12 08:15:44 AM UTC 24
Finished Oct 12 08:15:48 AM UTC 24
Peak memory 235904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003399913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2003399913 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.636238813
Short name T765
Test name
Test status
Simulation time 105041362997 ps
CPU time 2825.28 seconds
Started Oct 12 08:14:34 AM UTC 24
Finished Oct 12 09:02:11 AM UTC 24
Peak memory 2902568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636238813 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.636238813 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.2787903628
Short name T546
Test name
Test status
Simulation time 9807100978 ps
CPU time 203.2 seconds
Started Oct 12 08:14:39 AM UTC 24
Finished Oct 12 08:18:05 AM UTC 24
Peak memory 303720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787903628 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2787903628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload_invalid.3953576853
Short name T511
Test name
Test status
Simulation time 1110215690 ps
CPU time 11.01 seconds
Started Oct 12 08:14:44 AM UTC 24
Finished Oct 12 08:14:56 AM UTC 24
Peak memory 234996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953576853 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload_invalid.3953576853 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.732573910
Short name T513
Test name
Test status
Simulation time 2458585212 ps
CPU time 73.33 seconds
Started Oct 12 08:14:18 AM UTC 24
Finished Oct 12 08:15:33 AM UTC 24
Peak memory 236596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732573910 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.732573910 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.3387180592
Short name T769
Test name
Test status
Simulation time 93583581315 ps
CPU time 3500.82 seconds
Started Oct 12 08:15:48 AM UTC 24
Finished Oct 12 09:14:50 AM UTC 24
Peak memory 1434648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387180592 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3387180592 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.2217158200
Short name T531
Test name
Test status
Simulation time 33916359 ps
CPU time 0.98 seconds
Started Oct 12 08:16:19 AM UTC 24
Finished Oct 12 08:16:21 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217158200 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2217158200 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_app.2339337768
Short name T590
Test name
Test status
Simulation time 5522994703 ps
CPU time 365.79 seconds
Started Oct 12 08:15:56 AM UTC 24
Finished Oct 12 08:22:07 AM UTC 24
Peak memory 334580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339337768 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2339337768 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.1746785351
Short name T610
Test name
Test status
Simulation time 53130399519 ps
CPU time 577.7 seconds
Started Oct 12 08:15:56 AM UTC 24
Finished Oct 12 08:25:41 AM UTC 24
Peak memory 254700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746785351 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.1746785351 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.3933829599
Short name T606
Test name
Test status
Simulation time 32072205392 ps
CPU time 530.55 seconds
Started Oct 12 08:16:00 AM UTC 24
Finished Oct 12 08:24:58 AM UTC 24
Peak memory 569956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933829599 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3933829599 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_error.3796466878
Short name T584
Test name
Test status
Simulation time 15060616731 ps
CPU time 340.64 seconds
Started Oct 12 08:16:00 AM UTC 24
Finished Oct 12 08:21:46 AM UTC 24
Peak memory 342568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796466878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3796466878 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.2370798238
Short name T529
Test name
Test status
Simulation time 3975393881 ps
CPU time 13.32 seconds
Started Oct 12 08:16:02 AM UTC 24
Finished Oct 12 08:16:17 AM UTC 24
Peak memory 230064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370798238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2370798238 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.1063560724
Short name T530
Test name
Test status
Simulation time 53785233 ps
CPU time 2.26 seconds
Started Oct 12 08:16:14 AM UTC 24
Finished Oct 12 08:16:18 AM UTC 24
Peak memory 234344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063560724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1063560724 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.515622251
Short name T776
Test name
Test status
Simulation time 1449037007988 ps
CPU time 5096.04 seconds
Started Oct 12 08:15:54 AM UTC 24
Finished Oct 12 09:41:45 AM UTC 24
Peak memory 4285068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515622251 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.515622251 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.2801483216
Short name T605
Test name
Test status
Simulation time 31070865326 ps
CPU time 530.4 seconds
Started Oct 12 08:15:54 AM UTC 24
Finished Oct 12 08:24:51 AM UTC 24
Peak memory 582216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801483216 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2801483216 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload_invalid.3492245977
Short name T525
Test name
Test status
Simulation time 60323120 ps
CPU time 3.21 seconds
Started Oct 12 08:15:55 AM UTC 24
Finished Oct 12 08:15:59 AM UTC 24
Peak memory 236932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492245977 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload_invalid.3492245977 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.1973116813
Short name T533
Test name
Test status
Simulation time 2281639125 ps
CPU time 61.05 seconds
Started Oct 12 08:15:53 AM UTC 24
Finished Oct 12 08:16:55 AM UTC 24
Peak memory 238152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973116813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.1973116813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.2910379426
Short name T674
Test name
Test status
Simulation time 173624729923 ps
CPU time 1038.79 seconds
Started Oct 12 08:16:17 AM UTC 24
Finished Oct 12 08:33:48 AM UTC 24
Peak memory 320576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910379426 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2910379426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.3736719151
Short name T544
Test name
Test status
Simulation time 106207272 ps
CPU time 1.23 seconds
Started Oct 12 08:17:46 AM UTC 24
Finished Oct 12 08:17:48 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736719151 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3736719151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_app.46393888
Short name T597
Test name
Test status
Simulation time 16427862738 ps
CPU time 392.95 seconds
Started Oct 12 08:17:04 AM UTC 24
Finished Oct 12 08:23:42 AM UTC 24
Peak memory 524912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46393888 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.46393888 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.2706006303
Short name T583
Test name
Test status
Simulation time 17917760941 ps
CPU time 279.3 seconds
Started Oct 12 08:16:58 AM UTC 24
Finished Oct 12 08:21:42 AM UTC 24
Peak memory 254584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706006303 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.2706006303 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.2590280258
Short name T542
Test name
Test status
Simulation time 4071921746 ps
CPU time 38.56 seconds
Started Oct 12 08:17:07 AM UTC 24
Finished Oct 12 08:17:47 AM UTC 24
Peak memory 250984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590280258 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2590280258 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_error.1628186249
Short name T577
Test name
Test status
Simulation time 29173844165 ps
CPU time 240.78 seconds
Started Oct 12 08:17:21 AM UTC 24
Finished Oct 12 08:21:26 AM UTC 24
Peak memory 416488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628186249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1628186249 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.2185342327
Short name T540
Test name
Test status
Simulation time 6345794395 ps
CPU time 20.1 seconds
Started Oct 12 08:17:22 AM UTC 24
Finished Oct 12 08:17:44 AM UTC 24
Peak memory 232240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185342327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2185342327 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.1260723768
Short name T543
Test name
Test status
Simulation time 48699898 ps
CPU time 2.05 seconds
Started Oct 12 08:17:45 AM UTC 24
Finished Oct 12 08:17:48 AM UTC 24
Peak memory 234440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260723768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1260723768 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.2353881542
Short name T774
Test name
Test status
Simulation time 27289895935 ps
CPU time 3845.89 seconds
Started Oct 12 08:16:41 AM UTC 24
Finished Oct 12 09:21:31 AM UTC 24
Peak memory 1802952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353881542 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.2353881542 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.866185163
Short name T541
Test name
Test status
Simulation time 1867663543 ps
CPU time 51.75 seconds
Started Oct 12 08:16:52 AM UTC 24
Finished Oct 12 08:17:45 AM UTC 24
Peak memory 277012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866185163 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.866185163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload_invalid.3229864292
Short name T536
Test name
Test status
Simulation time 130136518 ps
CPU time 9.79 seconds
Started Oct 12 08:16:56 AM UTC 24
Finished Oct 12 08:17:07 AM UTC 24
Peak memory 237068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229864292 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload_invalid.3229864292 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.1460396208
Short name T539
Test name
Test status
Simulation time 2896579632 ps
CPU time 79.78 seconds
Started Oct 12 08:16:22 AM UTC 24
Finished Oct 12 08:17:43 AM UTC 24
Peak memory 238184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460396208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1460396208 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.480089717
Short name T747
Test name
Test status
Simulation time 117443558129 ps
CPU time 1694.31 seconds
Started Oct 12 08:17:45 AM UTC 24
Finished Oct 12 08:46:19 AM UTC 24
Peak memory 1172460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480089717 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.480089717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.1613907738
Short name T555
Test name
Test status
Simulation time 14803383 ps
CPU time 1.17 seconds
Started Oct 12 08:18:43 AM UTC 24
Finished Oct 12 08:18:45 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613907738 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1613907738 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_app.2079738105
Short name T568
Test name
Test status
Simulation time 1448847529 ps
CPU time 117.34 seconds
Started Oct 12 08:18:13 AM UTC 24
Finished Oct 12 08:20:13 AM UTC 24
Peak memory 268900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079738105 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.2079738105 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.2975328788
Short name T724
Test name
Test status
Simulation time 23846420970 ps
CPU time 1298.39 seconds
Started Oct 12 08:18:06 AM UTC 24
Finished Oct 12 08:40:00 AM UTC 24
Peak memory 270892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975328788 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.2975328788 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.2027869069
Short name T557
Test name
Test status
Simulation time 4529740763 ps
CPU time 33.14 seconds
Started Oct 12 08:18:14 AM UTC 24
Finished Oct 12 08:18:49 AM UTC 24
Peak memory 246380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027869069 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.2027869069 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_error.3531862997
Short name T632
Test name
Test status
Simulation time 6365331974 ps
CPU time 607.53 seconds
Started Oct 12 08:18:16 AM UTC 24
Finished Oct 12 08:28:31 AM UTC 24
Peak memory 412256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531862997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3531862997 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.3506325882
Short name T552
Test name
Test status
Simulation time 671962409 ps
CPU time 8.63 seconds
Started Oct 12 08:18:20 AM UTC 24
Finished Oct 12 08:18:29 AM UTC 24
Peak memory 232296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506325882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.3506325882 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.3172336708
Short name T553
Test name
Test status
Simulation time 825524913 ps
CPU time 20.66 seconds
Started Oct 12 08:18:21 AM UTC 24
Finished Oct 12 08:18:43 AM UTC 24
Peak memory 264820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172336708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3172336708 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.3781100418
Short name T727
Test name
Test status
Simulation time 12615460546 ps
CPU time 1332 seconds
Started Oct 12 08:17:49 AM UTC 24
Finished Oct 12 08:40:16 AM UTC 24
Peak memory 934640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781100418 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.3781100418 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.1344972406
Short name T579
Test name
Test status
Simulation time 6574993012 ps
CPU time 217.43 seconds
Started Oct 12 08:17:49 AM UTC 24
Finished Oct 12 08:21:30 AM UTC 24
Peak memory 310044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344972406 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1344972406 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload_invalid.1607397933
Short name T547
Test name
Test status
Simulation time 1616914921 ps
CPU time 13.69 seconds
Started Oct 12 08:17:57 AM UTC 24
Finished Oct 12 08:18:12 AM UTC 24
Peak memory 237656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607397933 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload_invalid.1607397933 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.189195833
Short name T550
Test name
Test status
Simulation time 5692946615 ps
CPU time 30 seconds
Started Oct 12 08:17:48 AM UTC 24
Finished Oct 12 08:18:19 AM UTC 24
Peak memory 238220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189195833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.189195833 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.1001386296
Short name T556
Test name
Test status
Simulation time 267830252 ps
CPU time 17.09 seconds
Started Oct 12 08:18:30 AM UTC 24
Finished Oct 12 08:18:48 AM UTC 24
Peak memory 238100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001386296 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1001386296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.3902529650
Short name T566
Test name
Test status
Simulation time 56829324 ps
CPU time 1.21 seconds
Started Oct 12 08:19:43 AM UTC 24
Finished Oct 12 08:19:45 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902529650 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3902529650 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_app.2658774732
Short name T570
Test name
Test status
Simulation time 12721618204 ps
CPU time 93.15 seconds
Started Oct 12 08:18:55 AM UTC 24
Finished Oct 12 08:20:30 AM UTC 24
Peak memory 309928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658774732 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2658774732 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.1188279057
Short name T750
Test name
Test status
Simulation time 36918966755 ps
CPU time 1695.6 seconds
Started Oct 12 08:18:54 AM UTC 24
Finished Oct 12 08:47:29 AM UTC 24
Peak memory 281140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188279057 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.1188279057 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.1617675206
Short name T602
Test name
Test status
Simulation time 31942621544 ps
CPU time 323.76 seconds
Started Oct 12 08:18:58 AM UTC 24
Finished Oct 12 08:24:27 AM UTC 24
Peak memory 475688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617675206 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1617675206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_error.4105926926
Short name T574
Test name
Test status
Simulation time 16916329116 ps
CPU time 123.14 seconds
Started Oct 12 08:19:00 AM UTC 24
Finished Oct 12 08:21:05 AM UTC 24
Peak memory 336564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105926926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.4105926926 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.975904230
Short name T564
Test name
Test status
Simulation time 7307301397 ps
CPU time 15.94 seconds
Started Oct 12 08:19:13 AM UTC 24
Finished Oct 12 08:19:30 AM UTC 24
Peak memory 230204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975904230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.975904230 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.436064637
Short name T748
Test name
Test status
Simulation time 76946885519 ps
CPU time 1648.64 seconds
Started Oct 12 08:18:46 AM UTC 24
Finished Oct 12 08:46:33 AM UTC 24
Peak memory 1948396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436064637 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.436064637 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.2563951472
Short name T637
Test name
Test status
Simulation time 84737255649 ps
CPU time 598.23 seconds
Started Oct 12 08:18:49 AM UTC 24
Finished Oct 12 08:28:55 AM UTC 24
Peak memory 625252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563951472 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2563951472 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload_invalid.2861332332
Short name T560
Test name
Test status
Simulation time 136522942 ps
CPU time 6.04 seconds
Started Oct 12 08:18:50 AM UTC 24
Finished Oct 12 08:18:57 AM UTC 24
Peak memory 236904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861332332 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload_invalid.2861332332 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.2983569199
Short name T567
Test name
Test status
Simulation time 9910535625 ps
CPU time 73.15 seconds
Started Oct 12 08:18:45 AM UTC 24
Finished Oct 12 08:20:00 AM UTC 24
Peak memory 238312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983569199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2983569199 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.3290749392
Short name T596
Test name
Test status
Simulation time 17540517529 ps
CPU time 246.34 seconds
Started Oct 12 08:19:31 AM UTC 24
Finished Oct 12 08:23:41 AM UTC 24
Peak memory 326396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290749392 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.3290749392 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.3353193413
Short name T576
Test name
Test status
Simulation time 10535649 ps
CPU time 1.23 seconds
Started Oct 12 08:21:18 AM UTC 24
Finished Oct 12 08:21:21 AM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353193413 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3353193413 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_app.2348731297
Short name T572
Test name
Test status
Simulation time 314092479 ps
CPU time 25.54 seconds
Started Oct 12 08:20:32 AM UTC 24
Finished Oct 12 08:20:58 AM UTC 24
Peak memory 238160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348731297 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2348731297 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.2972663523
Short name T678
Test name
Test status
Simulation time 33671789174 ps
CPU time 823.41 seconds
Started Oct 12 08:20:26 AM UTC 24
Finished Oct 12 08:34:19 AM UTC 24
Peak memory 250480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972663523 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.2972663523 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.1161815671
Short name T609
Test name
Test status
Simulation time 39737733086 ps
CPU time 285.9 seconds
Started Oct 12 08:20:50 AM UTC 24
Finished Oct 12 08:25:40 AM UTC 24
Peak memory 434792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161815671 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1161815671 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_error.3143849752
Short name T578
Test name
Test status
Simulation time 1512662438 ps
CPU time 27.07 seconds
Started Oct 12 08:21:00 AM UTC 24
Finished Oct 12 08:21:29 AM UTC 24
Peak memory 254508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143849752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3143849752 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.1869035103
Short name T575
Test name
Test status
Simulation time 3239584975 ps
CPU time 14.75 seconds
Started Oct 12 08:21:01 AM UTC 24
Finished Oct 12 08:21:17 AM UTC 24
Peak memory 230264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869035103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1869035103 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.3348918848
Short name T58
Test name
Test status
Simulation time 38148165 ps
CPU time 2.14 seconds
Started Oct 12 08:21:06 AM UTC 24
Finished Oct 12 08:21:09 AM UTC 24
Peak memory 234556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348918848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3348918848 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.1830438360
Short name T773
Test name
Test status
Simulation time 344406878443 ps
CPU time 3662.31 seconds
Started Oct 12 08:19:48 AM UTC 24
Finished Oct 12 09:21:31 AM UTC 24
Peak memory 3531376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830438360 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.1830438360 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.2284030308
Short name T599
Test name
Test status
Simulation time 19708330505 ps
CPU time 240.93 seconds
Started Oct 12 08:20:01 AM UTC 24
Finished Oct 12 08:24:06 AM UTC 24
Peak memory 438876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284030308 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.2284030308 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload_invalid.1589711838
Short name T569
Test name
Test status
Simulation time 712793212 ps
CPU time 10.42 seconds
Started Oct 12 08:20:13 AM UTC 24
Finished Oct 12 08:20:25 AM UTC 24
Peak memory 250564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589711838 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload_invalid.1589711838 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.1945832987
Short name T571
Test name
Test status
Simulation time 6887898039 ps
CPU time 61.51 seconds
Started Oct 12 08:19:46 AM UTC 24
Finished Oct 12 08:20:49 AM UTC 24
Peak memory 238156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945832987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1945832987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.227739514
Short name T594
Test name
Test status
Simulation time 23076832797 ps
CPU time 99.38 seconds
Started Oct 12 08:21:10 AM UTC 24
Finished Oct 12 08:22:52 AM UTC 24
Peak memory 285280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227739514 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.227739514 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.2875172222
Short name T588
Test name
Test status
Simulation time 20313639 ps
CPU time 1.24 seconds
Started Oct 12 08:21:58 AM UTC 24
Finished Oct 12 08:22:00 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875172222 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2875172222 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_app.1900416104
Short name T630
Test name
Test status
Simulation time 214386120344 ps
CPU time 388.2 seconds
Started Oct 12 08:21:40 AM UTC 24
Finished Oct 12 08:28:13 AM UTC 24
Peak memory 479984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900416104 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1900416104 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.2985019486
Short name T687
Test name
Test status
Simulation time 27839422677 ps
CPU time 791.45 seconds
Started Oct 12 08:21:36 AM UTC 24
Finished Oct 12 08:34:57 AM UTC 24
Peak memory 254508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985019486 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2985019486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.3217620218
Short name T603
Test name
Test status
Simulation time 10390717083 ps
CPU time 173.6 seconds
Started Oct 12 08:21:41 AM UTC 24
Finished Oct 12 08:24:37 AM UTC 24
Peak memory 328416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217620218 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3217620218 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_error.1101159812
Short name T648
Test name
Test status
Simulation time 78956960892 ps
CPU time 528.38 seconds
Started Oct 12 08:21:43 AM UTC 24
Finished Oct 12 08:30:38 AM UTC 24
Peak memory 621092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101159812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1101159812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.3643808523
Short name T587
Test name
Test status
Simulation time 2444699695 ps
CPU time 9.78 seconds
Started Oct 12 08:21:47 AM UTC 24
Finished Oct 12 08:21:58 AM UTC 24
Peak memory 232112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643808523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.3643808523 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.3334851888
Short name T586
Test name
Test status
Simulation time 116564562 ps
CPU time 2.03 seconds
Started Oct 12 08:21:50 AM UTC 24
Finished Oct 12 08:21:53 AM UTC 24
Peak memory 234436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334851888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3334851888 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.3143056396
Short name T766
Test name
Test status
Simulation time 80639796381 ps
CPU time 2577.7 seconds
Started Oct 12 08:21:26 AM UTC 24
Finished Oct 12 09:04:52 AM UTC 24
Peak memory 2857556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143056396 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.3143056396 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.187364403
Short name T595
Test name
Test status
Simulation time 3269647218 ps
CPU time 105.94 seconds
Started Oct 12 08:21:30 AM UTC 24
Finished Oct 12 08:23:18 AM UTC 24
Peak memory 303864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187364403 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.187364403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload_invalid.701079852
Short name T580
Test name
Test status
Simulation time 70081376 ps
CPU time 3.44 seconds
Started Oct 12 08:21:31 AM UTC 24
Finished Oct 12 08:21:35 AM UTC 24
Peak memory 234996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701079852 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload_invalid.701079852 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.600615753
Short name T581
Test name
Test status
Simulation time 937886007 ps
CPU time 16.91 seconds
Started Oct 12 08:21:21 AM UTC 24
Finished Oct 12 08:21:39 AM UTC 24
Peak memory 238228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600615753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.600615753 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.846409177
Short name T746
Test name
Test status
Simulation time 440297088825 ps
CPU time 1435.81 seconds
Started Oct 12 08:21:54 AM UTC 24
Finished Oct 12 08:46:07 AM UTC 24
Peak memory 1133152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846409177 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.846409177 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.2043052770
Short name T600
Test name
Test status
Simulation time 22793655 ps
CPU time 1.26 seconds
Started Oct 12 08:24:07 AM UTC 24
Finished Oct 12 08:24:09 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043052770 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.2043052770 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_app.1666312041
Short name T624
Test name
Test status
Simulation time 16672217624 ps
CPU time 252.56 seconds
Started Oct 12 08:22:40 AM UTC 24
Finished Oct 12 08:26:56 AM UTC 24
Peak memory 410292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666312041 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1666312041 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.2440016592
Short name T691
Test name
Test status
Simulation time 67218479805 ps
CPU time 777.32 seconds
Started Oct 12 08:22:31 AM UTC 24
Finished Oct 12 08:35:38 AM UTC 24
Peak memory 258828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440016592 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2440016592 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.362564737
Short name T613
Test name
Test status
Simulation time 25550772104 ps
CPU time 174.13 seconds
Started Oct 12 08:22:52 AM UTC 24
Finished Oct 12 08:25:49 AM UTC 24
Peak memory 289380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362564737 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.362564737 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_error.3229203043
Short name T37
Test name
Test status
Simulation time 10737112494 ps
CPU time 114.77 seconds
Started Oct 12 08:23:18 AM UTC 24
Finished Oct 12 08:25:15 AM UTC 24
Peak memory 320040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229203043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3229203043 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.1171012080
Short name T598
Test name
Test status
Simulation time 694796428 ps
CPU time 5.69 seconds
Started Oct 12 08:23:42 AM UTC 24
Finished Oct 12 08:23:49 AM UTC 24
Peak memory 230056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171012080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1171012080 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.4019491439
Short name T601
Test name
Test status
Simulation time 3912098165 ps
CPU time 35.06 seconds
Started Oct 12 08:23:43 AM UTC 24
Finished Oct 12 08:24:20 AM UTC 24
Peak memory 265016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019491439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.4019491439 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.2702166387
Short name T757
Test name
Test status
Simulation time 16428977036 ps
CPU time 1822.18 seconds
Started Oct 12 08:22:06 AM UTC 24
Finished Oct 12 08:52:49 AM UTC 24
Peak memory 1194604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702166387 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.2702166387 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.3708042344
Short name T659
Test name
Test status
Simulation time 18814397668 ps
CPU time 611.42 seconds
Started Oct 12 08:22:09 AM UTC 24
Finished Oct 12 08:32:28 AM UTC 24
Peak memory 608868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708042344 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.3708042344 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload_invalid.1369051111
Short name T592
Test name
Test status
Simulation time 805232300 ps
CPU time 8.5 seconds
Started Oct 12 08:22:21 AM UTC 24
Finished Oct 12 08:22:30 AM UTC 24
Peak memory 234824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369051111 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload_invalid.1369051111 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.3342632477
Short name T591
Test name
Test status
Simulation time 344666517 ps
CPU time 17.22 seconds
Started Oct 12 08:22:01 AM UTC 24
Finished Oct 12 08:22:20 AM UTC 24
Peak memory 236724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342632477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.3342632477 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.887576111
Short name T768
Test name
Test status
Simulation time 241234536808 ps
CPU time 2768.44 seconds
Started Oct 12 08:23:50 AM UTC 24
Finished Oct 12 09:10:31 AM UTC 24
Peak memory 1231888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887576111 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.887576111 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.3945203913
Short name T216
Test name
Test status
Simulation time 53979847 ps
CPU time 1.31 seconds
Started Oct 12 07:35:34 AM UTC 24
Finished Oct 12 07:35:36 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945203913 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3945203913 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_app.3582323336
Short name T239
Test name
Test status
Simulation time 31713049284 ps
CPU time 425.86 seconds
Started Oct 12 07:34:45 AM UTC 24
Finished Oct 12 07:41:56 AM UTC 24
Peak memory 524960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582323336 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3582323336 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.3225804693
Short name T235
Test name
Test status
Simulation time 17499221744 ps
CPU time 402.88 seconds
Started Oct 12 07:34:46 AM UTC 24
Finished Oct 12 07:41:34 AM UTC 24
Peak memory 555700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225804693 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3225804693 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.3475666808
Short name T392
Test name
Test status
Simulation time 130716633303 ps
CPU time 1565.66 seconds
Started Oct 12 07:33:52 AM UTC 24
Finished Oct 12 08:00:16 AM UTC 24
Peak memory 260716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475666808 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3475666808 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.175901056
Short name T81
Test name
Test status
Simulation time 115826879 ps
CPU time 1.6 seconds
Started Oct 12 07:35:09 AM UTC 24
Finished Oct 12 07:35:12 AM UTC 24
Peak memory 230008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175901056 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.175901056 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.2890824703
Short name T213
Test name
Test status
Simulation time 204876126 ps
CPU time 1.81 seconds
Started Oct 12 07:35:12 AM UTC 24
Finished Oct 12 07:35:15 AM UTC 24
Peak memory 230080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890824703 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2890824703 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.1626350518
Short name T215
Test name
Test status
Simulation time 2787247933 ps
CPU time 18.12 seconds
Started Oct 12 07:35:13 AM UTC 24
Finished Oct 12 07:35:33 AM UTC 24
Peak memory 232484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626350518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1626350518 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.339324794
Short name T76
Test name
Test status
Simulation time 5167557298 ps
CPU time 284.93 seconds
Started Oct 12 07:34:49 AM UTC 24
Finished Oct 12 07:39:38 AM UTC 24
Peak memory 313960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339324794 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.339324794 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_error.3209948550
Short name T172
Test name
Test status
Simulation time 11250374845 ps
CPU time 472.53 seconds
Started Oct 12 07:35:04 AM UTC 24
Finished Oct 12 07:43:03 AM UTC 24
Peak memory 410220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209948550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3209948550 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.1962731224
Short name T214
Test name
Test status
Simulation time 842991933 ps
CPU time 11 seconds
Started Oct 12 07:35:04 AM UTC 24
Finished Oct 12 07:35:16 AM UTC 24
Peak memory 232188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962731224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1962731224 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.4231497395
Short name T41
Test name
Test status
Simulation time 39701809 ps
CPU time 1.88 seconds
Started Oct 12 07:35:15 AM UTC 24
Finished Oct 12 07:35:18 AM UTC 24
Peak memory 233896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231497395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.4231497395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.2976068576
Short name T509
Test name
Test status
Simulation time 525043755926 ps
CPU time 2452.51 seconds
Started Oct 12 07:33:18 AM UTC 24
Finished Oct 12 08:14:37 AM UTC 24
Peak memory 2706020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976068576 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.2976068576 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.1367475703
Short name T97
Test name
Test status
Simulation time 7030031208 ps
CPU time 259.93 seconds
Started Oct 12 07:34:50 AM UTC 24
Finished Oct 12 07:39:14 AM UTC 24
Peak memory 392148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367475703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1367475703 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.2632819482
Short name T134
Test name
Test status
Simulation time 6546305047 ps
CPU time 73 seconds
Started Oct 12 07:35:31 AM UTC 24
Finished Oct 12 07:36:46 AM UTC 24
Peak memory 286404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632819482 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2632819482 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.1983417517
Short name T195
Test name
Test status
Simulation time 39765333976 ps
CPU time 361.24 seconds
Started Oct 12 07:33:39 AM UTC 24
Finished Oct 12 07:39:46 AM UTC 24
Peak memory 481956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983417517 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.1983417517 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload_invalid.3134814251
Short name T39
Test name
Test status
Simulation time 1003496552 ps
CPU time 9.48 seconds
Started Oct 12 07:33:46 AM UTC 24
Finished Oct 12 07:33:57 AM UTC 24
Peak memory 237076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134814251 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload_invalid.3134814251 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.1374764741
Short name T196
Test name
Test status
Simulation time 20801579376 ps
CPU time 96.62 seconds
Started Oct 12 07:32:55 AM UTC 24
Finished Oct 12 07:34:34 AM UTC 24
Peak memory 238236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374764741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1374764741 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.4020093822
Short name T95
Test name
Test status
Simulation time 4466752873 ps
CPU time 73.37 seconds
Started Oct 12 07:35:18 AM UTC 24
Finished Oct 12 07:36:33 AM UTC 24
Peak memory 269332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020093822 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.4020093822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.1259120406
Short name T210
Test name
Test status
Simulation time 575415971 ps
CPU time 3.31 seconds
Started Oct 12 07:34:39 AM UTC 24
Finished Oct 12 07:34:44 AM UTC 24
Peak memory 232584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259120406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.1259120406 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.3030357328
Short name T212
Test name
Test status
Simulation time 630245624 ps
CPU time 4.92 seconds
Started Oct 12 07:34:41 AM UTC 24
Finished Oct 12 07:34:47 AM UTC 24
Peak memory 232424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030357328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3030357328 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.1819293673
Short name T208
Test name
Test status
Simulation time 1317705414 ps
CPU time 42.33 seconds
Started Oct 12 07:33:55 AM UTC 24
Finished Oct 12 07:34:38 AM UTC 24
Peak memory 237724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819293673 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1819293673 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.471688980
Short name T437
Test name
Test status
Simulation time 17478662347 ps
CPU time 1942.17 seconds
Started Oct 12 07:33:56 AM UTC 24
Finished Oct 12 08:06:41 AM UTC 24
Peak memory 1147336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471688980 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.471688980 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.3838272455
Short name T209
Test name
Test status
Simulation time 1760286607 ps
CPU time 41.32 seconds
Started Oct 12 07:33:58 AM UTC 24
Finished Oct 12 07:34:41 AM UTC 24
Peak memory 244320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838272455 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3838272455 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.3341834701
Short name T211
Test name
Test status
Simulation time 1413889210 ps
CPU time 31.67 seconds
Started Oct 12 07:34:12 AM UTC 24
Finished Oct 12 07:34:45 AM UTC 24
Peak memory 234432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341834701 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3341834701 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.2039631495
Short name T200
Test name
Test status
Simulation time 8095224016 ps
CPU time 199.47 seconds
Started Oct 12 07:34:15 AM UTC 24
Finished Oct 12 07:37:38 AM UTC 24
Peak memory 448988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039631495 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2039631495 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.3895842774
Short name T199
Test name
Test status
Simulation time 10871166491 ps
CPU time 134.58 seconds
Started Oct 12 07:34:34 AM UTC 24
Finished Oct 12 07:36:51 AM UTC 24
Peak memory 367132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895842774 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3895842774 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.3580174243
Short name T611
Test name
Test status
Simulation time 21280972 ps
CPU time 1.27 seconds
Started Oct 12 08:25:42 AM UTC 24
Finished Oct 12 08:25:44 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580174243 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.3580174243 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_app.3796391368
Short name T626
Test name
Test status
Simulation time 4856601470 ps
CPU time 139.36 seconds
Started Oct 12 08:24:52 AM UTC 24
Finished Oct 12 08:27:14 AM UTC 24
Peak memory 316208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796391368 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3796391368 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.1354362244
Short name T749
Test name
Test status
Simulation time 27193239461 ps
CPU time 1301.2 seconds
Started Oct 12 08:24:44 AM UTC 24
Finished Oct 12 08:46:40 AM UTC 24
Peak memory 270952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354362244 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.1354362244 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.811072860
Short name T607
Test name
Test status
Simulation time 226598939 ps
CPU time 4.91 seconds
Started Oct 12 08:24:58 AM UTC 24
Finished Oct 12 08:25:04 AM UTC 24
Peak memory 236540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811072860 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.811072860 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_error.502270789
Short name T625
Test name
Test status
Simulation time 6062396228 ps
CPU time 125.02 seconds
Started Oct 12 08:25:05 AM UTC 24
Finished Oct 12 08:27:13 AM UTC 24
Peak memory 285416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502270789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.502270789 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.2996273319
Short name T608
Test name
Test status
Simulation time 7378663131 ps
CPU time 17.33 seconds
Started Oct 12 08:25:17 AM UTC 24
Finished Oct 12 08:25:35 AM UTC 24
Peak memory 230060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996273319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2996273319 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.2346357077
Short name T616
Test name
Test status
Simulation time 3892442808 ps
CPU time 41.58 seconds
Started Oct 12 08:25:36 AM UTC 24
Finished Oct 12 08:26:19 AM UTC 24
Peak memory 264892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346357077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2346357077 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.4054533424
Short name T777
Test name
Test status
Simulation time 2032758283193 ps
CPU time 5098.56 seconds
Started Oct 12 08:24:21 AM UTC 24
Finished Oct 12 09:50:15 AM UTC 24
Peak memory 4584144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054533424 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.4054533424 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.457701407
Short name T671
Test name
Test status
Simulation time 35693657236 ps
CPU time 544.68 seconds
Started Oct 12 08:24:28 AM UTC 24
Finished Oct 12 08:33:40 AM UTC 24
Peak memory 604904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457701407 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.457701407 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload_invalid.2483243789
Short name T604
Test name
Test status
Simulation time 80137020 ps
CPU time 4.07 seconds
Started Oct 12 08:24:38 AM UTC 24
Finished Oct 12 08:24:43 AM UTC 24
Peak memory 237776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483243789 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload_invalid.2483243789 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.310827692
Short name T612
Test name
Test status
Simulation time 9997129246 ps
CPU time 94.71 seconds
Started Oct 12 08:24:10 AM UTC 24
Finished Oct 12 08:25:46 AM UTC 24
Peak memory 234548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310827692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.310827692 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.4251191462
Short name T655
Test name
Test status
Simulation time 16102251444 ps
CPU time 383.18 seconds
Started Oct 12 08:25:41 AM UTC 24
Finished Oct 12 08:32:09 AM UTC 24
Peak memory 367608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251191462 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.4251191462 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.1007662894
Short name T623
Test name
Test status
Simulation time 14133015 ps
CPU time 1.29 seconds
Started Oct 12 08:26:53 AM UTC 24
Finished Oct 12 08:26:55 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007662894 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1007662894 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_app.1453605391
Short name T619
Test name
Test status
Simulation time 405912538 ps
CPU time 23.23 seconds
Started Oct 12 08:26:20 AM UTC 24
Finished Oct 12 08:26:44 AM UTC 24
Peak memory 253924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453605391 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1453605391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.3910569892
Short name T662
Test name
Test status
Simulation time 4072293088 ps
CPU time 381.57 seconds
Started Oct 12 08:26:15 AM UTC 24
Finished Oct 12 08:32:42 AM UTC 24
Peak memory 244460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910569892 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3910569892 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.1257701597
Short name T628
Test name
Test status
Simulation time 2043319607 ps
CPU time 80.66 seconds
Started Oct 12 08:26:23 AM UTC 24
Finished Oct 12 08:27:45 AM UTC 24
Peak memory 262700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257701597 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1257701597 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_error.1991656540
Short name T38
Test name
Test status
Simulation time 108830298158 ps
CPU time 429.91 seconds
Started Oct 12 08:26:42 AM UTC 24
Finished Oct 12 08:33:57 AM UTC 24
Peak memory 567916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991656540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.1991656540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.2236882621
Short name T620
Test name
Test status
Simulation time 71195303 ps
CPU time 2.04 seconds
Started Oct 12 08:26:45 AM UTC 24
Finished Oct 12 08:26:48 AM UTC 24
Peak memory 229916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236882621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2236882621 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.1689726766
Short name T622
Test name
Test status
Simulation time 54787960 ps
CPU time 2.12 seconds
Started Oct 12 08:26:49 AM UTC 24
Finished Oct 12 08:26:52 AM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689726766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1689726766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.3606637364
Short name T618
Test name
Test status
Simulation time 7589004106 ps
CPU time 51.77 seconds
Started Oct 12 08:25:47 AM UTC 24
Finished Oct 12 08:26:41 AM UTC 24
Peak memory 260900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606637364 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.3606637364 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.1669396184
Short name T665
Test name
Test status
Simulation time 49882687799 ps
CPU time 441.12 seconds
Started Oct 12 08:25:50 AM UTC 24
Finished Oct 12 08:33:17 AM UTC 24
Peak memory 592676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669396184 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1669396184 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload_invalid.1962866271
Short name T617
Test name
Test status
Simulation time 836546961 ps
CPU time 10.1 seconds
Started Oct 12 08:26:10 AM UTC 24
Finished Oct 12 08:26:22 AM UTC 24
Peak memory 236876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962866271 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload_invalid.1962866271 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.276990539
Short name T621
Test name
Test status
Simulation time 2359591395 ps
CPU time 62.16 seconds
Started Oct 12 08:25:45 AM UTC 24
Finished Oct 12 08:26:49 AM UTC 24
Peak memory 238352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276990539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.276990539 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.722156070
Short name T640
Test name
Test status
Simulation time 4507552668 ps
CPU time 136.91 seconds
Started Oct 12 08:26:50 AM UTC 24
Finished Oct 12 08:29:10 AM UTC 24
Peak memory 287268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722156070 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.722156070 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.871965024
Short name T636
Test name
Test status
Simulation time 43040159 ps
CPU time 1.28 seconds
Started Oct 12 08:28:37 AM UTC 24
Finished Oct 12 08:28:40 AM UTC 24
Peak memory 226924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871965024 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.871965024 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_app.2797231794
Short name T684
Test name
Test status
Simulation time 47390833738 ps
CPU time 401.91 seconds
Started Oct 12 08:27:46 AM UTC 24
Finished Oct 12 08:34:34 AM UTC 24
Peak memory 483944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797231794 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2797231794 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.2199565769
Short name T739
Test name
Test status
Simulation time 27550900355 ps
CPU time 960.8 seconds
Started Oct 12 08:27:22 AM UTC 24
Finished Oct 12 08:43:33 AM UTC 24
Peak memory 262952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199565769 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2199565769 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.529280586
Short name T643
Test name
Test status
Simulation time 10661572393 ps
CPU time 125.16 seconds
Started Oct 12 08:28:11 AM UTC 24
Finished Oct 12 08:30:19 AM UTC 24
Peak memory 260724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529280586 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.529280586 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_error.2538875053
Short name T685
Test name
Test status
Simulation time 77156719591 ps
CPU time 376.16 seconds
Started Oct 12 08:28:14 AM UTC 24
Finished Oct 12 08:34:36 AM UTC 24
Peak memory 561964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538875053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2538875053 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.4181504979
Short name T634
Test name
Test status
Simulation time 3653647067 ps
CPU time 19.18 seconds
Started Oct 12 08:28:16 AM UTC 24
Finished Oct 12 08:28:36 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181504979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.4181504979 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.2992702776
Short name T633
Test name
Test status
Simulation time 93032974 ps
CPU time 2.16 seconds
Started Oct 12 08:28:32 AM UTC 24
Finished Oct 12 08:28:36 AM UTC 24
Peak memory 236544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992702776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2992702776 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.687043466
Short name T631
Test name
Test status
Simulation time 2550799200 ps
CPU time 76.08 seconds
Started Oct 12 08:26:57 AM UTC 24
Finished Oct 12 08:28:15 AM UTC 24
Peak memory 316004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687043466 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.687043466 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.94746400
Short name T711
Test name
Test status
Simulation time 15974903276 ps
CPU time 630.75 seconds
Started Oct 12 08:27:14 AM UTC 24
Finished Oct 12 08:37:53 AM UTC 24
Peak memory 655924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94746400 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.94746400 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload_invalid.3439128972
Short name T627
Test name
Test status
Simulation time 152596992 ps
CPU time 4.15 seconds
Started Oct 12 08:27:16 AM UTC 24
Finished Oct 12 08:27:21 AM UTC 24
Peak memory 234864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439128972 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload_invalid.3439128972 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.1752552914
Short name T629
Test name
Test status
Simulation time 8554499990 ps
CPU time 72.1 seconds
Started Oct 12 08:26:56 AM UTC 24
Finished Oct 12 08:28:10 AM UTC 24
Peak memory 238160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752552914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.1752552914 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.527975726
Short name T653
Test name
Test status
Simulation time 9696108631 ps
CPU time 159.37 seconds
Started Oct 12 08:28:36 AM UTC 24
Finished Oct 12 08:31:18 AM UTC 24
Peak memory 306160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527975726 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.527975726 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.4223733570
Short name T647
Test name
Test status
Simulation time 16306019 ps
CPU time 1.34 seconds
Started Oct 12 08:30:28 AM UTC 24
Finished Oct 12 08:30:30 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223733570 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.4223733570 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_app.151326865
Short name T677
Test name
Test status
Simulation time 16561923533 ps
CPU time 291 seconds
Started Oct 12 08:29:11 AM UTC 24
Finished Oct 12 08:34:06 AM UTC 24
Peak memory 434796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151326865 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.151326865 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.3123313830
Short name T660
Test name
Test status
Simulation time 9067724179 ps
CPU time 204.66 seconds
Started Oct 12 08:29:10 AM UTC 24
Finished Oct 12 08:32:38 AM UTC 24
Peak memory 240380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123313830 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3123313830 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2274436120
Short name T676
Test name
Test status
Simulation time 7430476117 ps
CPU time 261.67 seconds
Started Oct 12 08:29:31 AM UTC 24
Finished Oct 12 08:33:57 AM UTC 24
Peak memory 369200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274436120 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2274436120 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_error.692606786
Short name T688
Test name
Test status
Simulation time 70787003545 ps
CPU time 336.45 seconds
Started Oct 12 08:29:36 AM UTC 24
Finished Oct 12 08:35:18 AM UTC 24
Peak memory 471764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692606786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.692606786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.2778049010
Short name T646
Test name
Test status
Simulation time 1879742251 ps
CPU time 6.32 seconds
Started Oct 12 08:30:20 AM UTC 24
Finished Oct 12 08:30:27 AM UTC 24
Peak memory 232052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778049010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2778049010 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.1533310606
Short name T645
Test name
Test status
Simulation time 78147928 ps
CPU time 1.81 seconds
Started Oct 12 08:30:20 AM UTC 24
Finished Oct 12 08:30:23 AM UTC 24
Peak memory 235940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533310606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1533310606 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.1149875624
Short name T755
Test name
Test status
Simulation time 12654548122 ps
CPU time 1336.72 seconds
Started Oct 12 08:28:41 AM UTC 24
Finished Oct 12 08:51:13 AM UTC 24
Peak memory 928384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149875624 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.1149875624 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.3419763531
Short name T641
Test name
Test status
Simulation time 337957992 ps
CPU time 33.15 seconds
Started Oct 12 08:28:56 AM UTC 24
Finished Oct 12 08:29:30 AM UTC 24
Peak memory 250400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419763531 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.3419763531 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload_invalid.19913604
Short name T639
Test name
Test status
Simulation time 541742084 ps
CPU time 10.9 seconds
Started Oct 12 08:28:57 AM UTC 24
Finished Oct 12 08:29:09 AM UTC 24
Peak memory 236872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19913604 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload_invalid.19913604 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.2146285658
Short name T649
Test name
Test status
Simulation time 15619176401 ps
CPU time 119.91 seconds
Started Oct 12 08:28:38 AM UTC 24
Finished Oct 12 08:30:41 AM UTC 24
Peak memory 240228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146285658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2146285658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.3660989118
Short name T692
Test name
Test status
Simulation time 34534989323 ps
CPU time 314.69 seconds
Started Oct 12 08:30:24 AM UTC 24
Finished Oct 12 08:35:43 AM UTC 24
Peak memory 394212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660989118 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3660989118 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.3822606492
Short name T658
Test name
Test status
Simulation time 11752521 ps
CPU time 1.23 seconds
Started Oct 12 08:32:23 AM UTC 24
Finished Oct 12 08:32:26 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822606492 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3822606492 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_app.2106373981
Short name T657
Test name
Test status
Simulation time 10057497472 ps
CPU time 64.24 seconds
Started Oct 12 08:31:16 AM UTC 24
Finished Oct 12 08:32:22 AM UTC 24
Peak memory 285256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106373981 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.2106373981 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.1978512036
Short name T699
Test name
Test status
Simulation time 24610780999 ps
CPU time 328.87 seconds
Started Oct 12 08:31:06 AM UTC 24
Finished Oct 12 08:36:39 AM UTC 24
Peak memory 246368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978512036 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1978512036 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.563287419
Short name T716
Test name
Test status
Simulation time 17727872543 ps
CPU time 408.77 seconds
Started Oct 12 08:31:19 AM UTC 24
Finished Oct 12 08:38:13 AM UTC 24
Peak memory 522956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563287419 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.563287419 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_error.1064832699
Short name T722
Test name
Test status
Simulation time 9712937241 ps
CPU time 410.61 seconds
Started Oct 12 08:32:00 AM UTC 24
Finished Oct 12 08:38:56 AM UTC 24
Peak memory 490164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064832699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1064832699 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.1842810470
Short name T656
Test name
Test status
Simulation time 2197572688 ps
CPU time 7.38 seconds
Started Oct 12 08:32:10 AM UTC 24
Finished Oct 12 08:32:19 AM UTC 24
Peak memory 230100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842810470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.1842810470 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.4259740141
Short name T63
Test name
Test status
Simulation time 173415757 ps
CPU time 2.13 seconds
Started Oct 12 08:32:19 AM UTC 24
Finished Oct 12 08:32:22 AM UTC 24
Peak memory 232356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259740141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.4259740141 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.1966049119
Short name T752
Test name
Test status
Simulation time 92466776538 ps
CPU time 1058.4 seconds
Started Oct 12 08:30:39 AM UTC 24
Finished Oct 12 08:48:31 AM UTC 24
Peak memory 1299048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966049119 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.1966049119 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.744434308
Short name T652
Test name
Test status
Simulation time 2656482333 ps
CPU time 32.44 seconds
Started Oct 12 08:30:41 AM UTC 24
Finished Oct 12 08:31:15 AM UTC 24
Peak memory 248496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744434308 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.744434308 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload_invalid.1906964111
Short name T651
Test name
Test status
Simulation time 199472443 ps
CPU time 9.72 seconds
Started Oct 12 08:30:54 AM UTC 24
Finished Oct 12 08:31:04 AM UTC 24
Peak memory 236900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906964111 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload_invalid.1906964111 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.293354761
Short name T650
Test name
Test status
Simulation time 944292338 ps
CPU time 20.03 seconds
Started Oct 12 08:30:31 AM UTC 24
Finished Oct 12 08:30:53 AM UTC 24
Peak memory 238224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293354761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.293354761 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.1558776611
Short name T756
Test name
Test status
Simulation time 209434112678 ps
CPU time 1128.41 seconds
Started Oct 12 08:32:22 AM UTC 24
Finished Oct 12 08:51:24 AM UTC 24
Peak memory 891576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558776611 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1558776611 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.375642022
Short name T673
Test name
Test status
Simulation time 36620727 ps
CPU time 1.35 seconds
Started Oct 12 08:33:39 AM UTC 24
Finished Oct 12 08:33:41 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375642022 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.375642022 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_app.2815270808
Short name T672
Test name
Test status
Simulation time 1053876726 ps
CPU time 44.6 seconds
Started Oct 12 08:32:54 AM UTC 24
Finished Oct 12 08:33:40 AM UTC 24
Peak memory 254380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815270808 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2815270808 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.1388507710
Short name T743
Test name
Test status
Simulation time 64122704863 ps
CPU time 720.34 seconds
Started Oct 12 08:32:43 AM UTC 24
Finished Oct 12 08:44:52 AM UTC 24
Peak memory 252712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388507710 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1388507710 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.731876872
Short name T707
Test name
Test status
Simulation time 39158678465 ps
CPU time 248.05 seconds
Started Oct 12 08:32:57 AM UTC 24
Finished Oct 12 08:37:09 AM UTC 24
Peak memory 396020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731876872 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.731876872 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_error.1715224563
Short name T695
Test name
Test status
Simulation time 6667199619 ps
CPU time 163.13 seconds
Started Oct 12 08:33:18 AM UTC 24
Finished Oct 12 08:36:04 AM UTC 24
Peak memory 381536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715224563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.1715224563 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.2287010511
Short name T669
Test name
Test status
Simulation time 659905315 ps
CPU time 8.99 seconds
Started Oct 12 08:33:27 AM UTC 24
Finished Oct 12 08:33:38 AM UTC 24
Peak memory 230188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287010511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2287010511 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.3382568337
Short name T670
Test name
Test status
Simulation time 32002746 ps
CPU time 2.14 seconds
Started Oct 12 08:33:36 AM UTC 24
Finished Oct 12 08:33:39 AM UTC 24
Peak memory 236420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382568337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3382568337 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.3772041357
Short name T742
Test name
Test status
Simulation time 6058545082 ps
CPU time 716.43 seconds
Started Oct 12 08:32:30 AM UTC 24
Finished Oct 12 08:44:35 AM UTC 24
Peak memory 592468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772041357 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.3772041357 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.2449034552
Short name T720
Test name
Test status
Simulation time 21367373313 ps
CPU time 356.31 seconds
Started Oct 12 08:32:39 AM UTC 24
Finished Oct 12 08:38:40 AM UTC 24
Peak memory 518764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449034552 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.2449034552 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload_invalid.3904497291
Short name T663
Test name
Test status
Simulation time 135695246 ps
CPU time 11.01 seconds
Started Oct 12 08:32:41 AM UTC 24
Finished Oct 12 08:32:53 AM UTC 24
Peak memory 234888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904497291 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload_invalid.3904497291 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.2315418529
Short name T664
Test name
Test status
Simulation time 656581147 ps
CPU time 28.43 seconds
Started Oct 12 08:32:27 AM UTC 24
Finished Oct 12 08:32:56 AM UTC 24
Peak memory 238160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315418529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.2315418529 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.2687336878
Short name T762
Test name
Test status
Simulation time 35004375174 ps
CPU time 1456.59 seconds
Started Oct 12 08:33:37 AM UTC 24
Finished Oct 12 08:58:10 AM UTC 24
Peak memory 982092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687336878 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2687336878 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.3033165665
Short name T683
Test name
Test status
Simulation time 27363089 ps
CPU time 1.29 seconds
Started Oct 12 08:34:25 AM UTC 24
Finished Oct 12 08:34:27 AM UTC 24
Peak memory 227224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033165665 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.3033165665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_app.1030214360
Short name T701
Test name
Test status
Simulation time 28781658953 ps
CPU time 175.14 seconds
Started Oct 12 08:33:52 AM UTC 24
Finished Oct 12 08:36:50 AM UTC 24
Peak memory 344632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030214360 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.1030214360 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.635723094
Short name T758
Test name
Test status
Simulation time 105379217430 ps
CPU time 1201.1 seconds
Started Oct 12 08:33:49 AM UTC 24
Finished Oct 12 08:54:04 AM UTC 24
Peak memory 271032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635723094 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.635723094 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.1594686071
Short name T681
Test name
Test status
Simulation time 1405481984 ps
CPU time 25.08 seconds
Started Oct 12 08:33:57 AM UTC 24
Finished Oct 12 08:34:24 AM UTC 24
Peak memory 254500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594686071 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.1594686071 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_error.178759624
Short name T705
Test name
Test status
Simulation time 12946658193 ps
CPU time 184.82 seconds
Started Oct 12 08:33:58 AM UTC 24
Finished Oct 12 08:37:06 AM UTC 24
Peak memory 361036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178759624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.178759624 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.3311239967
Short name T682
Test name
Test status
Simulation time 4870959364 ps
CPU time 15.44 seconds
Started Oct 12 08:34:08 AM UTC 24
Finished Oct 12 08:34:24 AM UTC 24
Peak memory 232232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311239967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3311239967 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.2114250008
Short name T679
Test name
Test status
Simulation time 78899522 ps
CPU time 2.18 seconds
Started Oct 12 08:34:20 AM UTC 24
Finished Oct 12 08:34:23 AM UTC 24
Peak memory 234340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114250008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2114250008 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.1612227838
Short name T700
Test name
Test status
Simulation time 18001381800 ps
CPU time 177.52 seconds
Started Oct 12 08:33:41 AM UTC 24
Finished Oct 12 08:36:41 AM UTC 24
Peak memory 387676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612227838 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.1612227838 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.10853567
Short name T712
Test name
Test status
Simulation time 34469558766 ps
CPU time 250.56 seconds
Started Oct 12 08:33:41 AM UTC 24
Finished Oct 12 08:37:55 AM UTC 24
Peak memory 451120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10853567 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.10853567 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload_invalid.3534875549
Short name T675
Test name
Test status
Simulation time 455919107 ps
CPU time 8.77 seconds
Started Oct 12 08:33:42 AM UTC 24
Finished Oct 12 08:33:52 AM UTC 24
Peak memory 235076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534875549 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload_invalid.3534875549 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.579821387
Short name T680
Test name
Test status
Simulation time 4564415775 ps
CPU time 42.51 seconds
Started Oct 12 08:33:40 AM UTC 24
Finished Oct 12 08:34:24 AM UTC 24
Peak memory 234500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579821387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.579821387 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.2377334817
Short name T754
Test name
Test status
Simulation time 58246971240 ps
CPU time 908.86 seconds
Started Oct 12 08:34:24 AM UTC 24
Finished Oct 12 08:49:44 AM UTC 24
Peak memory 371692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377334817 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.2377334817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.3294070192
Short name T694
Test name
Test status
Simulation time 19529680 ps
CPU time 1.24 seconds
Started Oct 12 08:35:44 AM UTC 24
Finished Oct 12 08:35:46 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294070192 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3294070192 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_app.4239652625
Short name T725
Test name
Test status
Simulation time 13700451397 ps
CPU time 327.42 seconds
Started Oct 12 08:34:38 AM UTC 24
Finished Oct 12 08:40:10 AM UTC 24
Peak memory 465456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239652625 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.4239652625 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.3840299026
Short name T760
Test name
Test status
Simulation time 23683785695 ps
CPU time 1318.41 seconds
Started Oct 12 08:34:36 AM UTC 24
Finished Oct 12 08:56:51 AM UTC 24
Peak memory 273012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840299026 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3840299026 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.796464036
Short name T719
Test name
Test status
Simulation time 27055296368 ps
CPU time 216.55 seconds
Started Oct 12 08:34:58 AM UTC 24
Finished Oct 12 08:38:38 AM UTC 24
Peak memory 309992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796464036 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.796464036 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_error.2459510443
Short name T726
Test name
Test status
Simulation time 3664947194 ps
CPU time 290.23 seconds
Started Oct 12 08:35:19 AM UTC 24
Finished Oct 12 08:40:13 AM UTC 24
Peak memory 336496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459510443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2459510443 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.1517175349
Short name T690
Test name
Test status
Simulation time 6762200064 ps
CPU time 10.56 seconds
Started Oct 12 08:35:23 AM UTC 24
Finished Oct 12 08:35:34 AM UTC 24
Peak memory 230096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517175349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1517175349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.570677209
Short name T693
Test name
Test status
Simulation time 684686216 ps
CPU time 10.21 seconds
Started Oct 12 08:35:35 AM UTC 24
Finished Oct 12 08:35:46 AM UTC 24
Peak memory 248388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570677209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.570677209 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.3294721962
Short name T772
Test name
Test status
Simulation time 59798796472 ps
CPU time 2727.44 seconds
Started Oct 12 08:34:25 AM UTC 24
Finished Oct 12 09:20:23 AM UTC 24
Peak memory 2888288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294721962 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.3294721962 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.128264672
Short name T730
Test name
Test status
Simulation time 144845207026 ps
CPU time 415.14 seconds
Started Oct 12 08:34:28 AM UTC 24
Finished Oct 12 08:41:30 AM UTC 24
Peak memory 504568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128264672 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.128264672 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload_invalid.3065888304
Short name T686
Test name
Test status
Simulation time 43060915 ps
CPU time 2.34 seconds
Started Oct 12 08:34:34 AM UTC 24
Finished Oct 12 08:34:38 AM UTC 24
Peak memory 234816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065888304 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload_invalid.3065888304 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.1464785292
Short name T689
Test name
Test status
Simulation time 8084525410 ps
CPU time 54.93 seconds
Started Oct 12 08:34:25 AM UTC 24
Finished Oct 12 08:35:22 AM UTC 24
Peak memory 236656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464785292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1464785292 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.3791928358
Short name T713
Test name
Test status
Simulation time 5267912146 ps
CPU time 145 seconds
Started Oct 12 08:35:39 AM UTC 24
Finished Oct 12 08:38:06 AM UTC 24
Peak memory 326624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791928358 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3791928358 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.789485906
Short name T706
Test name
Test status
Simulation time 29266209 ps
CPU time 1.29 seconds
Started Oct 12 08:37:04 AM UTC 24
Finished Oct 12 08:37:07 AM UTC 24
Peak memory 228720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789485906 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.789485906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_app.864013578
Short name T735
Test name
Test status
Simulation time 15167960489 ps
CPU time 363.62 seconds
Started Oct 12 08:36:27 AM UTC 24
Finished Oct 12 08:42:35 AM UTC 24
Peak memory 526828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864013578 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.864013578 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.3381957113
Short name T738
Test name
Test status
Simulation time 34496061716 ps
CPU time 408.4 seconds
Started Oct 12 08:36:27 AM UTC 24
Finished Oct 12 08:43:21 AM UTC 24
Peak memory 254404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381957113 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.3381957113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.3340153485
Short name T708
Test name
Test status
Simulation time 856768087 ps
CPU time 30.47 seconds
Started Oct 12 08:36:41 AM UTC 24
Finished Oct 12 08:37:13 AM UTC 24
Peak memory 240148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340153485 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.3340153485 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_error.1046070654
Short name T723
Test name
Test status
Simulation time 20454482431 ps
CPU time 179.35 seconds
Started Oct 12 08:36:42 AM UTC 24
Finished Oct 12 08:39:44 AM UTC 24
Peak memory 356972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046070654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1046070654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.3910522049
Short name T703
Test name
Test status
Simulation time 850726499 ps
CPU time 11.09 seconds
Started Oct 12 08:36:51 AM UTC 24
Finished Oct 12 08:37:03 AM UTC 24
Peak memory 230064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910522049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3910522049 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.1917730206
Short name T92
Test name
Test status
Simulation time 96343339 ps
CPU time 2.87 seconds
Started Oct 12 08:36:54 AM UTC 24
Finished Oct 12 08:36:58 AM UTC 24
Peak memory 236292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917730206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.1917730206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.949807018
Short name T778
Test name
Test status
Simulation time 238267947673 ps
CPU time 5339.89 seconds
Started Oct 12 08:35:47 AM UTC 24
Finished Oct 12 10:05:49 AM UTC 24
Peak memory 4770708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949807018 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.949807018 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.1054464705
Short name T704
Test name
Test status
Simulation time 1450014962 ps
CPU time 57.38 seconds
Started Oct 12 08:36:05 AM UTC 24
Finished Oct 12 08:37:04 AM UTC 24
Peak memory 268840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054464705 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1054464705 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload_invalid.2922868808
Short name T697
Test name
Test status
Simulation time 700233907 ps
CPU time 8.44 seconds
Started Oct 12 08:36:15 AM UTC 24
Finished Oct 12 08:36:25 AM UTC 24
Peak memory 237160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922868808 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload_invalid.2922868808 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.404942770
Short name T698
Test name
Test status
Simulation time 1224506547 ps
CPU time 36.96 seconds
Started Oct 12 08:35:47 AM UTC 24
Finished Oct 12 08:36:26 AM UTC 24
Peak memory 234480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404942770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.404942770 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.1069581113
Short name T767
Test name
Test status
Simulation time 20504115839 ps
CPU time 1745.15 seconds
Started Oct 12 08:36:59 AM UTC 24
Finished Oct 12 09:06:25 AM UTC 24
Peak memory 451640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069581113 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1069581113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.3046374311
Short name T717
Test name
Test status
Simulation time 19955014 ps
CPU time 1.27 seconds
Started Oct 12 08:38:11 AM UTC 24
Finished Oct 12 08:38:14 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046374311 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3046374311 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_app.89704059
Short name T710
Test name
Test status
Simulation time 509526423 ps
CPU time 4.39 seconds
Started Oct 12 08:37:23 AM UTC 24
Finished Oct 12 08:37:28 AM UTC 24
Peak memory 236536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89704059 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.89704059 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.1227426021
Short name T763
Test name
Test status
Simulation time 12252056044 ps
CPU time 1300.66 seconds
Started Oct 12 08:37:14 AM UTC 24
Finished Oct 12 08:59:09 AM UTC 24
Peak memory 256636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227426021 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1227426021 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.3258503693
Short name T734
Test name
Test status
Simulation time 91157491808 ps
CPU time 258.36 seconds
Started Oct 12 08:37:29 AM UTC 24
Finished Oct 12 08:41:51 AM UTC 24
Peak memory 309860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258503693 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3258503693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_error.3141077871
Short name T736
Test name
Test status
Simulation time 8980501672 ps
CPU time 291.11 seconds
Started Oct 12 08:37:54 AM UTC 24
Finished Oct 12 08:42:49 AM UTC 24
Peak memory 475748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141077871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3141077871 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.3616514782
Short name T714
Test name
Test status
Simulation time 3472575314 ps
CPU time 10.45 seconds
Started Oct 12 08:37:56 AM UTC 24
Finished Oct 12 08:38:08 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616514782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3616514782 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.142870895
Short name T715
Test name
Test status
Simulation time 142788344 ps
CPU time 2.14 seconds
Started Oct 12 08:38:07 AM UTC 24
Finished Oct 12 08:38:10 AM UTC 24
Peak memory 234316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142870895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.142870895 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.3273152369
Short name T771
Test name
Test status
Simulation time 19218164596 ps
CPU time 2422.47 seconds
Started Oct 12 08:37:07 AM UTC 24
Finished Oct 12 09:17:57 AM UTC 24
Peak memory 1376872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273152369 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.3273152369 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.1712300388
Short name T729
Test name
Test status
Simulation time 27666923354 ps
CPU time 247.23 seconds
Started Oct 12 08:37:07 AM UTC 24
Finished Oct 12 08:41:18 AM UTC 24
Peak memory 414308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712300388 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1712300388 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload_invalid.2058862421
Short name T709
Test name
Test status
Simulation time 216160546 ps
CPU time 10.37 seconds
Started Oct 12 08:37:11 AM UTC 24
Finished Oct 12 08:37:22 AM UTC 24
Peak memory 236936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058862421 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload_invalid.2058862421 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.1520973854
Short name T718
Test name
Test status
Simulation time 1527123286 ps
CPU time 78.04 seconds
Started Oct 12 08:37:05 AM UTC 24
Finished Oct 12 08:38:25 AM UTC 24
Peak memory 238116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520973854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1520973854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.2870048890
Short name T753
Test name
Test status
Simulation time 15507855745 ps
CPU time 651.97 seconds
Started Oct 12 08:38:08 AM UTC 24
Finished Oct 12 08:49:09 AM UTC 24
Peak memory 353392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870048890 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2870048890 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.1076554624
Short name T221
Test name
Test status
Simulation time 63111994 ps
CPU time 1.28 seconds
Started Oct 12 07:37:17 AM UTC 24
Finished Oct 12 07:37:19 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076554624 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1076554624 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_app.1071968512
Short name T243
Test name
Test status
Simulation time 12181724600 ps
CPU time 362.21 seconds
Started Oct 12 07:36:11 AM UTC 24
Finished Oct 12 07:42:18 AM UTC 24
Peak memory 330288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071968512 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.1071968512 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.2717199573
Short name T278
Test name
Test status
Simulation time 97156986855 ps
CPU time 647.24 seconds
Started Oct 12 07:36:14 AM UTC 24
Finished Oct 12 07:47:10 AM UTC 24
Peak memory 553652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717199573 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.2717199573 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.2243946291
Short name T375
Test name
Test status
Simulation time 262631719297 ps
CPU time 1323.86 seconds
Started Oct 12 07:36:01 AM UTC 24
Finished Oct 12 07:58:21 AM UTC 24
Peak memory 269100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243946291 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2243946291 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.1907901997
Short name T220
Test name
Test status
Simulation time 3401569693 ps
CPU time 26.61 seconds
Started Oct 12 07:36:46 AM UTC 24
Finished Oct 12 07:37:14 AM UTC 24
Peak memory 238052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907901997 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1907901997 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.533883717
Short name T219
Test name
Test status
Simulation time 128303984 ps
CPU time 1.77 seconds
Started Oct 12 07:36:50 AM UTC 24
Finished Oct 12 07:36:53 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533883717 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.533883717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.1154063111
Short name T224
Test name
Test status
Simulation time 15478458069 ps
CPU time 121.8 seconds
Started Oct 12 07:36:52 AM UTC 24
Finished Oct 12 07:38:57 AM UTC 24
Peak memory 238188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154063111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1154063111 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.696109438
Short name T223
Test name
Test status
Simulation time 2081121862 ps
CPU time 103.93 seconds
Started Oct 12 07:36:14 AM UTC 24
Finished Oct 12 07:38:00 AM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696109438 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.696109438 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_error.818433424
Short name T72
Test name
Test status
Simulation time 3990924125 ps
CPU time 125.87 seconds
Started Oct 12 07:36:34 AM UTC 24
Finished Oct 12 07:38:42 AM UTC 24
Peak memory 332392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818433424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.818433424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.3159174215
Short name T218
Test name
Test status
Simulation time 2278822525 ps
CPU time 8.32 seconds
Started Oct 12 07:36:40 AM UTC 24
Finished Oct 12 07:36:50 AM UTC 24
Peak memory 232288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159174215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3159174215 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.3810719353
Short name T45
Test name
Test status
Simulation time 48731727 ps
CPU time 2.45 seconds
Started Oct 12 07:36:55 AM UTC 24
Finished Oct 12 07:36:58 AM UTC 24
Peak memory 236500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810719353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.3810719353 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.230833643
Short name T731
Test name
Test status
Simulation time 430888922968 ps
CPU time 3909.58 seconds
Started Oct 12 07:35:42 AM UTC 24
Finished Oct 12 08:41:33 AM UTC 24
Peak memory 3936876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230833643 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.230833643 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.2249216786
Short name T98
Test name
Test status
Simulation time 7615096883 ps
CPU time 226.55 seconds
Started Oct 12 07:36:31 AM UTC 24
Finished Oct 12 07:40:21 AM UTC 24
Peak memory 385968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249216786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2249216786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.882628665
Short name T253
Test name
Test status
Simulation time 21223399363 ps
CPU time 484.72 seconds
Started Oct 12 07:35:52 AM UTC 24
Finished Oct 12 07:44:04 AM UTC 24
Peak memory 383656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882628665 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.882628665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload_invalid.2655948822
Short name T126
Test name
Test status
Simulation time 334677179 ps
CPU time 8.91 seconds
Started Oct 12 07:35:59 AM UTC 24
Finished Oct 12 07:36:09 AM UTC 24
Peak memory 234964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655948822 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload_invalid.2655948822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.3459148600
Short name T202
Test name
Test status
Simulation time 14131353268 ps
CPU time 34.09 seconds
Started Oct 12 07:35:37 AM UTC 24
Finished Oct 12 07:36:12 AM UTC 24
Peak memory 238164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459148600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3459148600 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.3778891387
Short name T307
Test name
Test status
Simulation time 80664876985 ps
CPU time 794.37 seconds
Started Oct 12 07:36:59 AM UTC 24
Finished Oct 12 07:50:24 AM UTC 24
Peak memory 384012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778891387 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3778891387 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.1716473894
Short name T228
Test name
Test status
Simulation time 20148790 ps
CPU time 1.35 seconds
Started Oct 12 07:39:35 AM UTC 24
Finished Oct 12 07:39:37 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716473894 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1716473894 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_app.3558494263
Short name T240
Test name
Test status
Simulation time 11870750301 ps
CPU time 264.48 seconds
Started Oct 12 07:37:33 AM UTC 24
Finished Oct 12 07:42:02 AM UTC 24
Peak memory 424756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558494263 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3558494263 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.1946486819
Short name T241
Test name
Test status
Simulation time 16125542891 ps
CPU time 266.66 seconds
Started Oct 12 07:37:39 AM UTC 24
Finished Oct 12 07:42:09 AM UTC 24
Peak memory 367216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946486819 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1946486819 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.1298211179
Short name T162
Test name
Test status
Simulation time 29364468734 ps
CPU time 700.7 seconds
Started Oct 12 07:37:27 AM UTC 24
Finished Oct 12 07:49:17 AM UTC 24
Peak memory 256808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298211179 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.1298211179 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.3471489957
Short name T229
Test name
Test status
Simulation time 6491572085 ps
CPU time 53.6 seconds
Started Oct 12 07:38:57 AM UTC 24
Finished Oct 12 07:39:53 AM UTC 24
Peak memory 248332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471489957 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3471489957 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.3242883658
Short name T226
Test name
Test status
Simulation time 27156664 ps
CPU time 1.54 seconds
Started Oct 12 07:39:03 AM UTC 24
Finished Oct 12 07:39:06 AM UTC 24
Peak memory 226752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242883658 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3242883658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.1168985948
Short name T230
Test name
Test status
Simulation time 5239909469 ps
CPU time 61.57 seconds
Started Oct 12 07:39:06 AM UTC 24
Finished Oct 12 07:40:10 AM UTC 24
Peak memory 236544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168985948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.1168985948 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.2087480920
Short name T77
Test name
Test status
Simulation time 38227105961 ps
CPU time 146.07 seconds
Started Oct 12 07:37:50 AM UTC 24
Finished Oct 12 07:40:18 AM UTC 24
Peak memory 328308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087480920 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.2087480920 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_error.579247573
Short name T171
Test name
Test status
Simulation time 9033981545 ps
CPU time 247.86 seconds
Started Oct 12 07:38:43 AM UTC 24
Finished Oct 12 07:42:55 AM UTC 24
Peak memory 336480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579247573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.579247573 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.2521148580
Short name T225
Test name
Test status
Simulation time 2069956370 ps
CPU time 16.28 seconds
Started Oct 12 07:38:48 AM UTC 24
Finished Oct 12 07:39:05 AM UTC 24
Peak memory 232092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521148580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2521148580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.789956309
Short name T69
Test name
Test status
Simulation time 155269309 ps
CPU time 2.16 seconds
Started Oct 12 07:39:06 AM UTC 24
Finished Oct 12 07:39:10 AM UTC 24
Peak memory 234448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789956309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.789956309 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.2740047883
Short name T198
Test name
Test status
Simulation time 25893262952 ps
CPU time 81.07 seconds
Started Oct 12 07:37:24 AM UTC 24
Finished Oct 12 07:38:47 AM UTC 24
Peak memory 285228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740047883 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.2740047883 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.3956613392
Short name T99
Test name
Test status
Simulation time 20978515454 ps
CPU time 277.31 seconds
Started Oct 12 07:38:01 AM UTC 24
Finished Oct 12 07:42:42 AM UTC 24
Peak memory 441304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956613392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3956613392 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.1664613260
Short name T249
Test name
Test status
Simulation time 4133994598 ps
CPU time 341.65 seconds
Started Oct 12 07:37:24 AM UTC 24
Finished Oct 12 07:43:11 AM UTC 24
Peak memory 346864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664613260 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1664613260 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload_invalid.2363449970
Short name T127
Test name
Test status
Simulation time 190814378 ps
CPU time 6.41 seconds
Started Oct 12 07:37:25 AM UTC 24
Finished Oct 12 07:37:33 AM UTC 24
Peak memory 236928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363449970 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload_invalid.2363449970 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.3814481120
Short name T222
Test name
Test status
Simulation time 974438562 ps
CPU time 27.34 seconds
Started Oct 12 07:37:20 AM UTC 24
Finished Oct 12 07:37:49 AM UTC 24
Peak memory 236536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814481120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.3814481120 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.240397735
Short name T514
Test name
Test status
Simulation time 82090152538 ps
CPU time 2163.3 seconds
Started Oct 12 07:39:11 AM UTC 24
Finished Oct 12 08:15:37 AM UTC 24
Peak memory 1549464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240397735 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.240397735 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all_with_rand_reset.3102522938
Short name T94
Test name
Test status
Simulation time 20649198664 ps
CPU time 247.75 seconds
Started Oct 12 07:39:15 AM UTC 24
Finished Oct 12 07:43:26 AM UTC 24
Peak memory 297556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3102522938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_r
and_reset.3102522938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.2290788135
Short name T236
Test name
Test status
Simulation time 14207960 ps
CPU time 1.21 seconds
Started Oct 12 07:41:35 AM UTC 24
Finished Oct 12 07:41:37 AM UTC 24
Peak memory 228484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290788135 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.2290788135 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_app.3985065179
Short name T274
Test name
Test status
Simulation time 17582879443 ps
CPU time 414.94 seconds
Started Oct 12 07:39:53 AM UTC 24
Finished Oct 12 07:46:54 AM UTC 24
Peak memory 533040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985065179 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3985065179 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.2533461701
Short name T231
Test name
Test status
Simulation time 2422574771 ps
CPU time 59.41 seconds
Started Oct 12 07:39:53 AM UTC 24
Finished Oct 12 07:40:54 AM UTC 24
Peak memory 254572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533461701 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2533461701 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.1487441837
Short name T346
Test name
Test status
Simulation time 12842165669 ps
CPU time 943.52 seconds
Started Oct 12 07:39:47 AM UTC 24
Finished Oct 12 07:55:42 AM UTC 24
Peak memory 250604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487441837 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.1487441837 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2900535814
Short name T237
Test name
Test status
Simulation time 1043435679 ps
CPU time 38.95 seconds
Started Oct 12 07:40:58 AM UTC 24
Finished Oct 12 07:41:39 AM UTC 24
Peak memory 237932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900535814 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2900535814 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.2788173468
Short name T234
Test name
Test status
Simulation time 889608145 ps
CPU time 14.28 seconds
Started Oct 12 07:41:07 AM UTC 24
Finished Oct 12 07:41:22 AM UTC 24
Peak memory 237744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788173468 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2788173468 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.885563224
Short name T238
Test name
Test status
Simulation time 2883262693 ps
CPU time 33.58 seconds
Started Oct 12 07:41:11 AM UTC 24
Finished Oct 12 07:41:46 AM UTC 24
Peak memory 238188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885563224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.885563224 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.3974297907
Short name T271
Test name
Test status
Simulation time 21063390470 ps
CPU time 363.59 seconds
Started Oct 12 07:40:10 AM UTC 24
Finished Oct 12 07:46:20 AM UTC 24
Peak memory 420664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974297907 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3974297907 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.241762337
Short name T233
Test name
Test status
Simulation time 2623693072 ps
CPU time 9.2 seconds
Started Oct 12 07:40:56 AM UTC 24
Finished Oct 12 07:41:06 AM UTC 24
Peak memory 230072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241762337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.241762337 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.2840044285
Short name T68
Test name
Test status
Simulation time 98560954 ps
CPU time 1.99 seconds
Started Oct 12 07:41:13 AM UTC 24
Finished Oct 12 07:41:16 AM UTC 24
Peak memory 235900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840044285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.2840044285 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.2210655553
Short name T280
Test name
Test status
Simulation time 5398365493 ps
CPU time 408.33 seconds
Started Oct 12 07:40:20 AM UTC 24
Finished Oct 12 07:47:13 AM UTC 24
Peak memory 353336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210655553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2210655553 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.22133014
Short name T247
Test name
Test status
Simulation time 7899622097 ps
CPU time 178.02 seconds
Started Oct 12 07:39:39 AM UTC 24
Finished Oct 12 07:42:40 AM UTC 24
Peak memory 291432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22133014 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.22133014 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload_invalid.3247662438
Short name T128
Test name
Test status
Simulation time 722196810 ps
CPU time 9.22 seconds
Started Oct 12 07:39:42 AM UTC 24
Finished Oct 12 07:39:52 AM UTC 24
Peak memory 236932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247662438 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload_invalid.3247662438 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.971965854
Short name T232
Test name
Test status
Simulation time 102078827405 ps
CPU time 78.46 seconds
Started Oct 12 07:39:37 AM UTC 24
Finished Oct 12 07:40:57 AM UTC 24
Peak memory 240280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971965854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.971965854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.2533508412
Short name T466
Test name
Test status
Simulation time 50340045765 ps
CPU time 1693.33 seconds
Started Oct 12 07:41:17 AM UTC 24
Finished Oct 12 08:09:49 AM UTC 24
Peak memory 1090584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533508412 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2533508412 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.3317666519
Short name T248
Test name
Test status
Simulation time 44516275 ps
CPU time 1.27 seconds
Started Oct 12 07:42:56 AM UTC 24
Finished Oct 12 07:42:58 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317666519 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.3317666519 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_app.2844723815
Short name T250
Test name
Test status
Simulation time 3619162835 ps
CPU time 79.35 seconds
Started Oct 12 07:41:55 AM UTC 24
Finished Oct 12 07:43:18 AM UTC 24
Peak memory 293432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844723815 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2844723815 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.3762842254
Short name T273
Test name
Test status
Simulation time 24547062752 ps
CPU time 280.86 seconds
Started Oct 12 07:41:58 AM UTC 24
Finished Oct 12 07:46:43 AM UTC 24
Peak memory 305716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762842254 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.3762842254 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.3603799387
Short name T477
Test name
Test status
Simulation time 300728408085 ps
CPU time 1724.46 seconds
Started Oct 12 07:41:54 AM UTC 24
Finished Oct 12 08:11:00 AM UTC 24
Peak memory 260656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603799387 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3603799387 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.1565400560
Short name T245
Test name
Test status
Simulation time 48916805 ps
CPU time 1.82 seconds
Started Oct 12 07:42:30 AM UTC 24
Finished Oct 12 07:42:33 AM UTC 24
Peak memory 230020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565400560 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.1565400560 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.1807125329
Short name T246
Test name
Test status
Simulation time 76604659 ps
CPU time 1.57 seconds
Started Oct 12 07:42:34 AM UTC 24
Finished Oct 12 07:42:37 AM UTC 24
Peak memory 226752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807125329 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1807125329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.66167225
Short name T252
Test name
Test status
Simulation time 5102572396 ps
CPU time 59.08 seconds
Started Oct 12 07:42:37 AM UTC 24
Finished Oct 12 07:43:38 AM UTC 24
Peak memory 236740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66167225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.66167225 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.3385776844
Short name T82
Test name
Test status
Simulation time 33161990345 ps
CPU time 138.91 seconds
Started Oct 12 07:42:03 AM UTC 24
Finished Oct 12 07:44:24 AM UTC 24
Peak memory 332392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385776844 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.3385776844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_error.3643337896
Short name T21
Test name
Test status
Simulation time 4837424010 ps
CPU time 236.75 seconds
Started Oct 12 07:42:14 AM UTC 24
Finished Oct 12 07:46:15 AM UTC 24
Peak memory 303976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643337896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3643337896 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.665267987
Short name T244
Test name
Test status
Simulation time 665903309 ps
CPU time 9.42 seconds
Started Oct 12 07:42:19 AM UTC 24
Finished Oct 12 07:42:30 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665267987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.665267987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.1481862236
Short name T70
Test name
Test status
Simulation time 97296456 ps
CPU time 1.81 seconds
Started Oct 12 07:42:41 AM UTC 24
Finished Oct 12 07:42:44 AM UTC 24
Peak memory 231876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481862236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1481862236 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.3055619002
Short name T302
Test name
Test status
Simulation time 67281189864 ps
CPU time 455.48 seconds
Started Oct 12 07:41:39 AM UTC 24
Finished Oct 12 07:49:21 AM UTC 24
Peak memory 743964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055619002 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.3055619002 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.2991707128
Short name T263
Test name
Test status
Simulation time 3268112802 ps
CPU time 179.59 seconds
Started Oct 12 07:42:11 AM UTC 24
Finished Oct 12 07:45:14 AM UTC 24
Peak memory 287720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991707128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2991707128 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.2308687522
Short name T289
Test name
Test status
Simulation time 14226348706 ps
CPU time 349.02 seconds
Started Oct 12 07:41:47 AM UTC 24
Finished Oct 12 07:47:41 AM UTC 24
Peak memory 330288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308687522 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2308687522 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload_invalid.2547697855
Short name T129
Test name
Test status
Simulation time 139309422 ps
CPU time 4.61 seconds
Started Oct 12 07:41:49 AM UTC 24
Finished Oct 12 07:41:55 AM UTC 24
Peak memory 236880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547697855 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload_invalid.2547697855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.2959084818
Short name T242
Test name
Test status
Simulation time 1021313672 ps
CPU time 33.81 seconds
Started Oct 12 07:41:38 AM UTC 24
Finished Oct 12 07:42:13 AM UTC 24
Peak memory 238056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959084818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2959084818 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.4051659755
Short name T334
Test name
Test status
Simulation time 133002863652 ps
CPU time 704.05 seconds
Started Oct 12 07:42:43 AM UTC 24
Finished Oct 12 07:54:36 AM UTC 24
Peak memory 301680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051659755 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.4051659755 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all_with_rand_reset.1599088820
Short name T143
Test name
Test status
Simulation time 70704780166 ps
CPU time 247.21 seconds
Started Oct 12 07:42:45 AM UTC 24
Finished Oct 12 07:46:56 AM UTC 24
Peak memory 314400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1599088820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_r
and_reset.1599088820 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.3085091641
Short name T260
Test name
Test status
Simulation time 25522367 ps
CPU time 1.33 seconds
Started Oct 12 07:44:29 AM UTC 24
Finished Oct 12 07:44:32 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085091641 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.3085091641 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_app.1977973309
Short name T303
Test name
Test status
Simulation time 24394921343 ps
CPU time 357.17 seconds
Started Oct 12 07:43:30 AM UTC 24
Finished Oct 12 07:49:32 AM UTC 24
Peak memory 461396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977973309 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1977973309 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.2639416518
Short name T264
Test name
Test status
Simulation time 1744513238 ps
CPU time 105.15 seconds
Started Oct 12 07:43:36 AM UTC 24
Finished Oct 12 07:45:24 AM UTC 24
Peak memory 256496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639416518 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2639416518 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.2795023229
Short name T157
Test name
Test status
Simulation time 1893647650 ps
CPU time 43.33 seconds
Started Oct 12 07:43:27 AM UTC 24
Finished Oct 12 07:44:12 AM UTC 24
Peak memory 234484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795023229 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.2795023229 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.4092438865
Short name T255
Test name
Test status
Simulation time 71627113 ps
CPU time 1.56 seconds
Started Oct 12 07:44:13 AM UTC 24
Finished Oct 12 07:44:15 AM UTC 24
Peak memory 230080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092438865 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.4092438865 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.918855755
Short name T256
Test name
Test status
Simulation time 24177136 ps
CPU time 1.27 seconds
Started Oct 12 07:44:16 AM UTC 24
Finished Oct 12 07:44:18 AM UTC 24
Peak memory 226752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918855755 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.918855755 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2671691480
Short name T259
Test name
Test status
Simulation time 428173144 ps
CPU time 8.42 seconds
Started Oct 12 07:44:19 AM UTC 24
Finished Oct 12 07:44:29 AM UTC 24
Peak memory 232420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671691480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2671691480 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.296414108
Short name T78
Test name
Test status
Simulation time 1547873328 ps
CPU time 74.07 seconds
Started Oct 12 07:43:38 AM UTC 24
Finished Oct 12 07:44:54 AM UTC 24
Peak memory 252396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296414108 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.296414108 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_error.2492752660
Short name T254
Test name
Test status
Simulation time 156919282 ps
CPU time 3.64 seconds
Started Oct 12 07:44:05 AM UTC 24
Finished Oct 12 07:44:09 AM UTC 24
Peak memory 236464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492752660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2492752660 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.561016687
Short name T257
Test name
Test status
Simulation time 2202656243 ps
CPU time 7.37 seconds
Started Oct 12 07:44:10 AM UTC 24
Finished Oct 12 07:44:18 AM UTC 24
Peak memory 232252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561016687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.561016687 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.279721340
Short name T258
Test name
Test status
Simulation time 1050623811 ps
CPU time 8.35 seconds
Started Oct 12 07:44:19 AM UTC 24
Finished Oct 12 07:44:29 AM UTC 24
Peak memory 246792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279721340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.279721340 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.3162652204
Short name T446
Test name
Test status
Simulation time 29341591798 ps
CPU time 1482.49 seconds
Started Oct 12 07:43:04 AM UTC 24
Finished Oct 12 08:08:02 AM UTC 24
Peak memory 1043048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162652204 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.3162652204 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.1052165963
Short name T320
Test name
Test status
Simulation time 74639783807 ps
CPU time 466.91 seconds
Started Oct 12 07:44:02 AM UTC 24
Finished Oct 12 07:51:55 AM UTC 24
Peak memory 586676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052165963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1052165963 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.2643598827
Short name T270
Test name
Test status
Simulation time 19838567889 ps
CPU time 172.04 seconds
Started Oct 12 07:43:12 AM UTC 24
Finished Oct 12 07:46:07 AM UTC 24
Peak memory 338668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643598827 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2643598827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload_invalid.2856329868
Short name T251
Test name
Test status
Simulation time 225616721 ps
CPU time 10.53 seconds
Started Oct 12 07:43:18 AM UTC 24
Finished Oct 12 07:43:30 AM UTC 24
Peak memory 236940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856329868 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload_invalid.2856329868 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.713176432
Short name T262
Test name
Test status
Simulation time 6479469172 ps
CPU time 126.17 seconds
Started Oct 12 07:42:59 AM UTC 24
Finished Oct 12 07:45:07 AM UTC 24
Peak memory 240284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713176432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.713176432 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.4186245682
Short name T100
Test name
Test status
Simulation time 612860129 ps
CPU time 13.36 seconds
Started Oct 12 07:44:19 AM UTC 24
Finished Oct 12 07:44:34 AM UTC 24
Peak memory 238508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186245682 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.4186245682 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all_with_rand_reset.297476395
Short name T83
Test name
Test status
Simulation time 12115885307 ps
CPU time 125.55 seconds
Started Oct 12 07:44:25 AM UTC 24
Finished Oct 12 07:46:33 AM UTC 24
Peak memory 283764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_11
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=297476395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_ra
nd_reset.297476395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_11/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest
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