Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601868762	60960959	0	0
DataKnown_AKnownEnable	601868762	601668801	0	0
DepthKnown_A	601868762	601668801	0	0
RvalidKnown_A	601868762	601668801	0	0
WreadyKnown_A	601868762	601668801	0	0
gen_passthru_fifo.paramCheckPass	934	934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	60960959	0	0
T1	7856	555	0	0
T2	6537	417	0	0
T3	1894	179	0	0
T4	165802	1179	0	0
T7	23351	610	0	0
T8	138958	1884	0	0
T9	3561	84	0	0
T11	4529	579	0	0
T52	3684	165	0	0
T53	1740	19	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	601668801	0	0
T1	7856	7786	0	0
T2	6537	6473	0	0
T3	1894	1841	0	0
T4	165802	165705	0	0
T7	23351	23261	0	0
T8	138958	138876	0	0
T9	3561	3424	0	0
T11	4529	4477	0	0
T52	3684	3618	0	0
T53	1740	1652	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	601668801	0	0
T1	7856	7786	0	0
T2	6537	6473	0	0
T3	1894	1841	0	0
T4	165802	165705	0	0
T7	23351	23261	0	0
T8	138958	138876	0	0
T9	3561	3424	0	0
T11	4529	4477	0	0
T52	3684	3618	0	0
T53	1740	1652	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	601668801	0	0
T1	7856	7786	0	0
T2	6537	6473	0	0
T3	1894	1841	0	0
T4	165802	165705	0	0
T7	23351	23261	0	0
T8	138958	138876	0	0
T9	3561	3424	0	0
T11	4529	4477	0	0
T52	3684	3618	0	0
T53	1740	1652	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	601668801	0	0
T1	7856	7786	0	0
T2	6537	6473	0	0
T3	1894	1841	0	0
T4	165802	165705	0	0
T7	23351	23261	0	0
T8	138958	138876	0	0
T9	3561	3424	0	0
T11	4529	4477	0	0
T52	3684	3618	0	0
T53	1740	1652	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T11	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601868762	105238269	0	0
DataKnown_AKnownEnable	601868762	601668801	0	0
DepthKnown_A	601868762	601668801	0	0
RvalidKnown_A	601868762	601668801	0	0
WreadyKnown_A	601868762	601668801	0	0
gen_passthru_fifo.paramCheckPass	934	934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	105238269	0	0
T1	7856	552	0	0
T2	6537	417	0	0
T3	1894	179	0	0
T4	165802	1179	0	0
T7	23351	2656	0	0
T8	138958	1884	0	0
T9	3561	84	0	0
T11	4529	579	0	0
T52	3684	747	0	0
T53	1740	67	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	601668801	0	0
T1	7856	7786	0	0
T2	6537	6473	0	0
T3	1894	1841	0	0
T4	165802	165705	0	0
T7	23351	23261	0	0
T8	138958	138876	0	0
T9	3561	3424	0	0
T11	4529	4477	0	0
T52	3684	3618	0	0
T53	1740	1652	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	601668801	0	0
T1	7856	7786	0	0
T2	6537	6473	0	0
T3	1894	1841	0	0
T4	165802	165705	0	0
T7	23351	23261	0	0
T8	138958	138876	0	0
T9	3561	3424	0	0
T11	4529	4477	0	0
T52	3684	3618	0	0
T53	1740	1652	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	601668801	0	0
T1	7856	7786	0	0
T2	6537	6473	0	0
T3	1894	1841	0	0
T4	165802	165705	0	0
T7	23351	23261	0	0
T8	138958	138876	0	0
T9	3561	3424	0	0
T11	4529	4477	0	0
T52	3684	3618	0	0
T53	1740	1652	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601868762	601668801	0	0
T1	7856	7786	0	0
T2	6537	6473	0	0
T3	1894	1841	0	0
T4	165802	165705	0	0
T7	23351	23261	0	0
T8	138958	138876	0	0
T9	3561	3424	0	0
T11	4529	4477	0	0
T52	3684	3618	0	0
T53	1740	1652	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	934	934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T11	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0