Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177467 |
1 |
|
|
T4 |
1006 |
|
T5 |
357 |
|
T13 |
599 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
94018 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
61354 |
1 |
|
|
T4 |
990 |
|
T5 |
351 |
|
T13 |
591 |
seven_bytes |
3235 |
1 |
|
|
T14 |
16 |
|
T15 |
24 |
|
T37 |
27 |
six_bytes |
3177 |
1 |
|
|
T14 |
21 |
|
T15 |
32 |
|
T37 |
22 |
five_bytes |
3121 |
1 |
|
|
T14 |
19 |
|
T15 |
19 |
|
T37 |
32 |
four_bytes |
3247 |
1 |
|
|
T14 |
17 |
|
T15 |
32 |
|
T37 |
31 |
three_bytes |
3098 |
1 |
|
|
T14 |
17 |
|
T15 |
21 |
|
T37 |
33 |
two_bytes |
3147 |
1 |
|
|
T14 |
20 |
|
T15 |
19 |
|
T37 |
27 |
one_byte |
3070 |
1 |
|
|
T14 |
17 |
|
T15 |
24 |
|
T37 |
26 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
174081 |
1 |
|
|
T4 |
974 |
|
T5 |
345 |
|
T13 |
583 |
auto[1] |
3386 |
1 |
|
|
T4 |
32 |
|
T5 |
12 |
|
T13 |
16 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177467 |
1 |
|
|
T4 |
1006 |
|
T5 |
357 |
|
T13 |
599 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
177456 |
1 |
|
|
T4 |
1006 |
|
T5 |
357 |
|
T13 |
599 |
auto[1] |
11 |
1 |
|
|
T6 |
2 |
|
T160 |
1 |
|
T161 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1175 |
1 |
|
|
T4 |
16 |
|
T5 |
6 |
|
T13 |
8 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3386 |
1 |
|
|
T4 |
32 |
|
T5 |
12 |
|
T13 |
16 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for app_err
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175766 |
1 |
|
|
T4 |
677 |
|
T5 |
754 |
|
T13 |
524 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
91011 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
62989 |
1 |
|
|
T4 |
666 |
|
T5 |
743 |
|
T13 |
518 |
seven_bytes |
3153 |
1 |
|
|
T14 |
24 |
|
T15 |
25 |
|
T37 |
19 |
six_bytes |
3113 |
1 |
|
|
T14 |
16 |
|
T15 |
13 |
|
T37 |
22 |
five_bytes |
3063 |
1 |
|
|
T14 |
20 |
|
T15 |
14 |
|
T37 |
17 |
four_bytes |
3128 |
1 |
|
|
T14 |
15 |
|
T15 |
28 |
|
T37 |
23 |
three_bytes |
3078 |
1 |
|
|
T14 |
12 |
|
T15 |
16 |
|
T37 |
16 |
two_bytes |
3106 |
1 |
|
|
T14 |
18 |
|
T15 |
23 |
|
T37 |
23 |
one_byte |
3125 |
1 |
|
|
T14 |
17 |
|
T15 |
16 |
|
T37 |
21 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
172436 |
1 |
|
|
T4 |
655 |
|
T5 |
732 |
|
T13 |
512 |
auto[1] |
3330 |
1 |
|
|
T4 |
22 |
|
T5 |
22 |
|
T13 |
12 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175766 |
1 |
|
|
T4 |
677 |
|
T5 |
754 |
|
T13 |
524 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
175755 |
1 |
|
|
T4 |
677 |
|
T5 |
754 |
|
T13 |
524 |
auto[1] |
11 |
1 |
|
|
T162 |
1 |
|
T85 |
1 |
|
T163 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
1159 |
1 |
|
|
T4 |
11 |
|
T5 |
11 |
|
T13 |
6 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
3330 |
1 |
|
|
T4 |
22 |
|
T5 |
22 |
|
T13 |
12 |
Summary for Variable app_err
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for app_err
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342414 |
1 |
|
|
T1 |
18 |
|
T9 |
12 |
|
T7 |
30 |
auto[1] |
573 |
1 |
|
|
T7 |
3 |
|
T4 |
24 |
|
T17 |
1 |
Summary for Variable data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
8 |
0 |
8 |
100.00 |
User Defined Bins for data_strb
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
179035 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full_data_beat |
121709 |
1 |
|
|
T1 |
12 |
|
T9 |
12 |
|
T7 |
22 |
seven_bytes |
6031 |
1 |
|
|
T14 |
73 |
|
T15 |
60 |
|
T37 |
71 |
six_bytes |
6168 |
1 |
|
|
T14 |
57 |
|
T15 |
73 |
|
T37 |
66 |
five_bytes |
6097 |
1 |
|
|
T14 |
59 |
|
T15 |
55 |
|
T37 |
77 |
four_bytes |
6033 |
1 |
|
|
T14 |
67 |
|
T15 |
59 |
|
T37 |
70 |
three_bytes |
6093 |
1 |
|
|
T14 |
60 |
|
T15 |
65 |
|
T37 |
67 |
two_bytes |
5965 |
1 |
|
|
T14 |
59 |
|
T15 |
62 |
|
T37 |
66 |
one_byte |
5856 |
1 |
|
|
T14 |
52 |
|
T15 |
68 |
|
T37 |
68 |
Summary for Variable done
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for done
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335720 |
1 |
|
|
T1 |
6 |
|
T9 |
12 |
|
T7 |
11 |
auto[1] |
7267 |
1 |
|
|
T1 |
12 |
|
T7 |
22 |
|
T4 |
48 |
Summary for Variable in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for in_keccak_rounds
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342987 |
1 |
|
|
T1 |
18 |
|
T9 |
12 |
|
T7 |
33 |
Summary for Variable single_data_beat
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for single_data_beat
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342877 |
1 |
|
|
T1 |
16 |
|
T9 |
12 |
|
T7 |
30 |
auto[1] |
110 |
1 |
|
|
T1 |
2 |
|
T7 |
3 |
|
T4 |
1 |
Summary for Cross partial_data_on_last_beat
Samples crossed: done data_strb
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for partial_data_on_last_beat
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
2607 |
1 |
|
|
T1 |
6 |
|
T7 |
11 |
|
T4 |
24 |
Summary for Cross done_in_keccak_rounds
Samples crossed: done in_keccak_rounds
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for done_in_keccak_rounds
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
7267 |
1 |
|
|
T1 |
12 |
|
T7 |
22 |
|
T4 |
48 |