Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	50015665	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

47946749

1

T1

750

T2

298

T3

104

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54745197	1			T1	946		T2	217		T3	57
values[0x0]	20932600	1			T1	96		T2	162		T3	70
values[0x1]	22284617	1			T1	87		T2	161		T3	52

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38440765	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

59521649

1

T1

882

T2

345

T3

120

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	315139	1			T2	1		T7	5		T4	16
valid_sources[0x01]	311270	1			T2	3		T9	2		T7	7
valid_sources[0x02]	311645	1			T2	4		T9	1		T53	1
valid_sources[0x03]	311164	1			T2	2		T52	1		T7	11
valid_sources[0x04]	310216	1			T2	2		T52	1		T9	1
valid_sources[0x05]	308459	1			T2	3		T9	1		T53	2
valid_sources[0x06]	311242	1			T2	1		T7	8		T4	34
valid_sources[0x07]	453689	1			T2	2		T52	1		T7	8
valid_sources[0x08]	308435	1			T7	8		T4	15		T16	17
valid_sources[0x09]	314654	1			T3	37		T9	3		T7	6
valid_sources[0x0a]	310782	1			T2	1		T52	1		T9	1
valid_sources[0x0b]	311851	1			T2	5		T9	1		T7	7
valid_sources[0x0c]	312429	1			T2	2		T9	2		T7	7
valid_sources[0x0d]	312491	1			T2	3		T52	2		T7	6
valid_sources[0x0e]	474215	1			T2	2		T52	1		T7	5
valid_sources[0x0f]	310282	1			T2	1		T52	1		T9	1
valid_sources[0x10]	308759	1			T9	3		T7	4		T4	14
valid_sources[0x11]	1118843	1			T2	2		T7	2		T4	29
valid_sources[0x12]	323598	1			T2	4		T52	1		T7	4
valid_sources[0x13]	307023	1			T2	2		T7	6		T4	25
valid_sources[0x14]	311205	1			T2	3		T52	1		T9	2
valid_sources[0x15]	314735	1			T2	1		T52	3		T7	6
valid_sources[0x16]	310207	1			T2	5		T52	1		T9	1
valid_sources[0x17]	311355	1			T2	2		T52	4		T9	3
valid_sources[0x18]	409708	1			T2	3		T9	2		T7	4
valid_sources[0x19]	313723	1			T2	3		T52	1		T9	1
valid_sources[0x1a]	515793	1			T2	2		T52	1		T9	1
valid_sources[0x1b]	419030	1			T52	2		T7	7		T4	14
valid_sources[0x1c]	1123316	1			T2	2		T52	1		T7	11
valid_sources[0x1d]	309530	1			T9	2		T7	6		T4	20
valid_sources[0x1e]	1319846	1			T52	1		T7	11		T4	4
valid_sources[0x1f]	311015	1			T2	3		T7	6		T4	9
valid_sources[0x20]	310586	1			T2	4		T9	1		T7	8
valid_sources[0x21]	313891	1			T2	1		T7	4		T4	17
valid_sources[0x22]	313120	1			T2	3		T52	3		T9	1
valid_sources[0x23]	450774	1			T7	10		T4	20		T16	18
valid_sources[0x24]	307693	1			T2	1		T52	2		T9	1
valid_sources[0x25]	309816	1			T2	1		T9	1		T53	2
valid_sources[0x26]	308599	1			T2	2		T3	9		T52	1
valid_sources[0x27]	310612	1			T7	16		T4	21		T16	14
valid_sources[0x28]	311154	1			T2	4		T52	1		T7	9
valid_sources[0x29]	311012	1			T2	1		T52	2		T7	2
valid_sources[0x2a]	367871	1			T2	1		T52	1		T9	1
valid_sources[0x2b]	312362	1			T2	3		T7	10		T4	49
valid_sources[0x2c]	359684	1			T2	3		T9	1		T7	5
valid_sources[0x2d]	313776	1			T2	3		T7	4		T4	5
valid_sources[0x2e]	311361	1			T2	5		T52	1		T9	1
valid_sources[0x2f]	315249	1			T2	1		T7	8		T4	15
valid_sources[0x30]	309949	1			T2	1		T52	1		T9	1
valid_sources[0x31]	308905	1			T2	4		T52	1		T9	1
valid_sources[0x32]	321058	1			T2	2		T52	1		T9	1
valid_sources[0x33]	317201	1			T2	2		T7	5		T4	20
valid_sources[0x34]	310994	1			T2	3		T7	8		T4	14
valid_sources[0x35]	307758	1			T2	1		T9	1		T7	8
valid_sources[0x36]	313058	1			T9	1		T53	1		T7	8
valid_sources[0x37]	343606	1			T2	2		T52	1		T9	1
valid_sources[0x38]	334068	1			T2	3		T52	1		T7	4
valid_sources[0x39]	424010	1			T2	4		T7	4		T4	6
valid_sources[0x3a]	307896	1			T2	1		T7	7		T4	13
valid_sources[0x3b]	471890	1			T2	3		T9	1		T7	5
valid_sources[0x3c]	437504	1			T2	2		T52	1		T7	9
valid_sources[0x3d]	312566	1			T2	3		T7	5		T4	29
valid_sources[0x3e]	835167	1			T2	2		T52	1		T9	1
valid_sources[0x3f]	411747	1			T2	2		T52	2		T7	7
valid_sources[0x40]	503500	1			T2	1		T52	1		T9	1
valid_sources[0x41]	410576	1			T1	59		T52	1		T9	2
valid_sources[0x42]	313467	1			T2	1		T52	1		T7	6
valid_sources[0x43]	309571	1			T2	3		T7	12		T4	9
valid_sources[0x44]	313067	1			T2	2		T52	1		T7	5
valid_sources[0x45]	313029	1			T2	1		T7	14		T4	6
valid_sources[0x46]	307036	1			T2	2		T52	1		T9	2
valid_sources[0x47]	324357	1			T2	1		T52	1		T9	1
valid_sources[0x48]	670012	1			T2	4		T52	2		T7	8
valid_sources[0x49]	335133	1			T2	1		T9	1		T53	1
valid_sources[0x4a]	335769	1			T2	2		T52	1		T7	8
valid_sources[0x4b]	623419	1			T1	1070		T2	3		T9	4
valid_sources[0x4c]	340655	1			T2	1		T52	1		T9	3
valid_sources[0x4d]	308380	1			T2	1		T52	2		T7	3
valid_sources[0x4e]	1324832	1			T2	2		T9	3		T7	11
valid_sources[0x4f]	1534639	1			T2	3		T9	1		T7	6
valid_sources[0x50]	309196	1			T2	1		T52	1		T9	1
valid_sources[0x51]	309215	1			T2	3		T52	1		T9	1
valid_sources[0x52]	310734	1			T2	4		T7	4		T4	6
valid_sources[0x53]	309985	1			T2	3		T7	3		T4	17
valid_sources[0x54]	324531	1			T2	2		T52	3		T7	4
valid_sources[0x55]	310083	1			T2	4		T9	1		T7	8
valid_sources[0x56]	311013	1			T2	3		T7	13		T4	9
valid_sources[0x57]	309309	1			T2	3		T52	1		T7	5
valid_sources[0x58]	306224	1			T2	2		T52	1		T7	9
valid_sources[0x59]	315212	1			T2	1		T7	5		T4	8
valid_sources[0x5a]	311084	1			T2	4		T52	2		T7	12
valid_sources[0x5b]	310886	1			T2	1		T52	1		T9	2
valid_sources[0x5c]	308236	1			T52	1		T9	2		T7	4
valid_sources[0x5d]	310258	1			T2	5		T7	6		T4	17
valid_sources[0x5e]	311330	1			T2	5		T7	5		T4	12
valid_sources[0x5f]	415689	1			T52	1		T9	1		T7	2
valid_sources[0x60]	310673	1			T2	4		T11	782		T7	5
valid_sources[0x61]	311905	1			T2	1		T9	4		T7	9
valid_sources[0x62]	455576	1			T2	2		T9	1		T53	1
valid_sources[0x63]	312495	1			T2	5		T7	9		T4	26
valid_sources[0x64]	312384	1			T2	3		T52	2		T9	2
valid_sources[0x65]	309660	1			T2	2		T9	1		T7	9
valid_sources[0x66]	462245	1			T2	1		T9	2		T7	13
valid_sources[0x67]	336387	1			T52	1		T7	7		T8	1884
valid_sources[0x68]	390106	1			T52	1		T9	1		T7	5
valid_sources[0x69]	309724	1			T2	1		T9	1		T7	7
valid_sources[0x6a]	437894	1			T2	1		T7	10		T4	8
valid_sources[0x6b]	340538	1			T2	3		T52	1		T7	8
valid_sources[0x6c]	310171	1			T2	2		T9	1		T7	5
valid_sources[0x6d]	307343	1			T2	3		T52	1		T9	1
valid_sources[0x6e]	312319	1			T2	2		T9	1		T7	7
valid_sources[0x6f]	311092	1			T2	2		T52	1		T9	3
valid_sources[0x70]	425588	1			T2	3		T52	1		T7	5
valid_sources[0x71]	309749	1			T52	2		T9	1		T7	6
valid_sources[0x72]	311341	1			T2	2		T9	4		T7	4
valid_sources[0x73]	366679	1			T2	3		T52	1		T9	1
valid_sources[0x74]	311255	1			T2	2		T7	6		T4	16
valid_sources[0x75]	311122	1			T2	4		T7	9		T4	20
valid_sources[0x76]	308634	1			T2	3		T52	1		T7	6
valid_sources[0x77]	310335	1			T2	1		T7	5		T4	17
valid_sources[0x78]	309071	1			T2	5		T9	5		T7	12
valid_sources[0x79]	1112604	1			T2	1		T7	6		T4	18
valid_sources[0x7a]	308118	1			T2	2		T52	1		T7	8
valid_sources[0x7b]	311671	1			T2	5		T52	1		T7	7
valid_sources[0x7c]	309665	1			T52	1		T7	8		T4	24
valid_sources[0x7d]	323969	1			T2	1		T52	1		T7	9
valid_sources[0x7e]	311903	1			T52	2		T7	9		T4	3
valid_sources[0x7f]	383622	1			T2	4		T9	2		T7	3
valid_sources[0x80]	308559	1			T2	2		T3	31		T7	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

21318824

1

T1

584

T2

90

T3

27

values[0x0]

all_enables

biggest_size

14007097

1

T1

88

T2

110

T3

48

values[0x1]

all_enables

biggest_size

12620828

1

T1

78

T2

98

T3

29