Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	261387087	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

185640095

1

T1

911706

T2

66079

T3

175816

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	231254648	1			T1	117989		T2	73842		T3	228173
values[0x0]	103643169	1			T1	550364		T2	17339		T3	106885
values[0x1]	112129365	1			T1	595251		T2	18462		T3	115560

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203153002	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

243874180

1

T1

122187

T2

76180

T3

235448

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3787509	1			T1	9024		T2	358		T7	26
valid_sources[0x01]	2671210	1			T1	9087		T2	533		T7	25
valid_sources[0x02]	1504598	1			T1	8859		T2	448		T7	34
valid_sources[0x03]	1314451	1			T1	8977		T2	443		T7	21
valid_sources[0x04]	3698463	1			T1	9225		T2	432		T7	27
valid_sources[0x05]	1302974	1			T1	9247		T2	454		T7	31
valid_sources[0x06]	1408529	1			T1	9218		T2	451		T7	24
valid_sources[0x07]	1366061	1			T1	9170		T2	382		T7	31
valid_sources[0x08]	1285893	1			T1	8993		T2	442		T7	23
valid_sources[0x09]	1373017	1			T1	9160		T2	373		T7	29
valid_sources[0x0a]	1315061	1			T1	8957		T2	420		T7	22
valid_sources[0x0b]	1292784	1			T1	9060		T2	354		T7	23
valid_sources[0x0c]	1490834	1			T1	9180		T2	352		T7	21
valid_sources[0x0d]	3242513	1			T1	9201		T2	371		T7	28
valid_sources[0x0e]	1360056	1			T1	9094		T2	483		T7	23
valid_sources[0x0f]	1290579	1			T1	9131		T2	363		T7	20
valid_sources[0x10]	1304103	1			T1	9004		T2	373		T7	31
valid_sources[0x11]	1316168	1			T1	9068		T2	439		T7	20
valid_sources[0x12]	1436193	1			T1	9024		T2	463		T7	28
valid_sources[0x13]	1290312	1			T1	9072		T2	430		T7	19
valid_sources[0x14]	1292761	1			T1	9119		T2	433		T7	28
valid_sources[0x15]	1294292	1			T1	9092		T2	429		T7	38
valid_sources[0x16]	1375471	1			T1	9264		T2	370		T7	33
valid_sources[0x17]	2229666	1			T1	8986		T2	388		T7	30
valid_sources[0x18]	1296117	1			T1	9239		T2	440		T7	22
valid_sources[0x19]	1299708	1			T1	9167		T2	316		T7	23
valid_sources[0x1a]	1297178	1			T1	8929		T2	444		T7	33
valid_sources[0x1b]	1287376	1			T1	9048		T2	465		T7	24
valid_sources[0x1c]	1410551	1			T1	9073		T2	421		T7	28
valid_sources[0x1d]	1301841	1			T1	9041		T2	471		T7	15
valid_sources[0x1e]	1288048	1			T1	9179		T2	462		T7	24
valid_sources[0x1f]	1295310	1			T1	9142		T2	456		T7	20
valid_sources[0x20]	1763083	1			T1	9074		T2	424		T7	26
valid_sources[0x21]	1299879	1			T1	8965		T2	413		T7	31
valid_sources[0x22]	1751258	1			T1	8989		T2	440		T7	22
valid_sources[0x23]	1291351	1			T1	8970		T2	487		T7	17
valid_sources[0x24]	1357237	1			T1	9225		T2	364		T7	25
valid_sources[0x25]	2144762	1			T1	9024		T2	465		T7	17
valid_sources[0x26]	1414611	1			T1	9195		T2	467		T7	29
valid_sources[0x27]	3365322	1			T1	9109		T2	463		T7	21
valid_sources[0x28]	1300947	1			T1	9123		T2	502		T7	20
valid_sources[0x29]	1593266	1			T1	8960		T2	327		T7	19
valid_sources[0x2a]	1294447	1			T1	8998		T2	422		T7	28
valid_sources[0x2b]	3510535	1			T1	9250		T2	442		T7	22
valid_sources[0x2c]	1292344	1			T1	8887		T2	400		T7	16
valid_sources[0x2d]	2199902	1			T1	9279		T2	424		T7	18
valid_sources[0x2e]	1330717	1			T1	9019		T2	394		T7	19
valid_sources[0x2f]	1939226	1			T1	9150		T2	368		T7	30
valid_sources[0x30]	1297669	1			T1	9121		T2	392		T7	23
valid_sources[0x31]	3638832	1			T1	9175		T2	508		T7	19
valid_sources[0x32]	1295415	1			T1	8822		T2	429		T7	26
valid_sources[0x33]	1298048	1			T1	9311		T2	415		T7	20
valid_sources[0x34]	1294628	1			T1	9081		T2	395		T7	38
valid_sources[0x35]	1464513	1			T1	9125		T2	447		T7	23
valid_sources[0x36]	1415477	1			T1	9259		T2	433		T7	22
valid_sources[0x37]	2142119	1			T1	9275		T2	488		T7	17
valid_sources[0x38]	1300655	1			T1	9119		T2	470		T7	20
valid_sources[0x39]	3557501	1			T1	9260		T2	502		T7	27
valid_sources[0x3a]	1288411	1			T1	9117		T2	419		T7	28
valid_sources[0x3b]	1302724	1			T1	9134		T2	500		T7	23
valid_sources[0x3c]	1373438	1			T1	9131		T2	440		T7	24
valid_sources[0x3d]	2798325	1			T1	8993		T2	560		T7	28
valid_sources[0x3e]	1957074	1			T1	9223		T2	493		T7	23
valid_sources[0x3f]	1484432	1			T1	9084		T2	423		T7	26
valid_sources[0x40]	4968024	1			T1	9104		T2	404		T7	33
valid_sources[0x41]	1301134	1			T1	8914		T2	318		T7	25
valid_sources[0x42]	3231185	1			T1	9029		T2	446		T7	22
valid_sources[0x43]	2205516	1			T1	9157		T2	443		T7	25
valid_sources[0x44]	1290463	1			T1	9178		T2	428		T7	32
valid_sources[0x45]	1296721	1			T1	9160		T2	492		T7	19
valid_sources[0x46]	1297389	1			T1	9078		T2	397		T7	21
valid_sources[0x47]	3213187	1			T1	9179		T2	432		T7	25
valid_sources[0x48]	1951908	1			T1	9104		T2	465		T7	15
valid_sources[0x49]	1293083	1			T1	9148		T2	415		T7	27
valid_sources[0x4a]	1902861	1			T1	9230		T2	448		T7	33
valid_sources[0x4b]	1291397	1			T1	9135		T2	363		T7	26
valid_sources[0x4c]	1930697	1			T1	9003		T2	335		T7	29
valid_sources[0x4d]	1294860	1			T1	9180		T2	498		T7	20
valid_sources[0x4e]	2187803	1			T1	9079		T2	382		T7	21
valid_sources[0x4f]	3611021	1			T1	9135		T2	442		T7	28
valid_sources[0x50]	2195060	1			T1	9069		T2	417		T7	29
valid_sources[0x51]	1295862	1			T1	8935		T2	425		T7	20
valid_sources[0x52]	1298789	1			T1	9152		T2	471		T7	24
valid_sources[0x53]	1299577	1			T1	9261		T2	505		T7	18
valid_sources[0x54]	1323542	1			T1	9221		T2	457		T7	25
valid_sources[0x55]	1291504	1			T1	8851		T2	372		T7	26
valid_sources[0x56]	2295967	1			T1	9220		T2	417		T7	29
valid_sources[0x57]	1291853	1			T1	9044		T2	416		T7	31
valid_sources[0x58]	1286173	1			T1	9139		T2	446		T7	20
valid_sources[0x59]	3630322	1			T1	8994		T2	487		T7	21
valid_sources[0x5a]	1294884	1			T1	9159		T2	460		T7	26
valid_sources[0x5b]	1290736	1			T1	9039		T2	430		T7	26
valid_sources[0x5c]	3683243	1			T1	9110		T2	466		T7	18
valid_sources[0x5d]	1433958	1			T1	8944		T2	385		T7	20
valid_sources[0x5e]	4159253	1			T1	9160		T2	484		T7	33
valid_sources[0x5f]	1298477	1			T1	9123		T2	451		T7	21
valid_sources[0x60]	1299580	1			T1	9065		T2	438		T7	27
valid_sources[0x61]	1295902	1			T1	9075		T2	393		T7	29
valid_sources[0x62]	1296623	1			T1	9209		T2	440		T7	19
valid_sources[0x63]	1297063	1			T1	8940		T2	450		T7	24
valid_sources[0x64]	1295054	1			T1	8994		T2	395		T7	12
valid_sources[0x65]	1295018	1			T1	8925		T2	430		T7	30
valid_sources[0x66]	1755057	1			T1	8954		T2	403		T7	20
valid_sources[0x67]	1292831	1			T1	8933		T2	468		T7	22
valid_sources[0x68]	1287259	1			T1	8893		T2	386		T7	14
valid_sources[0x69]	1297866	1			T1	9160		T2	436		T7	26
valid_sources[0x6a]	3290535	1			T1	8950		T2	472		T7	27
valid_sources[0x6b]	1293166	1			T1	9059		T2	398		T7	19
valid_sources[0x6c]	1291622	1			T1	9060		T2	392		T7	24
valid_sources[0x6d]	1283203	1			T1	9115		T2	444		T7	17
valid_sources[0x6e]	1294035	1			T1	9177		T2	408		T7	18
valid_sources[0x6f]	1288166	1			T1	9133		T2	365		T7	26
valid_sources[0x70]	1302178	1			T1	9088		T2	449		T7	22
valid_sources[0x71]	1294984	1			T1	9198		T2	391		T7	27
valid_sources[0x72]	1298650	1			T1	9001		T2	367		T7	22
valid_sources[0x73]	1296932	1			T1	8887		T2	397		T7	26
valid_sources[0x74]	1299450	1			T1	9022		T2	460		T7	27
valid_sources[0x75]	1297280	1			T1	9033		T2	340		T7	21
valid_sources[0x76]	3249381	1			T1	9144		T2	408		T7	27
valid_sources[0x77]	1340680	1			T1	9176		T2	453		T7	20
valid_sources[0x78]	1938262	1			T1	9118		T2	432		T7	29
valid_sources[0x79]	1303354	1			T1	9083		T2	465		T7	30
valid_sources[0x7a]	1296040	1			T1	9197		T2	433		T7	27
valid_sources[0x7b]	4485610	1			T1	9113		T2	460		T7	27
valid_sources[0x7c]	1646096	1			T1	9077		T2	529		T7	26
valid_sources[0x7d]	4188069	1			T1	9149		T2	445		T7	25
valid_sources[0x7e]	1302590	1			T1	9209		T2	490		T7	27
valid_sources[0x7f]	1293821	1			T1	8967		T2	464		T7	23
valid_sources[0x80]	1286230	1			T1	9035		T2	375		T7	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71712695

1

T1

335578

T2

45791

T3

63168

values[0x0]

all_enables

biggest_size

61222837

1

T1

312394

T2

10834

T3

61087

values[0x1]

all_enables

biggest_size

52704563

1

T1

263734

T2

9454

T3

51561