Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	259279641	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183280531

1

T1

12575

T2

1053

T3

1057

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	229528909	1			T1	8857		T2	819		T3	853
values[0x0]	102367678	1			T1	3066		T2	489		T3	483
values[0x1]	110663585	1			T1	3236		T2	446		T3	526

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201594622	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

240965550

1

T1

13261

T2

1209

T3

1259

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1515285	1			T1	1		T2	11		T3	3
valid_sources[0x01]	1810253	1			T1	1		T2	6		T3	4
valid_sources[0x02]	1375229	1			T1	1		T2	5		T3	6
valid_sources[0x03]	2037638	1			T2	5		T3	12		T9	2
valid_sources[0x04]	1388041	1			T1	1		T2	5		T3	5
valid_sources[0x05]	1382955	1			T1	3		T2	3		T3	6
valid_sources[0x06]	1386377	1			T2	9		T3	9		T9	3
valid_sources[0x07]	1408939	1			T1	2		T2	4		T3	6
valid_sources[0x08]	1383064	1			T1	1		T2	3		T3	8
valid_sources[0x09]	1396949	1			T1	1		T2	8		T3	7
valid_sources[0x0a]	1391063	1			T1	2		T2	3		T3	8
valid_sources[0x0b]	1380598	1			T1	1		T2	3		T3	6
valid_sources[0x0c]	2062694	1			T1	2		T2	7		T9	3
valid_sources[0x0d]	1384415	1			T2	3		T3	4		T9	1
valid_sources[0x0e]	1386385	1			T2	6		T3	8		T9	5
valid_sources[0x0f]	1381945	1			T2	6		T3	9		T9	1
valid_sources[0x10]	1397640	1			T1	2		T2	7		T3	2
valid_sources[0x11]	1373714	1			T1	2		T2	8		T3	13
valid_sources[0x12]	1841280	1			T1	1		T2	6		T3	6
valid_sources[0x13]	2220349	1			T2	5		T3	8		T9	4
valid_sources[0x14]	1392560	1			T2	8		T3	9		T9	4
valid_sources[0x15]	1922140	1			T2	5		T3	3		T9	9
valid_sources[0x16]	1375001	1			T2	8		T3	5		T9	6
valid_sources[0x17]	1431157	1			T1	2		T2	5		T3	6
valid_sources[0x18]	2295688	1			T2	4		T3	8		T9	4
valid_sources[0x19]	1388972	1			T1	1		T2	12		T3	5
valid_sources[0x1a]	2033297	1			T1	2		T2	5		T3	10
valid_sources[0x1b]	2150429	1			T1	1		T2	6		T3	5
valid_sources[0x1c]	3358571	1			T2	3		T3	8		T9	11
valid_sources[0x1d]	2176897	1			T1	1		T2	10		T3	2
valid_sources[0x1e]	2026453	1			T1	3		T2	7		T3	11
valid_sources[0x1f]	1382491	1			T2	6		T3	8		T9	5
valid_sources[0x20]	1982754	1			T2	9		T3	7		T9	5
valid_sources[0x21]	2288064	1			T2	1		T3	9		T10	10
valid_sources[0x22]	1468111	1			T1	2		T2	7		T3	9
valid_sources[0x23]	1395162	1			T1	1		T2	7		T3	14
valid_sources[0x24]	1423869	1			T2	18		T3	4		T9	1
valid_sources[0x25]	1385278	1			T2	7		T3	9		T9	2
valid_sources[0x26]	1381874	1			T1	1		T2	3		T3	7
valid_sources[0x27]	1375586	1			T2	5		T3	13		T9	2
valid_sources[0x28]	1421403	1			T1	3		T2	8		T3	7
valid_sources[0x29]	1384411	1			T1	1		T2	7		T3	4
valid_sources[0x2a]	1382398	1			T1	2		T2	12		T3	1
valid_sources[0x2b]	1384367	1			T1	2		T2	5		T3	8
valid_sources[0x2c]	1385632	1			T1	1		T2	14		T3	15
valid_sources[0x2d]	1377182	1			T1	1		T2	3		T3	6
valid_sources[0x2e]	1377303	1			T1	2		T2	12		T3	9
valid_sources[0x2f]	3812947	1			T2	6		T3	9		T9	3
valid_sources[0x30]	1371023	1			T1	1		T2	3		T3	8
valid_sources[0x31]	1382559	1			T1	3		T2	9		T3	13
valid_sources[0x32]	1386008	1			T1	1		T2	5		T3	10
valid_sources[0x33]	5569999	1			T1	1		T2	13		T3	7
valid_sources[0x34]	3720690	1			T2	4		T3	5		T9	1
valid_sources[0x35]	1371643	1			T2	5		T3	14		T9	4
valid_sources[0x36]	2066830	1			T1	1		T2	9		T3	8
valid_sources[0x37]	1382218	1			T1	1		T2	9		T3	9
valid_sources[0x38]	1386194	1			T2	9		T3	8		T9	1
valid_sources[0x39]	1447180	1			T2	10		T3	4		T9	4
valid_sources[0x3a]	1373502	1			T1	2		T2	7		T3	2
valid_sources[0x3b]	1388327	1			T1	1		T2	3		T3	7
valid_sources[0x3c]	1382626	1			T1	1		T2	6		T3	11
valid_sources[0x3d]	1506319	1			T2	5		T3	3		T9	7
valid_sources[0x3e]	1432590	1			T1	1		T2	10		T3	9
valid_sources[0x3f]	1516069	1			T1	2		T2	5		T3	8
valid_sources[0x40]	1956273	1			T1	1		T2	8		T3	11
valid_sources[0x41]	2153538	1			T1	1		T2	10		T3	10
valid_sources[0x42]	2276912	1			T1	1		T2	3		T3	5
valid_sources[0x43]	1381612	1			T2	11		T3	7		T9	4
valid_sources[0x44]	1381068	1			T1	2		T2	19		T3	8
valid_sources[0x45]	1388274	1			T1	2		T2	3		T3	8
valid_sources[0x46]	1385499	1			T1	1		T2	5		T3	5
valid_sources[0x47]	1385151	1			T1	1		T2	6		T3	8
valid_sources[0x48]	1376329	1			T2	8		T3	4		T9	3
valid_sources[0x49]	3357371	1			T1	1		T2	13		T3	10
valid_sources[0x4a]	1384951	1			T2	4		T3	4		T9	2
valid_sources[0x4b]	1374664	1			T2	1		T3	5		T9	7
valid_sources[0x4c]	2023988	1			T2	9		T3	11		T9	4
valid_sources[0x4d]	1600519	1			T1	2		T2	7		T3	5
valid_sources[0x4e]	1393278	1			T1	1		T2	1		T3	3
valid_sources[0x4f]	1550823	1			T1	1		T2	10		T3	2
valid_sources[0x50]	1397632	1			T1	1		T2	5		T3	7
valid_sources[0x51]	1550952	1			T1	1		T2	11		T3	12
valid_sources[0x52]	2273408	1			T2	4		T3	8		T9	2
valid_sources[0x53]	1385074	1			T1	1		T2	6		T3	7
valid_sources[0x54]	2283708	1			T1	2		T2	8		T3	9
valid_sources[0x55]	2280722	1			T1	1		T2	14		T3	5
valid_sources[0x56]	1395390	1			T1	1		T2	7		T3	13
valid_sources[0x57]	1387022	1			T1	1		T2	1		T3	5
valid_sources[0x58]	1638081	1			T1	1		T2	5		T3	12
valid_sources[0x59]	1377901	1			T1	1		T2	7		T3	9
valid_sources[0x5a]	1440435	1			T2	3		T3	11		T9	6
valid_sources[0x5b]	1382907	1			T1	1		T2	8		T3	2
valid_sources[0x5c]	1379272	1			T2	5		T3	8		T9	2
valid_sources[0x5d]	1379068	1			T2	6		T3	10		T9	6
valid_sources[0x5e]	3329567	1			T1	2		T2	3		T3	6
valid_sources[0x5f]	4591061	1			T2	8		T3	11		T9	3
valid_sources[0x60]	2041590	1			T1	1		T2	4		T3	8
valid_sources[0x61]	1380521	1			T2	10		T3	9		T9	7
valid_sources[0x62]	2305823	1			T1	1		T2	8		T3	5
valid_sources[0x63]	1467507	1			T2	14		T3	6		T9	4
valid_sources[0x64]	1381068	1			T2	10		T3	9		T9	7
valid_sources[0x65]	1372430	1			T2	17		T3	12		T9	1
valid_sources[0x66]	1383820	1			T1	1		T2	14		T3	8
valid_sources[0x67]	1411732	1			T1	1		T2	8		T3	8
valid_sources[0x68]	2930112	1			T1	1		T2	7		T3	2
valid_sources[0x69]	1382340	1			T1	1		T2	3		T3	8
valid_sources[0x6a]	2517351	1			T1	2		T2	7		T3	1
valid_sources[0x6b]	1379494	1			T2	13		T3	8		T9	3
valid_sources[0x6c]	1507922	1			T1	1		T2	15		T3	3
valid_sources[0x6d]	1657151	1			T1	1		T2	1		T3	8
valid_sources[0x6e]	3341891	1			T2	5		T3	7		T9	5
valid_sources[0x6f]	1848553	1			T1	2		T2	5		T3	7
valid_sources[0x70]	1382058	1			T2	11		T3	10		T9	4
valid_sources[0x71]	1376669	1			T1	1		T2	2		T3	3
valid_sources[0x72]	1383390	1			T2	7		T3	9		T9	6
valid_sources[0x73]	5297207	1			T2	15		T3	5		T9	6
valid_sources[0x74]	1567066	1			T2	3		T3	13		T9	4
valid_sources[0x75]	1389687	1			T1	1		T2	6		T3	8
valid_sources[0x76]	1387403	1			T2	8		T3	8		T9	4
valid_sources[0x77]	1387437	1			T1	1		T2	8		T3	3
valid_sources[0x78]	1823327	1			T1	1		T2	4		T3	5
valid_sources[0x79]	1380150	1			T1	2		T2	5		T3	7
valid_sources[0x7a]	2226588	1			T1	2		T2	5		T3	4
valid_sources[0x7b]	1384866	1			T1	1		T2	4		T3	6
valid_sources[0x7c]	1376836	1			T2	2		T3	7		T9	3
valid_sources[0x7d]	1383342	1			T2	13		T3	11		T9	3
valid_sources[0x7e]	1383078	1			T2	3		T3	9		T9	4
valid_sources[0x7f]	1380572	1			T2	3		T3	7		T9	2
valid_sources[0x80]	1385872	1			T2	8		T3	2		T9	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

71199116

1

T1

7377

T2

323

T3

340

values[0x0]

all_enables

biggest_size

60268298

1

T1

2603

T2

388

T3

370

values[0x1]

all_enables

biggest_size

51813117

1

T1

2595

T2

342

T3

347