Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

260362055

1

T1

2584

T2

701

T3

805

full_word

183347899

1

T1

12575

T2

1053

T3

1057

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	443709654	1			T1	15159		T2	1754		T3	1862
auto[TlIntgErrCmd]	89	1			T116	5		T117	1		T118	5
auto[TlIntgErrData]	101	1			T116	11		T117	4		T118	9
auto[TlIntgErrBoth]	110	1			T116	4		T117	5		T118	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229784688

1

T1

8857

T2

819

T3

853

auto[1]

213925266

1

T1

6302

T2

935

T3

1009

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	158565943	1			T1	1480		T2	496		T3	513
auto[TlIntgErrNone]	partial	auto[1]	101795841	1			T1	1104		T2	205		T3	292
auto[TlIntgErrNone]	full_word	auto[0]	71218607	1			T1	7377		T2	323		T3	340
auto[TlIntgErrNone]	full_word	auto[1]	112129263	1			T1	5198		T2	730		T3	717
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T116	1		T118	2		T175	1
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T116	4		T118	3		T132	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T117	1		T178	1		T177	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T177	1		T179	1		T180	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T116	5		T117	3		T118	2
auto[TlIntgErrData]	partial	auto[1]	41	1			T116	5		T117	1		T118	5
auto[TlIntgErrData]	full_word	auto[0]	7	1			T118	2		T175	1		T181	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T116	1		T175	1		T182	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T116	3		T117	1		T118	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T116	1		T117	3		T118	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T117	1		T122	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T118	1		T181	1		T179	1