Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

50075902

1

T1

379

T2

242

T3

75

full_word

47950611

1

T1

750

T2

298

T3

104

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	98026213	1			T1	1129		T2	540		T3	179
auto[TlIntgErrCmd]	91	1			T128	9		T129	5		T130	8
auto[TlIntgErrData]	106	1			T128	7		T129	9		T130	7
auto[TlIntgErrBoth]	103	1			T128	4		T129	6		T130	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54760349

1

T1

946

T2

217

T3

57

auto[1]

43266164

1

T1

183

T2

323

T3

122

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	33440198	1			T1	362		T2	127		T3	30
auto[TlIntgErrNone]	partial	auto[1]	16635427	1			T1	17		T2	115		T3	45
auto[TlIntgErrNone]	full_word	auto[0]	21320013	1			T1	584		T2	90		T3	27
auto[TlIntgErrNone]	full_word	auto[1]	26630575	1			T1	166		T2	208		T3	77
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T128	5		T129	3		T130	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T128	4		T129	1		T130	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T166	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T129	1		T164	1		T169	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T128	3		T129	3		T130	5
auto[TlIntgErrData]	partial	auto[1]	49	1			T128	4		T129	5		T130	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T167	2		T170	1		T171	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T129	1		T130	1		T170	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T129	5		T130	3		T166	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T128	4		T130	2		T166	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T129	1		T172	1		T173	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T174	1		T169	1		T175	1