Module Definition
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Module : prim_subreg_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_intr_state_fifo_empty.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_entropy_refresh_hash_cnt.wr_en_data_arb 50.00 50.00
tb.dut.u_reg.u_intr_state_kmac_done.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_state_kmac_err.wr_en_data_arb 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_done.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_fifo_empty.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_err.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_period_prescaler.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_period_wait_timer.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.staged_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.shadow_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.committed_reg.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_key_len.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_0.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_1.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_2.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_3.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_4.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_5.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_6.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_7.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_8.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_9.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_prefix_10.wr_en_data_arb 100.00 100.00 100.00 100.00
tb.dut.u_reg.u_err_code.wr_en_data_arb 100.00 100.00

Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_kmac_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_state_kmac_err.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
88 1 1
110 1 1


Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 + DW=32,SwAccess=1,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
50.00 50.00
tb.dut.u_reg.u_intr_state_fifo_empty.wr_en_data_arb

SCORELINE
50.00 50.00
tb.dut.u_reg.u_entropy_refresh_hash_cnt.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_err_code.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN4311100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
43 1 1
44 1 1
51 unreachable
52 unreachable
53 unreachable


Line Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=32,SwAccess=0,Mubi=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_done.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_fifo_empty.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_err.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_entropy_period_prescaler.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_entropy_period_wait_timer.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.staged_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.shadow_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.committed_reg.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_key_len.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_0.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_1.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_2.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_3.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_4.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_5.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_6.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_7.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_8.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_9.wr_en_data_arb

SCORELINE
100.00 100.00
tb.dut.u_reg.u_prefix_10.wr_en_data_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
33 1 1
34 1 1
39 unreachable


Cond Coverage for Module : prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kstrength.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_key_len.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=10,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_period_prescaler.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_refresh_threshold_shadowed.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_kmac_done.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_state_kmac_err.wr_en_data_arb

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_done.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_fifo_empty.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_intr_enable_kmac_err.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_kmac_en.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_endianness.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_state_endianness.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_sideload.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_fast_process.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_msg_mask.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_ready.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_en_unsupported_modestrength.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=16,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_entropy_period_wait_timer.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_0.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_1.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_2.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_3.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_4.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_5.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_6.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_7.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_8.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_9.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_prefix_10.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T7,T8

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T8

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T7,T8

Cond Coverage for Module : prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_mode.committed_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.staged_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.shadow_reg.wr_en_data_arb

SCORECOND
100.00 100.00
tb.dut.u_reg.u_cfg_shadowed_entropy_mode.committed_reg.wr_en_data_arb

TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT1,T2,T3

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_subreg_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 34 ((we == 1'b1)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%