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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.95 98.11 92.78 99.89 80.99 95.93 99.07 97.88


Total test records in report: 934
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T778 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1727168320 Oct 15 03:01:44 AM UTC 24 Oct 15 03:01:46 AM UTC 24 150869844 ps
T779 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.215598754 Oct 15 03:01:47 AM UTC 24 Oct 15 03:01:50 AM UTC 24 62152648 ps
T780 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.469091980 Oct 15 03:01:47 AM UTC 24 Oct 15 03:01:50 AM UTC 24 25777547 ps
T781 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.1276867595 Oct 15 03:01:44 AM UTC 24 Oct 15 03:01:50 AM UTC 24 64160056 ps
T782 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.968503373 Oct 15 03:01:47 AM UTC 24 Oct 15 03:01:51 AM UTC 24 688669846 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2087603879 Oct 15 03:01:44 AM UTC 24 Oct 15 03:01:52 AM UTC 24 244177931 ps
T783 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.312203691 Oct 15 03:01:51 AM UTC 24 Oct 15 03:01:53 AM UTC 24 12770429 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.1291234196 Oct 15 03:01:51 AM UTC 24 Oct 15 03:01:54 AM UTC 24 112373494 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.3425753877 Oct 15 03:01:53 AM UTC 24 Oct 15 03:01:55 AM UTC 24 19337148 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3797151337 Oct 15 03:01:51 AM UTC 24 Oct 15 03:01:56 AM UTC 24 49907248 ps
T784 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1747841362 Oct 15 03:01:51 AM UTC 24 Oct 15 03:01:57 AM UTC 24 157527867 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.87793741 Oct 15 03:01:51 AM UTC 24 Oct 15 03:01:57 AM UTC 24 414044852 ps
T785 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.1730699489 Oct 15 03:01:55 AM UTC 24 Oct 15 03:01:57 AM UTC 24 60714162 ps
T786 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.3197684821 Oct 15 03:01:55 AM UTC 24 Oct 15 03:01:57 AM UTC 24 102046559 ps
T787 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.3488113706 Oct 15 03:01:35 AM UTC 24 Oct 15 03:01:58 AM UTC 24 1011604554 ps
T788 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.370306065 Oct 15 03:01:28 AM UTC 24 Oct 15 03:01:58 AM UTC 24 4016580526 ps
T789 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.3374642483 Oct 15 03:01:47 AM UTC 24 Oct 15 03:01:59 AM UTC 24 564051345 ps
T790 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3981178331 Oct 15 03:01:58 AM UTC 24 Oct 15 03:02:01 AM UTC 24 22393650 ps
T791 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1448435267 Oct 15 03:01:45 AM UTC 24 Oct 15 03:02:01 AM UTC 24 1447436410 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1068637269 Oct 15 03:01:58 AM UTC 24 Oct 15 03:02:01 AM UTC 24 190107090 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.2260548422 Oct 15 03:01:58 AM UTC 24 Oct 15 03:02:01 AM UTC 24 58801401 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.19831980 Oct 15 03:01:59 AM UTC 24 Oct 15 03:02:01 AM UTC 24 74926907 ps
T792 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.4284778880 Oct 15 03:01:57 AM UTC 24 Oct 15 03:02:02 AM UTC 24 116001458 ps
T793 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.812328651 Oct 15 03:01:57 AM UTC 24 Oct 15 03:02:02 AM UTC 24 1275908169 ps
T794 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4252900433 Oct 15 03:01:58 AM UTC 24 Oct 15 03:02:02 AM UTC 24 54664350 ps
T795 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.3048183835 Oct 15 03:01:56 AM UTC 24 Oct 15 03:02:03 AM UTC 24 293745031 ps
T796 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.797667564 Oct 15 03:02:01 AM UTC 24 Oct 15 03:02:03 AM UTC 24 56251625 ps
T797 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.327896307 Oct 15 03:02:02 AM UTC 24 Oct 15 03:02:04 AM UTC 24 14464298 ps
T798 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.2933208030 Oct 15 03:01:59 AM UTC 24 Oct 15 03:02:05 AM UTC 24 117352469 ps
T799 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2791380631 Oct 15 03:01:55 AM UTC 24 Oct 15 03:02:05 AM UTC 24 603351812 ps
T800 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2173923194 Oct 15 03:02:03 AM UTC 24 Oct 15 03:02:06 AM UTC 24 79267565 ps
T801 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.666862927 Oct 15 03:02:03 AM UTC 24 Oct 15 03:02:06 AM UTC 24 47558202 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.2546799221 Oct 15 03:02:04 AM UTC 24 Oct 15 03:02:06 AM UTC 24 21796102 ps
T802 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.808479953 Oct 15 03:02:02 AM UTC 24 Oct 15 03:02:07 AM UTC 24 327545985 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.4107470159 Oct 15 03:01:59 AM UTC 24 Oct 15 03:02:07 AM UTC 24 749697800 ps
T803 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.500136035 Oct 15 03:02:05 AM UTC 24 Oct 15 03:02:08 AM UTC 24 24045101 ps
T804 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2035236222 Oct 15 03:02:03 AM UTC 24 Oct 15 03:02:08 AM UTC 24 236065695 ps
T805 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2086704162 Oct 15 03:02:03 AM UTC 24 Oct 15 03:02:08 AM UTC 24 418301322 ps
T806 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.3168665366 Oct 15 03:02:03 AM UTC 24 Oct 15 03:02:09 AM UTC 24 154361515 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3787745954 Oct 15 03:02:06 AM UTC 24 Oct 15 03:02:10 AM UTC 24 62989448 ps
T807 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2472853553 Oct 15 03:02:06 AM UTC 24 Oct 15 03:02:10 AM UTC 24 64568267 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3034577189 Oct 15 03:02:04 AM UTC 24 Oct 15 03:02:10 AM UTC 24 107687676 ps
T808 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.1071609218 Oct 15 03:02:08 AM UTC 24 Oct 15 03:02:11 AM UTC 24 25969719 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.4290680593 Oct 15 03:02:07 AM UTC 24 Oct 15 03:02:11 AM UTC 24 346773030 ps
T809 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3297604768 Oct 15 03:02:06 AM UTC 24 Oct 15 03:02:11 AM UTC 24 481821372 ps
T810 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3064633203 Oct 15 03:02:09 AM UTC 24 Oct 15 03:02:11 AM UTC 24 24077044 ps
T811 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2970726986 Oct 15 03:02:09 AM UTC 24 Oct 15 03:02:12 AM UTC 24 39211576 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.2694132053 Oct 15 03:02:08 AM UTC 24 Oct 15 03:02:13 AM UTC 24 201926141 ps
T812 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3164432724 Oct 15 03:02:09 AM UTC 24 Oct 15 03:02:13 AM UTC 24 225131729 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.2793537459 Oct 15 03:02:11 AM UTC 24 Oct 15 03:02:13 AM UTC 24 16514101 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3020951717 Oct 15 03:02:10 AM UTC 24 Oct 15 03:02:13 AM UTC 24 286798200 ps
T813 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2519496472 Oct 15 03:02:10 AM UTC 24 Oct 15 03:02:14 AM UTC 24 138845216 ps
T814 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.2375072112 Oct 15 03:02:12 AM UTC 24 Oct 15 03:02:15 AM UTC 24 41910916 ps
T815 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2589172197 Oct 15 03:02:12 AM UTC 24 Oct 15 03:02:15 AM UTC 24 121817754 ps
T816 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1633569390 Oct 15 03:02:12 AM UTC 24 Oct 15 03:02:16 AM UTC 24 135328407 ps
T817 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.4025864803 Oct 15 03:02:14 AM UTC 24 Oct 15 03:02:16 AM UTC 24 33097381 ps
T818 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3532245945 Oct 15 03:02:12 AM UTC 24 Oct 15 03:02:16 AM UTC 24 133563860 ps
T819 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.404020509 Oct 15 03:02:12 AM UTC 24 Oct 15 03:02:16 AM UTC 24 542975318 ps
T820 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2085030198 Oct 15 03:02:14 AM UTC 24 Oct 15 03:02:16 AM UTC 24 52157701 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3276824920 Oct 15 03:02:11 AM UTC 24 Oct 15 03:02:16 AM UTC 24 148199870 ps
T821 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.559511728 Oct 15 03:02:11 AM UTC 24 Oct 15 03:02:17 AM UTC 24 471822423 ps
T822 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2503574972 Oct 15 03:02:14 AM UTC 24 Oct 15 03:02:18 AM UTC 24 611608782 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.2190940873 Oct 15 03:02:14 AM UTC 24 Oct 15 03:02:18 AM UTC 24 116019339 ps
T823 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2222869173 Oct 15 03:02:15 AM UTC 24 Oct 15 03:02:18 AM UTC 24 165653960 ps
T824 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3268221052 Oct 15 03:02:16 AM UTC 24 Oct 15 03:02:18 AM UTC 24 26737441 ps
T825 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.291965415 Oct 15 03:02:15 AM UTC 24 Oct 15 03:02:19 AM UTC 24 390540102 ps
T826 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2839569952 Oct 15 03:02:16 AM UTC 24 Oct 15 03:02:19 AM UTC 24 82250334 ps
T827 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.1489349261 Oct 15 03:02:17 AM UTC 24 Oct 15 03:02:20 AM UTC 24 25933692 ps
T828 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.14094049 Oct 15 03:02:17 AM UTC 24 Oct 15 03:02:20 AM UTC 24 45219832 ps
T829 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.3372358771 Oct 15 03:02:16 AM UTC 24 Oct 15 03:02:20 AM UTC 24 278953520 ps
T830 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3028213956 Oct 15 03:02:17 AM UTC 24 Oct 15 03:02:20 AM UTC 24 86298992 ps
T831 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3291192754 Oct 15 03:02:02 AM UTC 24 Oct 15 03:02:20 AM UTC 24 5637247618 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.404948600 Oct 15 03:02:19 AM UTC 24 Oct 15 03:02:21 AM UTC 24 14859767 ps
T832 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3874869331 Oct 15 03:02:17 AM UTC 24 Oct 15 03:02:21 AM UTC 24 167283618 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3986006740 Oct 15 03:02:17 AM UTC 24 Oct 15 03:02:21 AM UTC 24 74464030 ps
T833 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.2724011716 Oct 15 03:02:19 AM UTC 24 Oct 15 03:02:21 AM UTC 24 60569340 ps
T834 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2034193294 Oct 15 03:02:33 AM UTC 24 Oct 15 03:02:35 AM UTC 24 23449112 ps
T835 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2610754143 Oct 15 03:02:17 AM UTC 24 Oct 15 03:02:22 AM UTC 24 82053156 ps
T836 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.292969325 Oct 15 03:02:19 AM UTC 24 Oct 15 03:02:22 AM UTC 24 33877482 ps
T837 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1262372983 Oct 15 03:02:19 AM UTC 24 Oct 15 03:02:22 AM UTC 24 157921214 ps
T838 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3176289796 Oct 15 03:02:20 AM UTC 24 Oct 15 03:02:22 AM UTC 24 73657560 ps
T839 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1583389524 Oct 15 03:02:20 AM UTC 24 Oct 15 03:02:23 AM UTC 24 23674829 ps
T840 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1474557037 Oct 15 03:02:21 AM UTC 24 Oct 15 03:02:23 AM UTC 24 15041543 ps
T841 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1769823172 Oct 15 03:02:20 AM UTC 24 Oct 15 03:02:23 AM UTC 24 188748925 ps
T842 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1653764122 Oct 15 03:02:21 AM UTC 24 Oct 15 03:02:24 AM UTC 24 84336710 ps
T843 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.93658871 Oct 15 03:02:21 AM UTC 24 Oct 15 03:02:24 AM UTC 24 27466044 ps
T844 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.466141772 Oct 15 03:02:21 AM UTC 24 Oct 15 03:02:24 AM UTC 24 111329130 ps
T845 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3737895972 Oct 15 03:02:23 AM UTC 24 Oct 15 03:02:25 AM UTC 24 22326990 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2478816053 Oct 15 03:02:19 AM UTC 24 Oct 15 03:02:25 AM UTC 24 371883837 ps
T846 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4082460722 Oct 15 03:02:22 AM UTC 24 Oct 15 03:02:25 AM UTC 24 24355192 ps
T847 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4265018012 Oct 15 03:02:21 AM UTC 24 Oct 15 03:02:25 AM UTC 24 65953253 ps
T848 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.49631184 Oct 15 03:02:23 AM UTC 24 Oct 15 03:02:25 AM UTC 24 187267682 ps
T849 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3900071552 Oct 15 03:02:21 AM UTC 24 Oct 15 03:02:26 AM UTC 24 153422861 ps
T850 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3909156568 Oct 15 03:02:22 AM UTC 24 Oct 15 03:02:26 AM UTC 24 75843592 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.344591229 Oct 15 03:02:24 AM UTC 24 Oct 15 03:02:26 AM UTC 24 31755795 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3279707775 Oct 15 03:02:24 AM UTC 24 Oct 15 03:02:27 AM UTC 24 61457750 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2142298460 Oct 15 03:02:24 AM UTC 24 Oct 15 03:02:27 AM UTC 24 76163624 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.435692426 Oct 15 03:02:24 AM UTC 24 Oct 15 03:02:27 AM UTC 24 98795159 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3873834914 Oct 15 03:02:25 AM UTC 24 Oct 15 03:02:27 AM UTC 24 18914928 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.1202615488 Oct 15 03:02:23 AM UTC 24 Oct 15 03:02:27 AM UTC 24 491441294 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3549450604 Oct 15 03:02:25 AM UTC 24 Oct 15 03:02:27 AM UTC 24 128142276 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3249553109 Oct 15 03:02:24 AM UTC 24 Oct 15 03:02:28 AM UTC 24 334250424 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.358453563 Oct 15 03:02:25 AM UTC 24 Oct 15 03:02:28 AM UTC 24 94393320 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3023271660 Oct 15 03:02:25 AM UTC 24 Oct 15 03:02:28 AM UTC 24 87054361 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2825155651 Oct 15 03:02:27 AM UTC 24 Oct 15 03:02:29 AM UTC 24 41437872 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3469827005 Oct 15 03:02:27 AM UTC 24 Oct 15 03:02:29 AM UTC 24 219538414 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1292885664 Oct 15 03:02:28 AM UTC 24 Oct 15 03:02:30 AM UTC 24 32416490 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1763408737 Oct 15 03:02:26 AM UTC 24 Oct 15 03:02:30 AM UTC 24 104506141 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3455821507 Oct 15 03:02:25 AM UTC 24 Oct 15 03:02:30 AM UTC 24 155698079 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.915383575 Oct 15 03:02:28 AM UTC 24 Oct 15 03:02:30 AM UTC 24 25514350 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2439043051 Oct 15 03:02:28 AM UTC 24 Oct 15 03:02:30 AM UTC 24 173995796 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1868310039 Oct 15 03:02:23 AM UTC 24 Oct 15 03:02:31 AM UTC 24 461258628 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.2704245355 Oct 15 03:02:29 AM UTC 24 Oct 15 03:02:31 AM UTC 24 37579417 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1465450270 Oct 15 03:02:27 AM UTC 24 Oct 15 03:02:31 AM UTC 24 298497535 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2646102283 Oct 15 03:02:29 AM UTC 24 Oct 15 03:02:31 AM UTC 24 50559309 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.571285530 Oct 15 03:02:28 AM UTC 24 Oct 15 03:02:31 AM UTC 24 52055672 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3244952632 Oct 15 03:02:28 AM UTC 24 Oct 15 03:02:32 AM UTC 24 51925651 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3277847941 Oct 15 03:02:28 AM UTC 24 Oct 15 03:02:32 AM UTC 24 198607646 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3917998562 Oct 15 03:02:33 AM UTC 24 Oct 15 03:02:35 AM UTC 24 29094638 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3499988520 Oct 15 03:02:28 AM UTC 24 Oct 15 03:02:32 AM UTC 24 59702524 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3247413356 Oct 15 03:02:29 AM UTC 24 Oct 15 03:02:32 AM UTC 24 122590598 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3649903707 Oct 15 03:02:29 AM UTC 24 Oct 15 03:02:33 AM UTC 24 135084685 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4089555758 Oct 15 03:02:30 AM UTC 24 Oct 15 03:02:33 AM UTC 24 55734160 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.198277144 Oct 15 03:02:31 AM UTC 24 Oct 15 03:02:33 AM UTC 24 51218530 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4246551859 Oct 15 03:02:30 AM UTC 24 Oct 15 03:02:33 AM UTC 24 87105760 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1004030490 Oct 15 03:02:30 AM UTC 24 Oct 15 03:02:34 AM UTC 24 108995675 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1186017932 Oct 15 03:02:32 AM UTC 24 Oct 15 03:02:34 AM UTC 24 79361857 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.1324848831 Oct 15 03:02:32 AM UTC 24 Oct 15 03:02:34 AM UTC 24 68962248 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2342494574 Oct 15 03:02:32 AM UTC 24 Oct 15 03:02:35 AM UTC 24 95163620 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3421177083 Oct 15 03:02:30 AM UTC 24 Oct 15 03:02:35 AM UTC 24 246516855 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3650238631 Oct 15 03:02:32 AM UTC 24 Oct 15 03:02:35 AM UTC 24 630903978 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1587912403 Oct 15 03:02:32 AM UTC 24 Oct 15 03:02:35 AM UTC 24 41879575 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2654484056 Oct 15 03:02:32 AM UTC 24 Oct 15 03:02:35 AM UTC 24 138353002 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3129694802 Oct 15 03:02:33 AM UTC 24 Oct 15 03:02:36 AM UTC 24 59437284 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.378490730 Oct 15 03:02:29 AM UTC 24 Oct 15 03:02:36 AM UTC 24 1030696996 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.37731399 Oct 15 03:02:33 AM UTC 24 Oct 15 03:02:36 AM UTC 24 103547911 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3130077654 Oct 15 03:02:33 AM UTC 24 Oct 15 03:02:36 AM UTC 24 356560500 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2200460664 Oct 15 03:02:33 AM UTC 24 Oct 15 03:02:37 AM UTC 24 141023018 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1915819402 Oct 15 03:02:31 AM UTC 24 Oct 15 03:02:37 AM UTC 24 365684044 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1759692566 Oct 15 03:02:33 AM UTC 24 Oct 15 03:02:37 AM UTC 24 129241283 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3178605717 Oct 15 03:02:36 AM UTC 24 Oct 15 03:02:38 AM UTC 24 12636854 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.2561057940 Oct 15 03:02:35 AM UTC 24 Oct 15 03:02:38 AM UTC 24 77538565 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3666349777 Oct 15 03:02:36 AM UTC 24 Oct 15 03:02:38 AM UTC 24 68278649 ps
T171 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2146051762 Oct 15 03:02:34 AM UTC 24 Oct 15 03:02:38 AM UTC 24 197110880 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1294476827 Oct 15 03:02:37 AM UTC 24 Oct 15 03:02:39 AM UTC 24 24003731 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2391883915 Oct 15 03:02:36 AM UTC 24 Oct 15 03:02:39 AM UTC 24 77768523 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2826291006 Oct 15 03:02:37 AM UTC 24 Oct 15 03:02:39 AM UTC 24 51069805 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.4289629856 Oct 15 03:02:37 AM UTC 24 Oct 15 03:02:39 AM UTC 24 27878825 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.232086968 Oct 15 03:02:36 AM UTC 24 Oct 15 03:02:39 AM UTC 24 264285431 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2440796844 Oct 15 03:02:37 AM UTC 24 Oct 15 03:02:40 AM UTC 24 56904066 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.753973630 Oct 15 03:02:37 AM UTC 24 Oct 15 03:02:40 AM UTC 24 208833622 ps
T902 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2488257279 Oct 15 03:02:38 AM UTC 24 Oct 15 03:02:40 AM UTC 24 68667727 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1242308028 Oct 15 03:02:33 AM UTC 24 Oct 15 03:02:40 AM UTC 24 747039293 ps
T904 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.723426995 Oct 15 03:02:37 AM UTC 24 Oct 15 03:02:40 AM UTC 24 26468757 ps
T905 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1456729479 Oct 15 03:02:38 AM UTC 24 Oct 15 03:02:40 AM UTC 24 27891457 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2945055272 Oct 15 03:02:38 AM UTC 24 Oct 15 03:02:40 AM UTC 24 31673200 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3828111001 Oct 15 03:02:38 AM UTC 24 Oct 15 03:02:40 AM UTC 24 34964209 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2770177297 Oct 15 03:02:38 AM UTC 24 Oct 15 03:02:40 AM UTC 24 16307699 ps
T909 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1215561327 Oct 15 03:02:37 AM UTC 24 Oct 15 03:02:40 AM UTC 24 41550896 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1195713492 Oct 15 03:02:38 AM UTC 24 Oct 15 03:02:41 AM UTC 24 14801225 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.1672785029 Oct 15 03:02:37 AM UTC 24 Oct 15 03:02:42 AM UTC 24 280580914 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2647652163 Oct 15 03:02:40 AM UTC 24 Oct 15 03:02:42 AM UTC 24 57368891 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2840946968 Oct 15 03:02:40 AM UTC 24 Oct 15 03:02:42 AM UTC 24 36589480 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.348657273 Oct 15 03:02:40 AM UTC 24 Oct 15 03:02:42 AM UTC 24 56924970 ps
T915 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.413354969 Oct 15 03:02:40 AM UTC 24 Oct 15 03:02:42 AM UTC 24 37170727 ps
T916 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.216471597 Oct 15 03:02:40 AM UTC 24 Oct 15 03:02:42 AM UTC 24 15117651 ps
T917 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1916539579 Oct 15 03:02:40 AM UTC 24 Oct 15 03:02:42 AM UTC 24 15199134 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1236111167 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 29217381 ps
T919 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3214363019 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 122623074 ps
T920 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.461886535 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 31342798 ps
T921 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.3468930699 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 64922506 ps
T922 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1267545206 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 77467326 ps
T923 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2367217956 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 19671215 ps
T924 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1699415179 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 83266719 ps
T925 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2356165052 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 18950637 ps
T926 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.4058785812 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 17811167 ps
T927 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.106087446 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 23158905 ps
T928 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.772192207 Oct 15 03:02:41 AM UTC 24 Oct 15 03:02:43 AM UTC 24 38302201 ps
T929 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3525219608 Oct 15 03:02:42 AM UTC 24 Oct 15 03:02:44 AM UTC 24 23937228 ps
T930 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3077305621 Oct 15 03:02:42 AM UTC 24 Oct 15 03:02:44 AM UTC 24 47037516 ps
T931 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2183144874 Oct 15 03:02:42 AM UTC 24 Oct 15 03:02:45 AM UTC 24 22627291 ps
T932 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3053542610 Oct 15 03:02:43 AM UTC 24 Oct 15 03:02:45 AM UTC 24 19649353 ps
T933 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.273700863 Oct 15 03:02:42 AM UTC 24 Oct 15 03:02:45 AM UTC 24 20946132 ps
T934 /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2552540236 Oct 15 03:02:42 AM UTC 24 Oct 15 03:02:45 AM UTC 24 14342919 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload_invalid.3451862258
Short name T7
Test name
Test status
Simulation time 467058320 ps
CPU time 8.81 seconds
Started Oct 15 04:46:26 AM UTC 24
Finished Oct 15 04:46:36 AM UTC 24
Peak memory 236932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451862258 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload_invalid.3451862258 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.1617455837
Short name T13
Test name
Test status
Simulation time 10240094497 ps
CPU time 148.24 seconds
Started Oct 15 04:46:21 AM UTC 24
Finished Oct 15 04:48:52 AM UTC 24
Peak memory 289756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617455837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1617455837 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all_with_rand_reset.3656155790
Short name T12
Test name
Test status
Simulation time 1784171755 ps
CPU time 61.88 seconds
Started Oct 15 04:46:24 AM UTC 24
Finished Oct 15 04:47:28 AM UTC 24
Peak memory 268972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3656155790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_r
and_reset.3656155790 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.4227430103
Short name T10
Test name
Test status
Simulation time 8440830420 ps
CPU time 41.76 seconds
Started Oct 15 04:47:38 AM UTC 24
Finished Oct 15 04:48:21 AM UTC 24
Peak memory 278212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227430103 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.4227430103 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.97325086
Short name T129
Test name
Test status
Simulation time 1135085996 ps
CPU time 7.57 seconds
Started Oct 15 03:01:34 AM UTC 24
Finished Oct 15 03:01:43 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97325086 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.97325086 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.3216852034
Short name T48
Test name
Test status
Simulation time 51416317 ps
CPU time 2.67 seconds
Started Oct 15 04:51:00 AM UTC 24
Finished Oct 15 04:51:04 AM UTC 24
Peak memory 236380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216852034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.3216852034 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.3015674775
Short name T80
Test name
Test status
Simulation time 30360902410 ps
CPU time 196.71 seconds
Started Oct 15 04:48:45 AM UTC 24
Finished Oct 15 04:52:05 AM UTC 24
Peak memory 354924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015674775 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3015674775 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3797151337
Short name T111
Test name
Test status
Simulation time 49907248 ps
CPU time 3.62 seconds
Started Oct 15 03:01:51 AM UTC 24
Finished Oct 15 03:01:56 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797151337 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.3797
151337 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.3886162677
Short name T4
Test name
Test status
Simulation time 1927973851 ps
CPU time 19.39 seconds
Started Oct 15 04:46:23 AM UTC 24
Finished Oct 15 04:46:43 AM UTC 24
Peak memory 234492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886162677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3886162677 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_error.3957025413
Short name T42
Test name
Test status
Simulation time 7505877099 ps
CPU time 454.19 seconds
Started Oct 15 04:57:58 AM UTC 24
Finished Oct 15 05:05:38 AM UTC 24
Peak memory 404128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957025413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.3957025413 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.1990431306
Short name T3
Test name
Test status
Simulation time 79030694 ps
CPU time 1.55 seconds
Started Oct 15 04:46:23 AM UTC 24
Finished Oct 15 04:46:25 AM UTC 24
Peak memory 230080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990431306 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1990431306 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.248334404
Short name T22
Test name
Test status
Simulation time 82652415 ps
CPU time 2.27 seconds
Started Oct 15 04:47:30 AM UTC 24
Finished Oct 15 04:47:34 AM UTC 24
Peak memory 234312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248334404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.248334404 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.3915542570
Short name T132
Test name
Test status
Simulation time 16499410 ps
CPU time 1.3 seconds
Started Oct 15 03:01:26 AM UTC 24
Finished Oct 15 03:01:28 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915542570 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3915542570 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.781153724
Short name T47
Test name
Test status
Simulation time 50090604 ps
CPU time 1.85 seconds
Started Oct 15 04:49:10 AM UTC 24
Finished Oct 15 04:49:13 AM UTC 24
Peak memory 235904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781153724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.781153724 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.638853746
Short name T72
Test name
Test status
Simulation time 243396839 ps
CPU time 6.58 seconds
Started Oct 15 05:03:00 AM UTC 24
Finished Oct 15 05:03:07 AM UTC 24
Peak memory 244820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638853746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.638853746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.3189928868
Short name T52
Test name
Test status
Simulation time 36874028 ps
CPU time 1.78 seconds
Started Oct 15 04:46:23 AM UTC 24
Finished Oct 15 04:46:25 AM UTC 24
Peak memory 229800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189928868 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3189928868 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.2131893835
Short name T60
Test name
Test status
Simulation time 106404095 ps
CPU time 2.12 seconds
Started Oct 15 05:08:35 AM UTC 24
Finished Oct 15 05:08:38 AM UTC 24
Peak memory 234368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131893835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2131893835 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.1453686686
Short name T50
Test name
Test status
Simulation time 3379276170 ps
CPU time 40.51 seconds
Started Oct 15 04:46:18 AM UTC 24
Finished Oct 15 04:47:00 AM UTC 24
Peak memory 238360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453686686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.1453686686 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload_invalid.4246234702
Short name T18
Test name
Test status
Simulation time 588518434 ps
CPU time 9.39 seconds
Started Oct 15 04:49:52 AM UTC 24
Finished Oct 15 04:50:03 AM UTC 24
Peak memory 236928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246234702 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload_invalid.4246234702 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.1401490153
Short name T142
Test name
Test status
Simulation time 181678905 ps
CPU time 2.53 seconds
Started Oct 15 03:01:43 AM UTC 24
Finished Oct 15 03:01:46 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401490153 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.1401490153 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.1068637269
Short name T114
Test name
Test status
Simulation time 190107090 ps
CPU time 1.88 seconds
Started Oct 15 03:01:58 AM UTC 24
Finished Oct 15 03:02:01 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068637269 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.1068637269 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload_invalid.611062782
Short name T19
Test name
Test status
Simulation time 140684731 ps
CPU time 11.65 seconds
Started Oct 15 05:47:25 AM UTC 24
Finished Oct 15 05:47:38 AM UTC 24
Peak memory 238460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611062782 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload_invalid.611062782 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.561093059
Short name T65
Test name
Test status
Simulation time 43137749 ps
CPU time 2.25 seconds
Started Oct 15 05:07:19 AM UTC 24
Finished Oct 15 05:07:22 AM UTC 24
Peak memory 236364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561093059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.561093059 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.787980389
Short name T76
Test name
Test status
Simulation time 45282600 ps
CPU time 2.35 seconds
Started Oct 15 05:30:11 AM UTC 24
Finished Oct 15 05:30:14 AM UTC 24
Peak memory 236428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787980389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.787980389 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.703493434
Short name T68
Test name
Test status
Simulation time 44724141 ps
CPU time 2.18 seconds
Started Oct 15 05:53:11 AM UTC 24
Finished Oct 15 05:53:14 AM UTC 24
Peak memory 236424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703493434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.703493434 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.1119408164
Short name T53
Test name
Test status
Simulation time 17959599 ps
CPU time 1.15 seconds
Started Oct 15 04:46:25 AM UTC 24
Finished Oct 15 04:46:27 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119408164 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1119408164 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.2579819133
Short name T120
Test name
Test status
Simulation time 2236137637 ps
CPU time 275.21 seconds
Started Oct 15 04:46:29 AM UTC 24
Finished Oct 15 04:51:08 AM UTC 24
Peak memory 250476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579819133 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2579819133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.3034577189
Short name T167
Test name
Test status
Simulation time 107687676 ps
CPU time 4.99 seconds
Started Oct 15 03:02:04 AM UTC 24
Finished Oct 15 03:02:10 AM UTC 24
Peak memory 225800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034577189 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.3034577189 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.2636193322
Short name T181
Test name
Test status
Simulation time 5412727334 ps
CPU time 149.09 seconds
Started Oct 15 04:48:22 AM UTC 24
Finished Oct 15 04:50:54 AM UTC 24
Peak memory 268764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636193322 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2636193322 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.2793537459
Short name T159
Test name
Test status
Simulation time 16514101 ps
CPU time 1.03 seconds
Started Oct 15 03:02:11 AM UTC 24
Finished Oct 15 03:02:13 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793537459 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2793537459 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.3213737300
Short name T177
Test name
Test status
Simulation time 26101855475 ps
CPU time 282.05 seconds
Started Oct 15 04:46:19 AM UTC 24
Finished Oct 15 04:51:06 AM UTC 24
Peak memory 287244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213737300 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3213737300 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.2911366298
Short name T161
Test name
Test status
Simulation time 17793665922 ps
CPU time 321.12 seconds
Started Oct 15 05:03:31 AM UTC 24
Finished Oct 15 05:08:57 AM UTC 24
Peak memory 467504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911366298 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.2911366298 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_stress_all.600698040
Short name T92
Test name
Test status
Simulation time 104776023991 ps
CPU time 1982.73 seconds
Started Oct 15 05:13:04 AM UTC 24
Finished Oct 15 05:46:30 AM UTC 24
Peak memory 1352636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600698040 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.600698040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2999691672
Short name T106
Test name
Test status
Simulation time 45744711 ps
CPU time 1.75 seconds
Started Oct 15 03:01:21 AM UTC 24
Finished Oct 15 03:01:25 AM UTC 24
Peak memory 227468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999691672 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.2999691672 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all_with_rand_reset.1715837579
Short name T94
Test name
Test status
Simulation time 2376894882 ps
CPU time 66.3 seconds
Started Oct 15 04:53:51 AM UTC 24
Finished Oct 15 04:54:59 AM UTC 24
Peak memory 266936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1715837579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_r
and_reset.1715837579 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_error.3075027231
Short name T290
Test name
Test status
Simulation time 17549135112 ps
CPU time 285.96 seconds
Started Oct 15 05:01:12 AM UTC 24
Finished Oct 15 05:06:02 AM UTC 24
Peak memory 346724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075027231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3075027231 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.2478816053
Short name T169
Test name
Test status
Simulation time 371883837 ps
CPU time 5.29 seconds
Started Oct 15 03:02:19 AM UTC 24
Finished Oct 15 03:02:25 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478816053 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2478816053 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.87793741
Short name T166
Test name
Test status
Simulation time 414044852 ps
CPU time 4.5 seconds
Started Oct 15 03:01:51 AM UTC 24
Finished Oct 15 03:01:57 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87793741 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.87793741 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.3743666393
Short name T8
Test name
Test status
Simulation time 5146592693 ps
CPU time 17.9 seconds
Started Oct 15 04:46:21 AM UTC 24
Finished Oct 15 04:46:40 AM UTC 24
Peak memory 232180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743666393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3743666393 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.282755494
Short name T16
Test name
Test status
Simulation time 2513248484 ps
CPU time 17.45 seconds
Started Oct 15 04:46:26 AM UTC 24
Finished Oct 15 04:46:45 AM UTC 24
Peak memory 238144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282755494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.282755494 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.3747481063
Short name T14
Test name
Test status
Simulation time 23466494930 ps
CPU time 165.44 seconds
Started Oct 15 04:46:21 AM UTC 24
Finished Oct 15 04:49:09 AM UTC 24
Peak memory 346732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747481063 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3747481063 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_error.1945895808
Short name T319
Test name
Test status
Simulation time 12707465676 ps
CPU time 416.6 seconds
Started Oct 15 05:02:38 AM UTC 24
Finished Oct 15 05:09:41 AM UTC 24
Peak memory 551524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945895808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1945895808 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.2121686932
Short name T151
Test name
Test status
Simulation time 459680543 ps
CPU time 10.65 seconds
Started Oct 15 03:01:29 AM UTC 24
Finished Oct 15 03:01:41 AM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121686932 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2121686932 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.370306065
Short name T788
Test name
Test status
Simulation time 4016580526 ps
CPU time 28.56 seconds
Started Oct 15 03:01:28 AM UTC 24
Finished Oct 15 03:01:58 AM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370306065 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.370306065 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.3423644311
Short name T133
Test name
Test status
Simulation time 35050060 ps
CPU time 1.76 seconds
Started Oct 15 03:01:27 AM UTC 24
Finished Oct 15 03:01:30 AM UTC 24
Peak memory 223784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423644311 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3423644311 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2874886054
Short name T136
Test name
Test status
Simulation time 169543523 ps
CPU time 2.12 seconds
Started Oct 15 03:01:30 AM UTC 24
Finished Oct 15 03:01:34 AM UTC 24
Peak memory 227700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2874886054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_
rw_with_rand_reset.2874886054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.3414484998
Short name T176
Test name
Test status
Simulation time 27920524 ps
CPU time 1.65 seconds
Started Oct 15 03:01:27 AM UTC 24
Finished Oct 15 03:01:30 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414484998 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3414484998 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.1546671582
Short name T140
Test name
Test status
Simulation time 28229296 ps
CPU time 2.04 seconds
Started Oct 15 03:01:24 AM UTC 24
Finished Oct 15 03:01:27 AM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546671582 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.1546671582 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.503187286
Short name T770
Test name
Test status
Simulation time 14349140 ps
CPU time 1.2 seconds
Started Oct 15 03:01:24 AM UTC 24
Finished Oct 15 03:01:27 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503187286 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.503187286 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1558172077
Short name T150
Test name
Test status
Simulation time 73218638 ps
CPU time 2.59 seconds
Started Oct 15 03:01:30 AM UTC 24
Finished Oct 15 03:01:34 AM UTC 24
Peak memory 225644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558172077 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.1558172077 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.221677949
Short name T107
Test name
Test status
Simulation time 461764282 ps
CPU time 2.81 seconds
Started Oct 15 03:01:23 AM UTC 24
Finished Oct 15 03:01:27 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221677949 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.22167
7949 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.2882058403
Short name T135
Test name
Test status
Simulation time 295973174 ps
CPU time 4.82 seconds
Started Oct 15 03:01:24 AM UTC 24
Finished Oct 15 03:01:30 AM UTC 24
Peak memory 225952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882058403 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2882058403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.1241992183
Short name T128
Test name
Test status
Simulation time 267761635 ps
CPU time 6.75 seconds
Started Oct 15 03:01:25 AM UTC 24
Finished Oct 15 03:01:33 AM UTC 24
Peak memory 225644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241992183 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.1241992183 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.709063729
Short name T775
Test name
Test status
Simulation time 318835235 ps
CPU time 6.16 seconds
Started Oct 15 03:01:35 AM UTC 24
Finished Oct 15 03:01:43 AM UTC 24
Peak memory 225656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709063729 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.709063729 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.3488113706
Short name T787
Test name
Test status
Simulation time 1011604554 ps
CPU time 21.54 seconds
Started Oct 15 03:01:35 AM UTC 24
Finished Oct 15 03:01:58 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488113706 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3488113706 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.1273966385
Short name T772
Test name
Test status
Simulation time 78318406 ps
CPU time 1.44 seconds
Started Oct 15 03:01:35 AM UTC 24
Finished Oct 15 03:01:38 AM UTC 24
Peak memory 224100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273966385 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1273966385 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2398146749
Short name T138
Test name
Test status
Simulation time 72893428 ps
CPU time 3.44 seconds
Started Oct 15 03:01:38 AM UTC 24
Finished Oct 15 03:01:43 AM UTC 24
Peak memory 231788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2398146749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_
rw_with_rand_reset.2398146749 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.1576360923
Short name T773
Test name
Test status
Simulation time 37773927 ps
CPU time 1.36 seconds
Started Oct 15 03:01:35 AM UTC 24
Finished Oct 15 03:01:38 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576360923 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1576360923 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.3087260455
Short name T153
Test name
Test status
Simulation time 44106821 ps
CPU time 1.21 seconds
Started Oct 15 03:01:35 AM UTC 24
Finished Oct 15 03:01:37 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087260455 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3087260455 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.3852590723
Short name T141
Test name
Test status
Simulation time 227932039 ps
CPU time 1.7 seconds
Started Oct 15 03:01:32 AM UTC 24
Finished Oct 15 03:01:35 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852590723 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.3852590723 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.2588092789
Short name T771
Test name
Test status
Simulation time 10946723 ps
CPU time 1.14 seconds
Started Oct 15 03:01:32 AM UTC 24
Finished Oct 15 03:01:34 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588092789 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2588092789 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.4272529573
Short name T774
Test name
Test status
Simulation time 40842103 ps
CPU time 3.1 seconds
Started Oct 15 03:01:38 AM UTC 24
Finished Oct 15 03:01:42 AM UTC 24
Peak memory 225608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272529573 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.4272529573 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.902739564
Short name T109
Test name
Test status
Simulation time 43800189 ps
CPU time 1.38 seconds
Started Oct 15 03:01:31 AM UTC 24
Finished Oct 15 03:01:33 AM UTC 24
Peak memory 224076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902739564 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.902739564 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1207289609
Short name T108
Test name
Test status
Simulation time 71675412 ps
CPU time 2.48 seconds
Started Oct 15 03:01:31 AM UTC 24
Finished Oct 15 03:01:34 AM UTC 24
Peak memory 230200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207289609 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.1207
289609 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.1900964130
Short name T137
Test name
Test status
Simulation time 217594787 ps
CPU time 2.92 seconds
Started Oct 15 03:01:34 AM UTC 24
Finished Oct 15 03:01:38 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900964130 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.1900964130 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1583389524
Short name T839
Test name
Test status
Simulation time 23674829 ps
CPU time 1.9 seconds
Started Oct 15 03:02:20 AM UTC 24
Finished Oct 15 03:02:23 AM UTC 24
Peak memory 225864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1583389524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem
_rw_with_rand_reset.1583389524 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.2724011716
Short name T833
Test name
Test status
Simulation time 60569340 ps
CPU time 1.46 seconds
Started Oct 15 03:02:19 AM UTC 24
Finished Oct 15 03:02:21 AM UTC 24
Peak memory 223932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724011716 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2724011716 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.404948600
Short name T157
Test name
Test status
Simulation time 14859767 ps
CPU time 1.17 seconds
Started Oct 15 03:02:19 AM UTC 24
Finished Oct 15 03:02:21 AM UTC 24
Peak memory 223772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404948600 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.404948600 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1769823172
Short name T841
Test name
Test status
Simulation time 188748925 ps
CPU time 2.64 seconds
Started Oct 15 03:02:20 AM UTC 24
Finished Oct 15 03:02:23 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769823172 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.1769823172 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3028213956
Short name T830
Test name
Test status
Simulation time 86298992 ps
CPU time 1.67 seconds
Started Oct 15 03:02:17 AM UTC 24
Finished Oct 15 03:02:20 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028213956 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.3028213956 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1262372983
Short name T837
Test name
Test status
Simulation time 157921214 ps
CPU time 2.83 seconds
Started Oct 15 03:02:19 AM UTC 24
Finished Oct 15 03:02:22 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262372983 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.126
2372983 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.292969325
Short name T836
Test name
Test status
Simulation time 33877482 ps
CPU time 2.21 seconds
Started Oct 15 03:02:19 AM UTC 24
Finished Oct 15 03:02:22 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292969325 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.292969325 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3909156568
Short name T850
Test name
Test status
Simulation time 75843592 ps
CPU time 2.77 seconds
Started Oct 15 03:02:22 AM UTC 24
Finished Oct 15 03:02:26 AM UTC 24
Peak memory 231860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3909156568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem
_rw_with_rand_reset.3909156568 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.1653764122
Short name T842
Test name
Test status
Simulation time 84336710 ps
CPU time 1.56 seconds
Started Oct 15 03:02:21 AM UTC 24
Finished Oct 15 03:02:24 AM UTC 24
Peak memory 224100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653764122 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.1653764122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.1474557037
Short name T840
Test name
Test status
Simulation time 15041543 ps
CPU time 0.96 seconds
Started Oct 15 03:02:21 AM UTC 24
Finished Oct 15 03:02:23 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474557037 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1474557037 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.93658871
Short name T843
Test name
Test status
Simulation time 27466044 ps
CPU time 1.81 seconds
Started Oct 15 03:02:21 AM UTC 24
Finished Oct 15 03:02:24 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93658871 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.93658871 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.3176289796
Short name T838
Test name
Test status
Simulation time 73657560 ps
CPU time 1.49 seconds
Started Oct 15 03:02:20 AM UTC 24
Finished Oct 15 03:02:22 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176289796 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.3176289796 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4265018012
Short name T847
Test name
Test status
Simulation time 65953253 ps
CPU time 3.06 seconds
Started Oct 15 03:02:21 AM UTC 24
Finished Oct 15 03:02:25 AM UTC 24
Peak memory 230224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265018012 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.426
5018012 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.466141772
Short name T844
Test name
Test status
Simulation time 111329130 ps
CPU time 2.1 seconds
Started Oct 15 03:02:21 AM UTC 24
Finished Oct 15 03:02:24 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466141772 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.466141772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.3900071552
Short name T849
Test name
Test status
Simulation time 153422861 ps
CPU time 3.99 seconds
Started Oct 15 03:02:21 AM UTC 24
Finished Oct 15 03:02:26 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900071552 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3900071552 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2142298460
Short name T853
Test name
Test status
Simulation time 76163624 ps
CPU time 1.98 seconds
Started Oct 15 03:02:24 AM UTC 24
Finished Oct 15 03:02:27 AM UTC 24
Peak memory 225864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2142298460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem
_rw_with_rand_reset.2142298460 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.344591229
Short name T851
Test name
Test status
Simulation time 31755795 ps
CPU time 1.55 seconds
Started Oct 15 03:02:24 AM UTC 24
Finished Oct 15 03:02:26 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344591229 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.344591229 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.3737895972
Short name T845
Test name
Test status
Simulation time 22326990 ps
CPU time 0.98 seconds
Started Oct 15 03:02:23 AM UTC 24
Finished Oct 15 03:02:25 AM UTC 24
Peak memory 223816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737895972 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3737895972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3249553109
Short name T858
Test name
Test status
Simulation time 334250424 ps
CPU time 2.8 seconds
Started Oct 15 03:02:24 AM UTC 24
Finished Oct 15 03:02:28 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249553109 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.3249553109 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4082460722
Short name T846
Test name
Test status
Simulation time 24355192 ps
CPU time 1.52 seconds
Started Oct 15 03:02:22 AM UTC 24
Finished Oct 15 03:02:25 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082460722 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.4082460722 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.49631184
Short name T848
Test name
Test status
Simulation time 187267682 ps
CPU time 1.85 seconds
Started Oct 15 03:02:23 AM UTC 24
Finished Oct 15 03:02:25 AM UTC 24
Peak memory 230128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49631184 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.49631
184 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.1202615488
Short name T856
Test name
Test status
Simulation time 491441294 ps
CPU time 3.89 seconds
Started Oct 15 03:02:23 AM UTC 24
Finished Oct 15 03:02:27 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202615488 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1202615488 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1868310039
Short name T866
Test name
Test status
Simulation time 461258628 ps
CPU time 7.04 seconds
Started Oct 15 03:02:23 AM UTC 24
Finished Oct 15 03:02:31 AM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868310039 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1868310039 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1763408737
Short name T863
Test name
Test status
Simulation time 104506141 ps
CPU time 2.36 seconds
Started Oct 15 03:02:26 AM UTC 24
Finished Oct 15 03:02:30 AM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1763408737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem
_rw_with_rand_reset.1763408737 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.3549450604
Short name T857
Test name
Test status
Simulation time 128142276 ps
CPU time 1.26 seconds
Started Oct 15 03:02:25 AM UTC 24
Finished Oct 15 03:02:27 AM UTC 24
Peak memory 224076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549450604 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.3549450604 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.3873834914
Short name T855
Test name
Test status
Simulation time 18914928 ps
CPU time 1.11 seconds
Started Oct 15 03:02:25 AM UTC 24
Finished Oct 15 03:02:27 AM UTC 24
Peak memory 224088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873834914 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3873834914 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3023271660
Short name T860
Test name
Test status
Simulation time 87054361 ps
CPU time 2.11 seconds
Started Oct 15 03:02:25 AM UTC 24
Finished Oct 15 03:02:28 AM UTC 24
Peak memory 225880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023271660 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.3023271660 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3279707775
Short name T852
Test name
Test status
Simulation time 61457750 ps
CPU time 1.63 seconds
Started Oct 15 03:02:24 AM UTC 24
Finished Oct 15 03:02:27 AM UTC 24
Peak memory 225924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279707775 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.3279707775 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.435692426
Short name T854
Test name
Test status
Simulation time 98795159 ps
CPU time 2.09 seconds
Started Oct 15 03:02:24 AM UTC 24
Finished Oct 15 03:02:27 AM UTC 24
Peak memory 230108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435692426 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.4356
92426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.358453563
Short name T859
Test name
Test status
Simulation time 94393320 ps
CPU time 1.91 seconds
Started Oct 15 03:02:25 AM UTC 24
Finished Oct 15 03:02:28 AM UTC 24
Peak memory 223744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358453563 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.358453563 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3455821507
Short name T173
Test name
Test status
Simulation time 155698079 ps
CPU time 3.79 seconds
Started Oct 15 03:02:25 AM UTC 24
Finished Oct 15 03:02:30 AM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455821507 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3455821507 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3244952632
Short name T870
Test name
Test status
Simulation time 51925651 ps
CPU time 2.71 seconds
Started Oct 15 03:02:28 AM UTC 24
Finished Oct 15 03:02:32 AM UTC 24
Peak memory 229940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3244952632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem
_rw_with_rand_reset.3244952632 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.915383575
Short name T864
Test name
Test status
Simulation time 25514350 ps
CPU time 1.43 seconds
Started Oct 15 03:02:28 AM UTC 24
Finished Oct 15 03:02:30 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915383575 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.915383575 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.1292885664
Short name T862
Test name
Test status
Simulation time 32416490 ps
CPU time 0.93 seconds
Started Oct 15 03:02:28 AM UTC 24
Finished Oct 15 03:02:30 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292885664 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1292885664 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3277847941
Short name T871
Test name
Test status
Simulation time 198607646 ps
CPU time 3.2 seconds
Started Oct 15 03:02:28 AM UTC 24
Finished Oct 15 03:02:32 AM UTC 24
Peak memory 225656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277847941 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.3277847941 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2825155651
Short name T113
Test name
Test status
Simulation time 41437872 ps
CPU time 1.27 seconds
Started Oct 15 03:02:27 AM UTC 24
Finished Oct 15 03:02:29 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825155651 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.2825155651 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.3469827005
Short name T861
Test name
Test status
Simulation time 219538414 ps
CPU time 1.89 seconds
Started Oct 15 03:02:27 AM UTC 24
Finished Oct 15 03:02:29 AM UTC 24
Peak memory 230304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469827005 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.346
9827005 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1465450270
Short name T868
Test name
Test status
Simulation time 298497535 ps
CPU time 3.52 seconds
Started Oct 15 03:02:27 AM UTC 24
Finished Oct 15 03:02:31 AM UTC 24
Peak memory 226040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465450270 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1465450270 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.3499988520
Short name T873
Test name
Test status
Simulation time 59702524 ps
CPU time 3.32 seconds
Started Oct 15 03:02:28 AM UTC 24
Finished Oct 15 03:02:32 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499988520 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3499988520 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4246551859
Short name T878
Test name
Test status
Simulation time 87105760 ps
CPU time 2.04 seconds
Started Oct 15 03:02:30 AM UTC 24
Finished Oct 15 03:02:33 AM UTC 24
Peak memory 227700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4246551859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem
_rw_with_rand_reset.4246551859 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2646102283
Short name T869
Test name
Test status
Simulation time 50559309 ps
CPU time 1.22 seconds
Started Oct 15 03:02:29 AM UTC 24
Finished Oct 15 03:02:31 AM UTC 24
Peak memory 223932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646102283 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2646102283 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.2704245355
Short name T867
Test name
Test status
Simulation time 37579417 ps
CPU time 0.83 seconds
Started Oct 15 03:02:29 AM UTC 24
Finished Oct 15 03:02:31 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704245355 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2704245355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3247413356
Short name T874
Test name
Test status
Simulation time 122590598 ps
CPU time 1.94 seconds
Started Oct 15 03:02:29 AM UTC 24
Finished Oct 15 03:02:32 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247413356 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.3247413356 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2439043051
Short name T865
Test name
Test status
Simulation time 173995796 ps
CPU time 1.56 seconds
Started Oct 15 03:02:28 AM UTC 24
Finished Oct 15 03:02:30 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439043051 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.2439043051 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.571285530
Short name T117
Test name
Test status
Simulation time 52055672 ps
CPU time 2.62 seconds
Started Oct 15 03:02:28 AM UTC 24
Finished Oct 15 03:02:31 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571285530 -assert
nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.5712
85530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3649903707
Short name T875
Test name
Test status
Simulation time 135084685 ps
CPU time 2.5 seconds
Started Oct 15 03:02:29 AM UTC 24
Finished Oct 15 03:02:33 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649903707 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3649903707 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.378490730
Short name T168
Test name
Test status
Simulation time 1030696996 ps
CPU time 5.94 seconds
Started Oct 15 03:02:29 AM UTC 24
Finished Oct 15 03:02:36 AM UTC 24
Peak memory 225660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378490730 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.378490730 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1587912403
Short name T885
Test name
Test status
Simulation time 41879575 ps
CPU time 2.49 seconds
Started Oct 15 03:02:32 AM UTC 24
Finished Oct 15 03:02:35 AM UTC 24
Peak memory 227700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1587912403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem
_rw_with_rand_reset.1587912403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.1324848831
Short name T881
Test name
Test status
Simulation time 68962248 ps
CPU time 1.76 seconds
Started Oct 15 03:02:32 AM UTC 24
Finished Oct 15 03:02:34 AM UTC 24
Peak memory 224100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324848831 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1324848831 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.198277144
Short name T877
Test name
Test status
Simulation time 51218530 ps
CPU time 1.1 seconds
Started Oct 15 03:02:31 AM UTC 24
Finished Oct 15 03:02:33 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198277144 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.198277144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1186017932
Short name T880
Test name
Test status
Simulation time 79361857 ps
CPU time 1.7 seconds
Started Oct 15 03:02:32 AM UTC 24
Finished Oct 15 03:02:34 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186017932 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.1186017932 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4089555758
Short name T876
Test name
Test status
Simulation time 55734160 ps
CPU time 1.4 seconds
Started Oct 15 03:02:30 AM UTC 24
Finished Oct 15 03:02:33 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089555758 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.4089555758 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.3421177083
Short name T883
Test name
Test status
Simulation time 246516855 ps
CPU time 3.65 seconds
Started Oct 15 03:02:30 AM UTC 24
Finished Oct 15 03:02:35 AM UTC 24
Peak memory 230304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421177083 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.342
1177083 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.1004030490
Short name T879
Test name
Test status
Simulation time 108995675 ps
CPU time 2.81 seconds
Started Oct 15 03:02:30 AM UTC 24
Finished Oct 15 03:02:34 AM UTC 24
Peak memory 225784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004030490 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1004030490 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1915819402
Short name T175
Test name
Test status
Simulation time 365684044 ps
CPU time 5.45 seconds
Started Oct 15 03:02:31 AM UTC 24
Finished Oct 15 03:02:37 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915819402 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1915819402 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2200460664
Short name T890
Test name
Test status
Simulation time 141023018 ps
CPU time 2.68 seconds
Started Oct 15 03:02:33 AM UTC 24
Finished Oct 15 03:02:37 AM UTC 24
Peak memory 231860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2200460664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem
_rw_with_rand_reset.2200460664 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3129694802
Short name T887
Test name
Test status
Simulation time 59437284 ps
CPU time 1.66 seconds
Started Oct 15 03:02:33 AM UTC 24
Finished Oct 15 03:02:36 AM UTC 24
Peak memory 224100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129694802 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3129694802 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.2034193294
Short name T834
Test name
Test status
Simulation time 23449112 ps
CPU time 1.22 seconds
Started Oct 15 03:02:33 AM UTC 24
Finished Oct 15 03:02:35 AM UTC 24
Peak memory 223312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034193294 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2034193294 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.37731399
Short name T888
Test name
Test status
Simulation time 103547911 ps
CPU time 2.3 seconds
Started Oct 15 03:02:33 AM UTC 24
Finished Oct 15 03:02:36 AM UTC 24
Peak memory 225656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37731399 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.37731399 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2342494574
Short name T882
Test name
Test status
Simulation time 95163620 ps
CPU time 1.86 seconds
Started Oct 15 03:02:32 AM UTC 24
Finished Oct 15 03:02:35 AM UTC 24
Peak memory 228288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342494574 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2342494574 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.3650238631
Short name T884
Test name
Test status
Simulation time 630903978 ps
CPU time 2.36 seconds
Started Oct 15 03:02:32 AM UTC 24
Finished Oct 15 03:02:35 AM UTC 24
Peak memory 225680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650238631 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.365
0238631 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2654484056
Short name T886
Test name
Test status
Simulation time 138353002 ps
CPU time 2.5 seconds
Started Oct 15 03:02:32 AM UTC 24
Finished Oct 15 03:02:35 AM UTC 24
Peak memory 225784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654484056 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2654484056 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1242308028
Short name T903
Test name
Test status
Simulation time 747039293 ps
CPU time 6.14 seconds
Started Oct 15 03:02:33 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 225064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242308028 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1242308028 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.232086968
Short name T899
Test name
Test status
Simulation time 264285431 ps
CPU time 2.85 seconds
Started Oct 15 03:02:36 AM UTC 24
Finished Oct 15 03:02:39 AM UTC 24
Peak memory 231780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=232086968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_
rw_with_rand_reset.232086968 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.3178605717
Short name T892
Test name
Test status
Simulation time 12636854 ps
CPU time 1.26 seconds
Started Oct 15 03:02:36 AM UTC 24
Finished Oct 15 03:02:38 AM UTC 24
Peak memory 223932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178605717 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3178605717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.2561057940
Short name T893
Test name
Test status
Simulation time 77538565 ps
CPU time 1.33 seconds
Started Oct 15 03:02:35 AM UTC 24
Finished Oct 15 03:02:38 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561057940 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2561057940 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2391883915
Short name T896
Test name
Test status
Simulation time 77768523 ps
CPU time 2.53 seconds
Started Oct 15 03:02:36 AM UTC 24
Finished Oct 15 03:02:39 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391883915 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.2391883915 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.3917998562
Short name T872
Test name
Test status
Simulation time 29094638 ps
CPU time 1.32 seconds
Started Oct 15 03:02:33 AM UTC 24
Finished Oct 15 03:02:35 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917998562 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.3917998562 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1759692566
Short name T891
Test name
Test status
Simulation time 129241283 ps
CPU time 2.93 seconds
Started Oct 15 03:02:33 AM UTC 24
Finished Oct 15 03:02:37 AM UTC 24
Peak memory 230032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759692566 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.175
9692566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.3130077654
Short name T889
Test name
Test status
Simulation time 356560500 ps
CPU time 2.12 seconds
Started Oct 15 03:02:33 AM UTC 24
Finished Oct 15 03:02:36 AM UTC 24
Peak memory 225804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130077654 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3130077654 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.2146051762
Short name T171
Test name
Test status
Simulation time 197110880 ps
CPU time 2.72 seconds
Started Oct 15 03:02:34 AM UTC 24
Finished Oct 15 03:02:38 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146051762 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2146051762 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1215561327
Short name T909
Test name
Test status
Simulation time 41550896 ps
CPU time 2.47 seconds
Started Oct 15 03:02:37 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 227804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1215561327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem
_rw_with_rand_reset.1215561327 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.2826291006
Short name T897
Test name
Test status
Simulation time 51069805 ps
CPU time 1.25 seconds
Started Oct 15 03:02:37 AM UTC 24
Finished Oct 15 03:02:39 AM UTC 24
Peak memory 223920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826291006 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2826291006 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.1294476827
Short name T895
Test name
Test status
Simulation time 24003731 ps
CPU time 0.86 seconds
Started Oct 15 03:02:37 AM UTC 24
Finished Oct 15 03:02:39 AM UTC 24
Peak memory 223816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294476827 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.1294476827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.753973630
Short name T901
Test name
Test status
Simulation time 208833622 ps
CPU time 2 seconds
Started Oct 15 03:02:37 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753973630 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.753973630 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3666349777
Short name T894
Test name
Test status
Simulation time 68278649 ps
CPU time 1.41 seconds
Started Oct 15 03:02:36 AM UTC 24
Finished Oct 15 03:02:38 AM UTC 24
Peak memory 228324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666349777 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.3666349777 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2440796844
Short name T900
Test name
Test status
Simulation time 56904066 ps
CPU time 2.24 seconds
Started Oct 15 03:02:37 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 230332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440796844 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.244
0796844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.723426995
Short name T904
Test name
Test status
Simulation time 26468757 ps
CPU time 2.52 seconds
Started Oct 15 03:02:37 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723426995 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.723426995 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.1672785029
Short name T911
Test name
Test status
Simulation time 280580914 ps
CPU time 3.74 seconds
Started Oct 15 03:02:37 AM UTC 24
Finished Oct 15 03:02:42 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672785029 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1672785029 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.3374642483
Short name T789
Test name
Test status
Simulation time 564051345 ps
CPU time 11.27 seconds
Started Oct 15 03:01:47 AM UTC 24
Finished Oct 15 03:01:59 AM UTC 24
Peak memory 225652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374642483 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.3374642483 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1448435267
Short name T791
Test name
Test status
Simulation time 1447436410 ps
CPU time 15.14 seconds
Started Oct 15 03:01:45 AM UTC 24
Finished Oct 15 03:02:01 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448435267 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1448435267 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1727168320
Short name T778
Test name
Test status
Simulation time 150869844 ps
CPU time 1.56 seconds
Started Oct 15 03:01:44 AM UTC 24
Finished Oct 15 03:01:46 AM UTC 24
Peak memory 224100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727168320 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1727168320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.968503373
Short name T782
Test name
Test status
Simulation time 688669846 ps
CPU time 2.52 seconds
Started Oct 15 03:01:47 AM UTC 24
Finished Oct 15 03:01:51 AM UTC 24
Peak memory 229732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=968503373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_r
w_with_rand_reset.968503373 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3947824566
Short name T777
Test name
Test status
Simulation time 25609326 ps
CPU time 1.43 seconds
Started Oct 15 03:01:44 AM UTC 24
Finished Oct 15 03:01:46 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947824566 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3947824566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.4013368224
Short name T156
Test name
Test status
Simulation time 13568168 ps
CPU time 1.22 seconds
Started Oct 15 03:01:44 AM UTC 24
Finished Oct 15 03:01:46 AM UTC 24
Peak memory 223776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013368224 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.4013368224 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.307557406
Short name T776
Test name
Test status
Simulation time 14976491 ps
CPU time 1.16 seconds
Started Oct 15 03:01:41 AM UTC 24
Finished Oct 15 03:01:44 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307557406 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.307557406 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.469091980
Short name T780
Test name
Test status
Simulation time 25777547 ps
CPU time 2.03 seconds
Started Oct 15 03:01:47 AM UTC 24
Finished Oct 15 03:01:50 AM UTC 24
Peak memory 225844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469091980 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.469091980 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.249349500
Short name T118
Test name
Test status
Simulation time 85624682 ps
CPU time 1.52 seconds
Started Oct 15 03:01:38 AM UTC 24
Finished Oct 15 03:01:41 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249349500 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.249349500 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3400043131
Short name T110
Test name
Test status
Simulation time 71213585 ps
CPU time 2.34 seconds
Started Oct 15 03:01:39 AM UTC 24
Finished Oct 15 03:01:43 AM UTC 24
Peak memory 226240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400043131 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.3400
043131 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.1276867595
Short name T781
Test name
Test status
Simulation time 64160056 ps
CPU time 5.47 seconds
Started Oct 15 03:01:44 AM UTC 24
Finished Oct 15 03:01:50 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276867595 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1276867595 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2087603879
Short name T130
Test name
Test status
Simulation time 244177931 ps
CPU time 7.43 seconds
Started Oct 15 03:01:44 AM UTC 24
Finished Oct 15 03:01:52 AM UTC 24
Peak memory 225588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087603879 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.2087603879 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.4289629856
Short name T898
Test name
Test status
Simulation time 27878825 ps
CPU time 1.03 seconds
Started Oct 15 03:02:37 AM UTC 24
Finished Oct 15 03:02:39 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289629856 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.4289629856 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2488257279
Short name T902
Test name
Test status
Simulation time 68667727 ps
CPU time 0.9 seconds
Started Oct 15 03:02:38 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488257279 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2488257279 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2945055272
Short name T906
Test name
Test status
Simulation time 31673200 ps
CPU time 1.21 seconds
Started Oct 15 03:02:38 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945055272 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2945055272 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.2770177297
Short name T908
Test name
Test status
Simulation time 16307699 ps
CPU time 1.15 seconds
Started Oct 15 03:02:38 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770177297 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.2770177297 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3828111001
Short name T907
Test name
Test status
Simulation time 34964209 ps
CPU time 1.06 seconds
Started Oct 15 03:02:38 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828111001 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3828111001 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.1456729479
Short name T905
Test name
Test status
Simulation time 27891457 ps
CPU time 1.03 seconds
Started Oct 15 03:02:38 AM UTC 24
Finished Oct 15 03:02:40 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456729479 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1456729479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.1195713492
Short name T910
Test name
Test status
Simulation time 14801225 ps
CPU time 1.15 seconds
Started Oct 15 03:02:38 AM UTC 24
Finished Oct 15 03:02:41 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195713492 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1195713492 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.2647652163
Short name T912
Test name
Test status
Simulation time 57368891 ps
CPU time 1.07 seconds
Started Oct 15 03:02:40 AM UTC 24
Finished Oct 15 03:02:42 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647652163 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2647652163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.2840946968
Short name T913
Test name
Test status
Simulation time 36589480 ps
CPU time 1.12 seconds
Started Oct 15 03:02:40 AM UTC 24
Finished Oct 15 03:02:42 AM UTC 24
Peak memory 223816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840946968 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2840946968 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.413354969
Short name T915
Test name
Test status
Simulation time 37170727 ps
CPU time 1.15 seconds
Started Oct 15 03:02:40 AM UTC 24
Finished Oct 15 03:02:42 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413354969 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.413354969 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.3048183835
Short name T795
Test name
Test status
Simulation time 293745031 ps
CPU time 6.04 seconds
Started Oct 15 03:01:56 AM UTC 24
Finished Oct 15 03:02:03 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048183835 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3048183835 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.2791380631
Short name T799
Test name
Test status
Simulation time 603351812 ps
CPU time 9.62 seconds
Started Oct 15 03:01:55 AM UTC 24
Finished Oct 15 03:02:05 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791380631 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2791380631 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.3197684821
Short name T786
Test name
Test status
Simulation time 102046559 ps
CPU time 1.76 seconds
Started Oct 15 03:01:55 AM UTC 24
Finished Oct 15 03:01:57 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197684821 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3197684821 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.812328651
Short name T793
Test name
Test status
Simulation time 1275908169 ps
CPU time 3.9 seconds
Started Oct 15 03:01:57 AM UTC 24
Finished Oct 15 03:02:02 AM UTC 24
Peak memory 231784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=812328651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_r
w_with_rand_reset.812328651 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.1730699489
Short name T785
Test name
Test status
Simulation time 60714162 ps
CPU time 1.51 seconds
Started Oct 15 03:01:55 AM UTC 24
Finished Oct 15 03:01:57 AM UTC 24
Peak memory 224120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730699489 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1730699489 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.3425753877
Short name T154
Test name
Test status
Simulation time 19337148 ps
CPU time 1.27 seconds
Started Oct 15 03:01:53 AM UTC 24
Finished Oct 15 03:01:55 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425753877 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3425753877 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.1291234196
Short name T143
Test name
Test status
Simulation time 112373494 ps
CPU time 1.84 seconds
Started Oct 15 03:01:51 AM UTC 24
Finished Oct 15 03:01:54 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291234196 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.1291234196 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.312203691
Short name T783
Test name
Test status
Simulation time 12770429 ps
CPU time 1.21 seconds
Started Oct 15 03:01:51 AM UTC 24
Finished Oct 15 03:01:53 AM UTC 24
Peak memory 223768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312203691 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.312203691 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.4284778880
Short name T792
Test name
Test status
Simulation time 116001458 ps
CPU time 3.54 seconds
Started Oct 15 03:01:57 AM UTC 24
Finished Oct 15 03:02:02 AM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284778880 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.4284778880 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.215598754
Short name T779
Test name
Test status
Simulation time 62152648 ps
CPU time 1.83 seconds
Started Oct 15 03:01:47 AM UTC 24
Finished Oct 15 03:01:50 AM UTC 24
Peak memory 223884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215598754 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.215598754 +enable_masking=1 +
sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.1747841362
Short name T784
Test name
Test status
Simulation time 157527867 ps
CPU time 4.57 seconds
Started Oct 15 03:01:51 AM UTC 24
Finished Oct 15 03:01:57 AM UTC 24
Peak memory 226004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747841362 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1747841362 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.1916539579
Short name T917
Test name
Test status
Simulation time 15199134 ps
CPU time 1.21 seconds
Started Oct 15 03:02:40 AM UTC 24
Finished Oct 15 03:02:42 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916539579 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1916539579 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.216471597
Short name T916
Test name
Test status
Simulation time 15117651 ps
CPU time 1.05 seconds
Started Oct 15 03:02:40 AM UTC 24
Finished Oct 15 03:02:42 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216471597 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.216471597 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.348657273
Short name T914
Test name
Test status
Simulation time 56924970 ps
CPU time 0.92 seconds
Started Oct 15 03:02:40 AM UTC 24
Finished Oct 15 03:02:42 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348657273 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.348657273 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3214363019
Short name T919
Test name
Test status
Simulation time 122623074 ps
CPU time 1 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214363019 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3214363019 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.461886535
Short name T920
Test name
Test status
Simulation time 31342798 ps
CPU time 1.1 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 224072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461886535 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.461886535 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.1267545206
Short name T922
Test name
Test status
Simulation time 77467326 ps
CPU time 1.16 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267545206 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.1267545206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.2367217956
Short name T923
Test name
Test status
Simulation time 19671215 ps
CPU time 1.27 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367217956 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2367217956 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.1236111167
Short name T918
Test name
Test status
Simulation time 29217381 ps
CPU time 0.88 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236111167 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1236111167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.4058785812
Short name T926
Test name
Test status
Simulation time 17811167 ps
CPU time 1.27 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058785812 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.4058785812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.1699415179
Short name T924
Test name
Test status
Simulation time 83266719 ps
CPU time 1.08 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699415179 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1699415179 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.808479953
Short name T802
Test name
Test status
Simulation time 327545985 ps
CPU time 4.33 seconds
Started Oct 15 03:02:02 AM UTC 24
Finished Oct 15 03:02:07 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808479953 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.808479953 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.3291192754
Short name T831
Test name
Test status
Simulation time 5637247618 ps
CPU time 17.25 seconds
Started Oct 15 03:02:02 AM UTC 24
Finished Oct 15 03:02:20 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291192754 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3291192754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.797667564
Short name T796
Test name
Test status
Simulation time 56251625 ps
CPU time 1.82 seconds
Started Oct 15 03:02:01 AM UTC 24
Finished Oct 15 03:02:03 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797667564 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.797667564 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.666862927
Short name T801
Test name
Test status
Simulation time 47558202 ps
CPU time 2.37 seconds
Started Oct 15 03:02:03 AM UTC 24
Finished Oct 15 03:02:06 AM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=666862927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_r
w_with_rand_reset.666862927 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.327896307
Short name T797
Test name
Test status
Simulation time 14464298 ps
CPU time 1.32 seconds
Started Oct 15 03:02:02 AM UTC 24
Finished Oct 15 03:02:04 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327896307 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.327896307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.19831980
Short name T158
Test name
Test status
Simulation time 74926907 ps
CPU time 1.06 seconds
Started Oct 15 03:01:59 AM UTC 24
Finished Oct 15 03:02:01 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19831980 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.19831980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.2260548422
Short name T144
Test name
Test status
Simulation time 58801401 ps
CPU time 2.16 seconds
Started Oct 15 03:01:58 AM UTC 24
Finished Oct 15 03:02:01 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260548422 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.2260548422 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3981178331
Short name T790
Test name
Test status
Simulation time 22393650 ps
CPU time 1.26 seconds
Started Oct 15 03:01:58 AM UTC 24
Finished Oct 15 03:02:01 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981178331 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3981178331 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2086704162
Short name T805
Test name
Test status
Simulation time 418301322 ps
CPU time 4.13 seconds
Started Oct 15 03:02:03 AM UTC 24
Finished Oct 15 03:02:08 AM UTC 24
Peak memory 225652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086704162 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.2086704162 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.4252900433
Short name T794
Test name
Test status
Simulation time 54664350 ps
CPU time 2.81 seconds
Started Oct 15 03:01:58 AM UTC 24
Finished Oct 15 03:02:02 AM UTC 24
Peak memory 226044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252900433 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.4252
900433 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.2933208030
Short name T798
Test name
Test status
Simulation time 117352469 ps
CPU time 4.59 seconds
Started Oct 15 03:01:59 AM UTC 24
Finished Oct 15 03:02:05 AM UTC 24
Peak memory 225892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933208030 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.2933208030 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.4107470159
Short name T172
Test name
Test status
Simulation time 749697800 ps
CPU time 6.58 seconds
Started Oct 15 03:01:59 AM UTC 24
Finished Oct 15 03:02:07 AM UTC 24
Peak memory 225784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107470159 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.4107470159 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2356165052
Short name T925
Test name
Test status
Simulation time 18950637 ps
CPU time 1.11 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356165052 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2356165052 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.3468930699
Short name T921
Test name
Test status
Simulation time 64922506 ps
CPU time 0.85 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468930699 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3468930699 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.106087446
Short name T927
Test name
Test status
Simulation time 23158905 ps
CPU time 1.05 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106087446 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.106087446 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.772192207
Short name T928
Test name
Test status
Simulation time 38302201 ps
CPU time 1.2 seconds
Started Oct 15 03:02:41 AM UTC 24
Finished Oct 15 03:02:43 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772192207 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.772192207 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.2552540236
Short name T934
Test name
Test status
Simulation time 14342919 ps
CPU time 1.22 seconds
Started Oct 15 03:02:42 AM UTC 24
Finished Oct 15 03:02:45 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552540236 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2552540236 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.3525219608
Short name T929
Test name
Test status
Simulation time 23937228 ps
CPU time 0.99 seconds
Started Oct 15 03:02:42 AM UTC 24
Finished Oct 15 03:02:44 AM UTC 24
Peak memory 223816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525219608 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3525219608 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.2183144874
Short name T931
Test name
Test status
Simulation time 22627291 ps
CPU time 1.11 seconds
Started Oct 15 03:02:42 AM UTC 24
Finished Oct 15 03:02:45 AM UTC 24
Peak memory 224116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183144874 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2183144874 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.3077305621
Short name T930
Test name
Test status
Simulation time 47037516 ps
CPU time 0.99 seconds
Started Oct 15 03:02:42 AM UTC 24
Finished Oct 15 03:02:44 AM UTC 24
Peak memory 224056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077305621 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3077305621 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.273700863
Short name T933
Test name
Test status
Simulation time 20946132 ps
CPU time 1.19 seconds
Started Oct 15 03:02:42 AM UTC 24
Finished Oct 15 03:02:45 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273700863 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.273700863 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.3053542610
Short name T932
Test name
Test status
Simulation time 19649353 ps
CPU time 1.06 seconds
Started Oct 15 03:02:43 AM UTC 24
Finished Oct 15 03:02:45 AM UTC 24
Peak memory 223820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053542610 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3053542610 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3297604768
Short name T809
Test name
Test status
Simulation time 481821372 ps
CPU time 3.92 seconds
Started Oct 15 03:02:06 AM UTC 24
Finished Oct 15 03:02:11 AM UTC 24
Peak memory 231984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3297604768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_
rw_with_rand_reset.3297604768 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.500136035
Short name T803
Test name
Test status
Simulation time 24045101 ps
CPU time 1.41 seconds
Started Oct 15 03:02:05 AM UTC 24
Finished Oct 15 03:02:08 AM UTC 24
Peak memory 224108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500136035 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.500136035 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.2546799221
Short name T155
Test name
Test status
Simulation time 21796102 ps
CPU time 1.19 seconds
Started Oct 15 03:02:04 AM UTC 24
Finished Oct 15 03:02:06 AM UTC 24
Peak memory 224104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546799221 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2546799221 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2472853553
Short name T807
Test name
Test status
Simulation time 64568267 ps
CPU time 2.6 seconds
Started Oct 15 03:02:06 AM UTC 24
Finished Oct 15 03:02:10 AM UTC 24
Peak memory 225848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472853553 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.2472853553 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2173923194
Short name T800
Test name
Test status
Simulation time 79267565 ps
CPU time 1.79 seconds
Started Oct 15 03:02:03 AM UTC 24
Finished Oct 15 03:02:06 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173923194 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.2173923194 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.2035236222
Short name T804
Test name
Test status
Simulation time 236065695 ps
CPU time 3.62 seconds
Started Oct 15 03:02:03 AM UTC 24
Finished Oct 15 03:02:08 AM UTC 24
Peak memory 230336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035236222 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.2035
236222 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.3168665366
Short name T806
Test name
Test status
Simulation time 154361515 ps
CPU time 5.31 seconds
Started Oct 15 03:02:03 AM UTC 24
Finished Oct 15 03:02:09 AM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168665366 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3168665366 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2970726986
Short name T811
Test name
Test status
Simulation time 39211576 ps
CPU time 1.77 seconds
Started Oct 15 03:02:09 AM UTC 24
Finished Oct 15 03:02:12 AM UTC 24
Peak memory 227976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2970726986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_
rw_with_rand_reset.2970726986 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.3064633203
Short name T810
Test name
Test status
Simulation time 24077044 ps
CPU time 1.53 seconds
Started Oct 15 03:02:09 AM UTC 24
Finished Oct 15 03:02:11 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064633203 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3064633203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.1303447540
Short name T134
Test name
Test status
Simulation time 27272986 ps
CPU time 1.13 seconds
Started Oct 15 03:02:08 AM UTC 24
Finished Oct 15 03:02:10 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303447540 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1303447540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.3164432724
Short name T812
Test name
Test status
Simulation time 225131729 ps
CPU time 3.14 seconds
Started Oct 15 03:02:09 AM UTC 24
Finished Oct 15 03:02:13 AM UTC 24
Peak memory 225656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164432724 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.3164432724 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3787745954
Short name T115
Test name
Test status
Simulation time 62989448 ps
CPU time 2.15 seconds
Started Oct 15 03:02:06 AM UTC 24
Finished Oct 15 03:02:10 AM UTC 24
Peak memory 228040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787745954 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.3787745954 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.4290680593
Short name T112
Test name
Test status
Simulation time 346773030 ps
CPU time 2.61 seconds
Started Oct 15 03:02:07 AM UTC 24
Finished Oct 15 03:02:11 AM UTC 24
Peak memory 225720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290680593 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.4290
680593 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.1071609218
Short name T808
Test name
Test status
Simulation time 25969719 ps
CPU time 2.15 seconds
Started Oct 15 03:02:08 AM UTC 24
Finished Oct 15 03:02:11 AM UTC 24
Peak memory 225816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071609218 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1071609218 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.2694132053
Short name T164
Test name
Test status
Simulation time 201926141 ps
CPU time 4.04 seconds
Started Oct 15 03:02:08 AM UTC 24
Finished Oct 15 03:02:13 AM UTC 24
Peak memory 225588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694132053 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.2694132053 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1633569390
Short name T816
Test name
Test status
Simulation time 135328407 ps
CPU time 2.31 seconds
Started Oct 15 03:02:12 AM UTC 24
Finished Oct 15 03:02:16 AM UTC 24
Peak memory 229940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1633569390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_
rw_with_rand_reset.1633569390 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.2375072112
Short name T814
Test name
Test status
Simulation time 41910916 ps
CPU time 1.46 seconds
Started Oct 15 03:02:12 AM UTC 24
Finished Oct 15 03:02:15 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375072112 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.2375072112 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.404020509
Short name T819
Test name
Test status
Simulation time 542975318 ps
CPU time 2.93 seconds
Started Oct 15 03:02:12 AM UTC 24
Finished Oct 15 03:02:16 AM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404020509 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.404020509 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2519496472
Short name T813
Test name
Test status
Simulation time 138845216 ps
CPU time 2.7 seconds
Started Oct 15 03:02:10 AM UTC 24
Finished Oct 15 03:02:14 AM UTC 24
Peak memory 228048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519496472 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.2519496472 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3020951717
Short name T116
Test name
Test status
Simulation time 286798200 ps
CPU time 2.53 seconds
Started Oct 15 03:02:10 AM UTC 24
Finished Oct 15 03:02:13 AM UTC 24
Peak memory 225716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020951717 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.3020
951717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.559511728
Short name T821
Test name
Test status
Simulation time 471822423 ps
CPU time 5.15 seconds
Started Oct 15 03:02:11 AM UTC 24
Finished Oct 15 03:02:17 AM UTC 24
Peak memory 225988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559511728 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.559511728 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.3276824920
Short name T170
Test name
Test status
Simulation time 148199870 ps
CPU time 4.48 seconds
Started Oct 15 03:02:11 AM UTC 24
Finished Oct 15 03:02:16 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276824920 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.3276824920 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2222869173
Short name T823
Test name
Test status
Simulation time 165653960 ps
CPU time 2.42 seconds
Started Oct 15 03:02:15 AM UTC 24
Finished Oct 15 03:02:18 AM UTC 24
Peak memory 231988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2222869173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_
rw_with_rand_reset.2222869173 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.2085030198
Short name T820
Test name
Test status
Simulation time 52157701 ps
CPU time 1.56 seconds
Started Oct 15 03:02:14 AM UTC 24
Finished Oct 15 03:02:16 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085030198 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2085030198 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.4025864803
Short name T817
Test name
Test status
Simulation time 33097381 ps
CPU time 1.24 seconds
Started Oct 15 03:02:14 AM UTC 24
Finished Oct 15 03:02:16 AM UTC 24
Peak memory 224112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025864803 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.4025864803 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.291965415
Short name T825
Test name
Test status
Simulation time 390540102 ps
CPU time 3.22 seconds
Started Oct 15 03:02:15 AM UTC 24
Finished Oct 15 03:02:19 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291965415 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.291965415 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2589172197
Short name T815
Test name
Test status
Simulation time 121817754 ps
CPU time 1.84 seconds
Started Oct 15 03:02:12 AM UTC 24
Finished Oct 15 03:02:15 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589172197 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.2589172197 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3532245945
Short name T818
Test name
Test status
Simulation time 133563860 ps
CPU time 2.5 seconds
Started Oct 15 03:02:12 AM UTC 24
Finished Oct 15 03:02:16 AM UTC 24
Peak memory 230068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532245945 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.3532
245945 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.2503574972
Short name T822
Test name
Test status
Simulation time 611608782 ps
CPU time 3.19 seconds
Started Oct 15 03:02:14 AM UTC 24
Finished Oct 15 03:02:18 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503574972 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2503574972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.2190940873
Short name T165
Test name
Test status
Simulation time 116019339 ps
CPU time 3.35 seconds
Started Oct 15 03:02:14 AM UTC 24
Finished Oct 15 03:02:18 AM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190940873 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.2190940873 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2610754143
Short name T835
Test name
Test status
Simulation time 82053156 ps
CPU time 3.2 seconds
Started Oct 15 03:02:17 AM UTC 24
Finished Oct 15 03:02:22 AM UTC 24
Peak memory 231856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2610754143 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_
rw_with_rand_reset.2610754143 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.14094049
Short name T828
Test name
Test status
Simulation time 45219832 ps
CPU time 1.4 seconds
Started Oct 15 03:02:17 AM UTC 24
Finished Oct 15 03:02:20 AM UTC 24
Peak memory 223880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14094049 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.14094049 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.1489349261
Short name T827
Test name
Test status
Simulation time 25933692 ps
CPU time 1.35 seconds
Started Oct 15 03:02:17 AM UTC 24
Finished Oct 15 03:02:20 AM UTC 24
Peak memory 223872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489349261 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1489349261 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3874869331
Short name T832
Test name
Test status
Simulation time 167283618 ps
CPU time 2.73 seconds
Started Oct 15 03:02:17 AM UTC 24
Finished Oct 15 03:02:21 AM UTC 24
Peak memory 225584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874869331 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.3874869331 +enable_mas
king=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3268221052
Short name T824
Test name
Test status
Simulation time 26737441 ps
CPU time 1.55 seconds
Started Oct 15 03:02:16 AM UTC 24
Finished Oct 15 03:02:18 AM UTC 24
Peak memory 223876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268221052 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.3268221052 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2839569952
Short name T826
Test name
Test status
Simulation time 82250334 ps
CPU time 2.52 seconds
Started Oct 15 03:02:16 AM UTC 24
Finished Oct 15 03:02:19 AM UTC 24
Peak memory 230304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839569952 -asser
t nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.2839
569952 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.3372358771
Short name T829
Test name
Test status
Simulation time 278953520 ps
CPU time 2.82 seconds
Started Oct 15 03:02:16 AM UTC 24
Finished Oct 15 03:02:20 AM UTC 24
Peak memory 225808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372358771 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3372358771 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.3986006740
Short name T174
Test name
Test status
Simulation time 74464030 ps
CPU time 2.82 seconds
Started Oct 15 03:02:17 AM UTC 24
Finished Oct 15 03:02:21 AM UTC 24
Peak memory 225604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986006740 -assert nopostproc +UVM_
TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.3986006740 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_app.4079125676
Short name T119
Test name
Test status
Simulation time 9128278015 ps
CPU time 279.86 seconds
Started Oct 15 04:46:21 AM UTC 24
Finished Oct 15 04:51:05 AM UTC 24
Peak memory 400112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079125676 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.4079125676 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.3708717664
Short name T37
Test name
Test status
Simulation time 28119622731 ps
CPU time 227.53 seconds
Started Oct 15 04:46:21 AM UTC 24
Finished Oct 15 04:50:12 AM UTC 24
Peak memory 346736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708717664 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.3708717664 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.2924038242
Short name T121
Test name
Test status
Simulation time 3356288814 ps
CPU time 319.31 seconds
Started Oct 15 04:46:19 AM UTC 24
Finished Oct 15 04:51:43 AM UTC 24
Peak memory 242412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924038242 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2924038242 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_error.1675795757
Short name T69
Test name
Test status
Simulation time 9740704118 ps
CPU time 175.32 seconds
Started Oct 15 04:46:21 AM UTC 24
Finished Oct 15 04:49:20 AM UTC 24
Peak memory 385636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675795757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1675795757 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.3273115658
Short name T9
Test name
Test status
Simulation time 35638441 ps
CPU time 1.98 seconds
Started Oct 15 04:46:23 AM UTC 24
Finished Oct 15 04:46:26 AM UTC 24
Peak memory 235848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273115658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3273115658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.1043527790
Short name T576
Test name
Test status
Simulation time 155138544245 ps
CPU time 3198.9 seconds
Started Oct 15 04:46:19 AM UTC 24
Finished Oct 15 05:40:13 AM UTC 24
Peak memory 3336580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043527790 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.1043527790 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.869633410
Short name T21
Test name
Test status
Simulation time 8849883739 ps
CPU time 53.93 seconds
Started Oct 15 04:46:24 AM UTC 24
Finished Oct 15 04:47:20 AM UTC 24
Peak memory 280232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869633410 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.869633410 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.470413794
Short name T30
Test name
Test status
Simulation time 20636881312 ps
CPU time 554.64 seconds
Started Oct 15 04:46:19 AM UTC 24
Finished Oct 15 04:55:41 AM UTC 24
Peak memory 631544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470413794 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.470413794 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload_invalid.2888170264
Short name T1
Test name
Test status
Simulation time 78585311 ps
CPU time 3.67 seconds
Started Oct 15 04:46:19 AM UTC 24
Finished Oct 15 04:46:24 AM UTC 24
Peak memory 237000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888170264 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload_invalid.2888170264 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.3285164115
Short name T341
Test name
Test status
Simulation time 30504775281 ps
CPU time 1505.16 seconds
Started Oct 15 04:46:23 AM UTC 24
Finished Oct 15 05:11:46 AM UTC 24
Peak memory 694896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285164115 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3285164115 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.4275579640
Short name T2
Test name
Test status
Simulation time 272430533 ps
CPU time 2.89 seconds
Started Oct 15 04:46:21 AM UTC 24
Finished Oct 15 04:46:25 AM UTC 24
Peak memory 232380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275579640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.4275579640 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.1270469260
Short name T11
Test name
Test status
Simulation time 46706794 ps
CPU time 3.45 seconds
Started Oct 15 04:46:21 AM UTC 24
Finished Oct 15 04:46:26 AM UTC 24
Peak memory 232444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270469260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1270469260 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_224.1646428928
Short name T485
Test name
Test status
Simulation time 259002568234 ps
CPU time 2579.69 seconds
Started Oct 15 04:46:19 AM UTC 24
Finished Oct 15 05:29:47 AM UTC 24
Peak memory 3211852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646428928 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1646428928 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.3146548288
Short name T375
Test name
Test status
Simulation time 17278382936 ps
CPU time 1776.64 seconds
Started Oct 15 04:46:19 AM UTC 24
Finished Oct 15 05:16:17 AM UTC 24
Peak memory 1112524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146548288 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3146548288 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.3143263793
Short name T335
Test name
Test status
Simulation time 26957621143 ps
CPU time 1489.64 seconds
Started Oct 15 04:46:19 AM UTC 24
Finished Oct 15 05:11:26 AM UTC 24
Peak memory 911824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143263793 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3143263793 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.2676380938
Short name T317
Test name
Test status
Simulation time 31057044453 ps
CPU time 1372.98 seconds
Started Oct 15 04:46:19 AM UTC 24
Finished Oct 15 05:09:28 AM UTC 24
Peak memory 1706612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676380938 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2676380938 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.821033021
Short name T187
Test name
Test status
Simulation time 51713461207 ps
CPU time 571.77 seconds
Started Oct 15 04:46:21 AM UTC 24
Finished Oct 15 04:56:00 AM UTC 24
Peak memory 371280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821033021 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.821033021 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.3015142417
Short name T104
Test name
Test status
Simulation time 21754253 ps
CPU time 1.33 seconds
Started Oct 15 04:47:43 AM UTC 24
Finished Oct 15 04:47:45 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015142417 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.3015142417 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_app.1068915869
Short name T162
Test name
Test status
Simulation time 65626467105 ps
CPU time 192.73 seconds
Started Oct 15 04:47:03 AM UTC 24
Finished Oct 15 04:50:19 AM UTC 24
Peak memory 350908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068915869 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1068915869 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.1409808075
Short name T15
Test name
Test status
Simulation time 12594699861 ps
CPU time 151.48 seconds
Started Oct 15 04:47:05 AM UTC 24
Finished Oct 15 04:49:40 AM UTC 24
Peak memory 266864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409808075 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1409808075 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.4225014338
Short name T86
Test name
Test status
Simulation time 48547940 ps
CPU time 1.38 seconds
Started Oct 15 04:47:23 AM UTC 24
Finished Oct 15 04:47:26 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225014338 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.4225014338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.574276292
Short name T90
Test name
Test status
Simulation time 25749010 ps
CPU time 1.77 seconds
Started Oct 15 04:47:26 AM UTC 24
Finished Oct 15 04:47:29 AM UTC 24
Peak memory 230076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574276292 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.574276292 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.1484106862
Short name T5
Test name
Test status
Simulation time 8211909604 ps
CPU time 29.9 seconds
Started Oct 15 04:47:28 AM UTC 24
Finished Oct 15 04:48:00 AM UTC 24
Peak memory 234564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484106862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1484106862 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.2598221990
Short name T83
Test name
Test status
Simulation time 4619453107 ps
CPU time 284.07 seconds
Started Oct 15 04:47:07 AM UTC 24
Finished Oct 15 04:51:55 AM UTC 24
Peak memory 309864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598221990 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2598221990 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_error.2941778901
Short name T24
Test name
Test status
Simulation time 16184411079 ps
CPU time 254.85 seconds
Started Oct 15 04:47:19 AM UTC 24
Finished Oct 15 04:51:38 AM UTC 24
Peak memory 316012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941778901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.2941778901 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.929809716
Short name T34
Test name
Test status
Simulation time 2038901022 ps
CPU time 13.16 seconds
Started Oct 15 04:47:21 AM UTC 24
Finished Oct 15 04:47:35 AM UTC 24
Peak memory 232056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929809716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.929809716 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.2982861287
Short name T602
Test name
Test status
Simulation time 74361204640 ps
CPU time 3399.04 seconds
Started Oct 15 04:46:26 AM UTC 24
Finished Oct 15 05:43:43 AM UTC 24
Peak memory 3547676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982861287 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.2982861287 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.1700940071
Short name T35
Test name
Test status
Simulation time 13413852114 ps
CPU time 225.17 seconds
Started Oct 15 04:47:07 AM UTC 24
Finished Oct 15 04:50:55 AM UTC 24
Peak memory 373716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700940071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1700940071 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.472044035
Short name T183
Test name
Test status
Simulation time 32836318065 ps
CPU time 355.84 seconds
Started Oct 15 04:46:26 AM UTC 24
Finished Oct 15 04:52:27 AM UTC 24
Peak memory 358960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472044035 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.472044035 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.3826581483
Short name T424
Test name
Test status
Simulation time 201442669933 ps
CPU time 2028.84 seconds
Started Oct 15 04:47:35 AM UTC 24
Finished Oct 15 05:21:45 AM UTC 24
Peak memory 1203172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826581483 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.3826581483 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.2313933474
Short name T54
Test name
Test status
Simulation time 99362500 ps
CPU time 3.72 seconds
Started Oct 15 04:46:57 AM UTC 24
Finished Oct 15 04:47:02 AM UTC 24
Peak memory 232556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313933474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.2313933474 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.3909679391
Short name T55
Test name
Test status
Simulation time 703847891 ps
CPU time 3.35 seconds
Started Oct 15 04:47:01 AM UTC 24
Finished Oct 15 04:47:06 AM UTC 24
Peak memory 232424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909679391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3909679391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.1236397200
Short name T541
Test name
Test status
Simulation time 417011714516 ps
CPU time 2940.01 seconds
Started Oct 15 04:46:38 AM UTC 24
Finished Oct 15 05:36:09 AM UTC 24
Peak memory 3168656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236397200 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1236397200 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.152893783
Short name T486
Test name
Test status
Simulation time 59706179039 ps
CPU time 2577.69 seconds
Started Oct 15 04:46:40 AM UTC 24
Finished Oct 15 05:30:07 AM UTC 24
Peak memory 2929100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152893783 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.152893783 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.519062024
Short name T51
Test name
Test status
Simulation time 1367363781 ps
CPU time 35.26 seconds
Started Oct 15 04:46:41 AM UTC 24
Finished Oct 15 04:47:18 AM UTC 24
Peak memory 244184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519062024 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.519062024 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.1373309552
Short name T278
Test name
Test status
Simulation time 10310601896 ps
CPU time 1037.29 seconds
Started Oct 15 04:46:44 AM UTC 24
Finished Oct 15 05:04:13 AM UTC 24
Peak memory 705104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373309552 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1373309552 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.3971336135
Short name T204
Test name
Test status
Simulation time 96978325509 ps
CPU time 395.09 seconds
Started Oct 15 04:46:46 AM UTC 24
Finished Oct 15 04:53:26 AM UTC 24
Peak memory 287340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971336135 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3971336135 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.1501778513
Short name T596
Test name
Test status
Simulation time 181330883511 ps
CPU time 3295.88 seconds
Started Oct 15 04:46:52 AM UTC 24
Finished Oct 15 05:42:26 AM UTC 24
Peak memory 3008968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501778513 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1501778513 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.3177332830
Short name T255
Test name
Test status
Simulation time 16024882 ps
CPU time 1.26 seconds
Started Oct 15 05:02:05 AM UTC 24
Finished Oct 15 05:02:07 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177332830 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3177332830 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_app.1847734414
Short name T254
Test name
Test status
Simulation time 4562462502 ps
CPU time 55.77 seconds
Started Oct 15 05:01:07 AM UTC 24
Finished Oct 15 05:02:04 AM UTC 24
Peak memory 248424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847734414 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1847734414 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.1576087931
Short name T438
Test name
Test status
Simulation time 26017700549 ps
CPU time 1361.93 seconds
Started Oct 15 05:01:05 AM UTC 24
Finished Oct 15 05:24:02 AM UTC 24
Peak memory 258716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576087931 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1576087931 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.3942620469
Short name T259
Test name
Test status
Simulation time 1334033561 ps
CPU time 55.05 seconds
Started Oct 15 05:01:30 AM UTC 24
Finished Oct 15 05:02:27 AM UTC 24
Peak memory 237904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942620469 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3942620469 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.1271316253
Short name T253
Test name
Test status
Simulation time 19932674 ps
CPU time 1.45 seconds
Started Oct 15 05:01:32 AM UTC 24
Finished Oct 15 05:01:35 AM UTC 24
Peak memory 226748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271316253 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.1271316253 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.2182978693
Short name T272
Test name
Test status
Simulation time 14271294596 ps
CPU time 138.91 seconds
Started Oct 15 05:01:08 AM UTC 24
Finished Oct 15 05:03:29 AM UTC 24
Peak memory 266776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182978693 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2182978693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.726411633
Short name T252
Test name
Test status
Simulation time 367652268 ps
CPU time 5.37 seconds
Started Oct 15 05:01:23 AM UTC 24
Finished Oct 15 05:01:30 AM UTC 24
Peak memory 230012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726411633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.726411633 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.84759880
Short name T256
Test name
Test status
Simulation time 3798003260 ps
CPU time 37.04 seconds
Started Oct 15 05:01:36 AM UTC 24
Finished Oct 15 05:02:14 AM UTC 24
Peak memory 264872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84759880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.84759880 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.964550322
Short name T514
Test name
Test status
Simulation time 43979227467 ps
CPU time 1917.98 seconds
Started Oct 15 05:00:48 AM UTC 24
Finished Oct 15 05:33:07 AM UTC 24
Peak memory 2232952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964550322 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.964550322 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.3693413343
Short name T258
Test name
Test status
Simulation time 4429857652 ps
CPU time 87.66 seconds
Started Oct 15 05:00:53 AM UTC 24
Finished Oct 15 05:02:23 AM UTC 24
Peak memory 266912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693413343 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3693413343 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload_invalid.4185171650
Short name T251
Test name
Test status
Simulation time 113122435 ps
CPU time 2.77 seconds
Started Oct 15 05:01:02 AM UTC 24
Finished Oct 15 05:01:07 AM UTC 24
Peak memory 236872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185171650 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload_invalid.4185171650 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.691150104
Short name T257
Test name
Test status
Simulation time 3400958750 ps
CPU time 92.63 seconds
Started Oct 15 05:00:42 AM UTC 24
Finished Oct 15 05:02:17 AM UTC 24
Peak memory 238256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691150104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.691150104 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.3147054739
Short name T163
Test name
Test status
Simulation time 44567146467 ps
CPU time 924.87 seconds
Started Oct 15 05:01:40 AM UTC 24
Finished Oct 15 05:17:16 AM UTC 24
Peak memory 318484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147054739 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3147054739 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.662931151
Short name T268
Test name
Test status
Simulation time 55371180 ps
CPU time 1.29 seconds
Started Oct 15 05:03:03 AM UTC 24
Finished Oct 15 05:03:05 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662931151 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.662931151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_app.1127345028
Short name T274
Test name
Test status
Simulation time 3845375776 ps
CPU time 91.98 seconds
Started Oct 15 05:02:30 AM UTC 24
Finished Oct 15 05:04:04 AM UTC 24
Peak memory 303716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127345028 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.1127345028 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.232493795
Short name T417
Test name
Test status
Simulation time 47307039281 ps
CPU time 1107.7 seconds
Started Oct 15 05:02:28 AM UTC 24
Finished Oct 15 05:21:08 AM UTC 24
Peak memory 254708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232493795 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.232493795 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.4128897781
Short name T263
Test name
Test status
Simulation time 24091820 ps
CPU time 1.54 seconds
Started Oct 15 05:02:56 AM UTC 24
Finished Oct 15 05:02:58 AM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128897781 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.4128897781 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.2266061333
Short name T266
Test name
Test status
Simulation time 40874571 ps
CPU time 1.89 seconds
Started Oct 15 05:02:59 AM UTC 24
Finished Oct 15 05:03:02 AM UTC 24
Peak memory 230136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266061333 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2266061333 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.2880749909
Short name T300
Test name
Test status
Simulation time 18163237665 ps
CPU time 279.16 seconds
Started Oct 15 05:02:32 AM UTC 24
Finished Oct 15 05:07:16 AM UTC 24
Peak memory 412208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880749909 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.2880749909 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.1091199346
Short name T267
Test name
Test status
Simulation time 885554168 ps
CPU time 10.43 seconds
Started Oct 15 05:02:53 AM UTC 24
Finished Oct 15 05:03:04 AM UTC 24
Peak memory 230004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091199346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1091199346 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.1677759505
Short name T665
Test name
Test status
Simulation time 60813059371 ps
CPU time 2818 seconds
Started Oct 15 05:02:15 AM UTC 24
Finished Oct 15 05:49:43 AM UTC 24
Peak memory 3070508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677759505 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.1677759505 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.2733031261
Short name T320
Test name
Test status
Simulation time 19409991060 ps
CPU time 446.58 seconds
Started Oct 15 05:02:17 AM UTC 24
Finished Oct 15 05:09:50 AM UTC 24
Peak memory 500388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733031261 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2733031261 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload_invalid.2644787043
Short name T260
Test name
Test status
Simulation time 243948412 ps
CPU time 6.68 seconds
Started Oct 15 05:02:24 AM UTC 24
Finished Oct 15 05:02:32 AM UTC 24
Peak memory 236904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644787043 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload_invalid.2644787043 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.1002930417
Short name T265
Test name
Test status
Simulation time 3768691242 ps
CPU time 51.66 seconds
Started Oct 15 05:02:08 AM UTC 24
Finished Oct 15 05:03:01 AM UTC 24
Peak memory 236852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002930417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1002930417 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.1659236512
Short name T294
Test name
Test status
Simulation time 26388415799 ps
CPU time 198.75 seconds
Started Oct 15 05:03:02 AM UTC 24
Finished Oct 15 05:06:24 AM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659236512 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.1659236512 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.1840927662
Short name T282
Test name
Test status
Simulation time 18610958 ps
CPU time 1.23 seconds
Started Oct 15 05:04:14 AM UTC 24
Finished Oct 15 05:04:17 AM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840927662 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1840927662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_app.4284120081
Short name T321
Test name
Test status
Simulation time 12733643982 ps
CPU time 378.1 seconds
Started Oct 15 05:03:27 AM UTC 24
Finished Oct 15 05:09:51 AM UTC 24
Peak memory 352816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284120081 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.4284120081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.210570921
Short name T502
Test name
Test status
Simulation time 109391001336 ps
CPU time 1721.85 seconds
Started Oct 15 05:03:21 AM UTC 24
Finished Oct 15 05:32:24 AM UTC 24
Peak memory 277104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210570921 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.210570921 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.3590383463
Short name T275
Test name
Test status
Simulation time 16088631 ps
CPU time 1.5 seconds
Started Oct 15 05:04:05 AM UTC 24
Finished Oct 15 05:04:08 AM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590383463 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3590383463 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.2076875206
Short name T276
Test name
Test status
Simulation time 46825906 ps
CPU time 1.55 seconds
Started Oct 15 05:04:09 AM UTC 24
Finished Oct 15 05:04:12 AM UTC 24
Peak memory 226748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076875206 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2076875206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_error.602233327
Short name T316
Test name
Test status
Simulation time 12092093026 ps
CPU time 330.09 seconds
Started Oct 15 05:03:53 AM UTC 24
Finished Oct 15 05:09:28 AM UTC 24
Peak memory 496236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602233327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.602233327 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.3457031296
Short name T277
Test name
Test status
Simulation time 1908004845 ps
CPU time 8.44 seconds
Started Oct 15 05:04:02 AM UTC 24
Finished Oct 15 05:04:12 AM UTC 24
Peak memory 230060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457031296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3457031296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.1847840761
Short name T280
Test name
Test status
Simulation time 473938974 ps
CPU time 1.97 seconds
Started Oct 15 05:04:12 AM UTC 24
Finished Oct 15 05:04:15 AM UTC 24
Peak memory 235896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847840761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.1847840761 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.386195996
Short name T651
Test name
Test status
Simulation time 57993192327 ps
CPU time 2662.38 seconds
Started Oct 15 05:03:06 AM UTC 24
Finished Oct 15 05:47:58 AM UTC 24
Peak memory 2847284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386195996 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.386195996 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.1837075709
Short name T279
Test name
Test status
Simulation time 2356494794 ps
CPU time 64.58 seconds
Started Oct 15 05:03:08 AM UTC 24
Finished Oct 15 05:04:14 AM UTC 24
Peak memory 256548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837075709 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1837075709 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload_invalid.2468763772
Short name T270
Test name
Test status
Simulation time 204554380 ps
CPU time 9.74 seconds
Started Oct 15 05:03:09 AM UTC 24
Finished Oct 15 05:03:20 AM UTC 24
Peak memory 234824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468763772 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload_invalid.2468763772 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.862005795
Short name T281
Test name
Test status
Simulation time 2517573183 ps
CPU time 69.33 seconds
Started Oct 15 05:03:05 AM UTC 24
Finished Oct 15 05:04:16 AM UTC 24
Peak memory 238352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862005795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.862005795 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.1406799442
Short name T427
Test name
Test status
Simulation time 52006812501 ps
CPU time 1051.85 seconds
Started Oct 15 05:04:13 AM UTC 24
Finished Oct 15 05:21:58 AM UTC 24
Peak memory 1301460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406799442 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1406799442 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.2800025260
Short name T292
Test name
Test status
Simulation time 56625000 ps
CPU time 1.32 seconds
Started Oct 15 05:06:03 AM UTC 24
Finished Oct 15 05:06:05 AM UTC 24
Peak memory 227824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800025260 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.2800025260 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_app.1889466214
Short name T331
Test name
Test status
Simulation time 10131099156 ps
CPU time 335.47 seconds
Started Oct 15 05:05:06 AM UTC 24
Finished Oct 15 05:10:46 AM UTC 24
Peak memory 332340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889466214 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1889466214 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.1182876902
Short name T147
Test name
Test status
Simulation time 13883553883 ps
CPU time 157.87 seconds
Started Oct 15 05:04:26 AM UTC 24
Finished Oct 15 05:07:06 AM UTC 24
Peak memory 248552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182876902 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1182876902 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.2668051831
Short name T297
Test name
Test status
Simulation time 2002039670 ps
CPU time 46.85 seconds
Started Oct 15 05:05:52 AM UTC 24
Finished Oct 15 05:06:41 AM UTC 24
Peak memory 237872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668051831 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2668051831 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.4037742706
Short name T289
Test name
Test status
Simulation time 177975788 ps
CPU time 1.65 seconds
Started Oct 15 05:05:58 AM UTC 24
Finished Oct 15 05:06:00 AM UTC 24
Peak memory 230112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037742706 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.4037742706 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_refresh.2562210259
Short name T307
Test name
Test status
Simulation time 12909323704 ps
CPU time 154.69 seconds
Started Oct 15 05:05:12 AM UTC 24
Finished Oct 15 05:07:50 AM UTC 24
Peak memory 277104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562210259 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2562210259 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_error.3891249120
Short name T295
Test name
Test status
Simulation time 15133257869 ps
CPU time 45.75 seconds
Started Oct 15 05:05:39 AM UTC 24
Finished Oct 15 05:06:27 AM UTC 24
Peak memory 281196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891249120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3891249120 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.3141604957
Short name T287
Test name
Test status
Simulation time 2528478533 ps
CPU time 7.24 seconds
Started Oct 15 05:05:48 AM UTC 24
Finished Oct 15 05:05:57 AM UTC 24
Peak memory 232284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141604957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3141604957 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.2183073358
Short name T291
Test name
Test status
Simulation time 42975382 ps
CPU time 2.26 seconds
Started Oct 15 05:06:01 AM UTC 24
Finished Oct 15 05:06:04 AM UTC 24
Peak memory 236392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183073358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2183073358 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.2754545546
Short name T556
Test name
Test status
Simulation time 105971612937 ps
CPU time 2046.4 seconds
Started Oct 15 05:04:17 AM UTC 24
Finished Oct 15 05:38:45 AM UTC 24
Peak memory 1366696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754545546 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.2754545546 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.3204378332
Short name T340
Test name
Test status
Simulation time 14481242650 ps
CPU time 442.74 seconds
Started Oct 15 05:04:17 AM UTC 24
Finished Oct 15 05:11:46 AM UTC 24
Peak memory 551520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204378332 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.3204378332 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload_invalid.3419280330
Short name T283
Test name
Test status
Simulation time 627658810 ps
CPU time 5.73 seconds
Started Oct 15 05:04:18 AM UTC 24
Finished Oct 15 05:04:25 AM UTC 24
Peak memory 237068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419280330 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload_invalid.3419280330 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.2596086285
Short name T286
Test name
Test status
Simulation time 2982374428 ps
CPU time 93.64 seconds
Started Oct 15 05:04:16 AM UTC 24
Finished Oct 15 05:05:51 AM UTC 24
Peak memory 238056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596086285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.2596086285 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.4246146240
Short name T345
Test name
Test status
Simulation time 28776743074 ps
CPU time 373.26 seconds
Started Oct 15 05:06:02 AM UTC 24
Finished Oct 15 05:12:20 AM UTC 24
Peak memory 389676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246146240 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.4246146240 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.683657311
Short name T304
Test name
Test status
Simulation time 56257264 ps
CPU time 1.34 seconds
Started Oct 15 05:07:23 AM UTC 24
Finished Oct 15 05:07:25 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683657311 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.683657311 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_app.1853766046
Short name T359
Test name
Test status
Simulation time 12359699068 ps
CPU time 431.49 seconds
Started Oct 15 05:06:32 AM UTC 24
Finished Oct 15 05:13:50 AM UTC 24
Peak memory 354924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853766046 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1853766046 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.3221360723
Short name T328
Test name
Test status
Simulation time 1824628864 ps
CPU time 235.62 seconds
Started Oct 15 05:06:27 AM UTC 24
Finished Oct 15 05:10:27 AM UTC 24
Peak memory 238060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221360723 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3221360723 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.236867545
Short name T301
Test name
Test status
Simulation time 113130658 ps
CPU time 1.89 seconds
Started Oct 15 05:07:15 AM UTC 24
Finished Oct 15 05:07:18 AM UTC 24
Peak memory 230072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236867545 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.236867545 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.1313548055
Short name T302
Test name
Test status
Simulation time 27649462 ps
CPU time 1.32 seconds
Started Oct 15 05:07:17 AM UTC 24
Finished Oct 15 05:07:19 AM UTC 24
Peak memory 226748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313548055 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1313548055 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.3142972345
Short name T355
Test name
Test status
Simulation time 10058803129 ps
CPU time 392.41 seconds
Started Oct 15 05:06:41 AM UTC 24
Finished Oct 15 05:13:19 AM UTC 24
Peak memory 451152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142972345 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3142972345 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_error.2713920375
Short name T361
Test name
Test status
Simulation time 67634574803 ps
CPU time 428.78 seconds
Started Oct 15 05:06:52 AM UTC 24
Finished Oct 15 05:14:07 AM UTC 24
Peak memory 615012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713920375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.2713920375 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.4175472667
Short name T299
Test name
Test status
Simulation time 1173032609 ps
CPU time 5.38 seconds
Started Oct 15 05:07:08 AM UTC 24
Finished Oct 15 05:07:14 AM UTC 24
Peak memory 230196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175472667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.4175472667 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.1713651045
Short name T409
Test name
Test status
Simulation time 32453222094 ps
CPU time 847.23 seconds
Started Oct 15 05:06:06 AM UTC 24
Finished Oct 15 05:20:23 AM UTC 24
Peak memory 694968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713651045 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.1713651045 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.2187289846
Short name T305
Test name
Test status
Simulation time 3455143020 ps
CPU time 82.51 seconds
Started Oct 15 05:06:21 AM UTC 24
Finished Oct 15 05:07:45 AM UTC 24
Peak memory 260712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187289846 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2187289846 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload_invalid.3913234553
Short name T296
Test name
Test status
Simulation time 419314884 ps
CPU time 5.37 seconds
Started Oct 15 05:06:25 AM UTC 24
Finished Oct 15 05:06:32 AM UTC 24
Peak memory 238460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913234553 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload_invalid.3913234553 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.3390955033
Short name T298
Test name
Test status
Simulation time 6492793888 ps
CPU time 45.51 seconds
Started Oct 15 05:06:05 AM UTC 24
Finished Oct 15 05:06:52 AM UTC 24
Peak memory 238216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390955033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3390955033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.2743056518
Short name T303
Test name
Test status
Simulation time 336470982 ps
CPU time 3.58 seconds
Started Oct 15 05:07:20 AM UTC 24
Finished Oct 15 05:07:25 AM UTC 24
Peak memory 232440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743056518 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2743056518 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.2284816782
Short name T314
Test name
Test status
Simulation time 45955296 ps
CPU time 1.35 seconds
Started Oct 15 05:08:39 AM UTC 24
Finished Oct 15 05:08:42 AM UTC 24
Peak memory 228064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284816782 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2284816782 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_app.2455835308
Short name T374
Test name
Test status
Simulation time 28011344974 ps
CPU time 468.06 seconds
Started Oct 15 05:07:48 AM UTC 24
Finished Oct 15 05:15:43 AM UTC 24
Peak memory 356912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455835308 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2455835308 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.2093511831
Short name T563
Test name
Test status
Simulation time 181947859928 ps
CPU time 1859.94 seconds
Started Oct 15 05:07:46 AM UTC 24
Finished Oct 15 05:39:07 AM UTC 24
Peak memory 281128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093511831 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2093511831 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.1571193981
Short name T311
Test name
Test status
Simulation time 96937171 ps
CPU time 1.61 seconds
Started Oct 15 05:08:28 AM UTC 24
Finished Oct 15 05:08:31 AM UTC 24
Peak memory 230060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571193981 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1571193981 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.3330578877
Short name T313
Test name
Test status
Simulation time 53724139 ps
CPU time 1.36 seconds
Started Oct 15 05:08:32 AM UTC 24
Finished Oct 15 05:08:35 AM UTC 24
Peak memory 227348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330578877 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3330578877 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.1006372264
Short name T330
Test name
Test status
Simulation time 17122497932 ps
CPU time 169.21 seconds
Started Oct 15 05:07:51 AM UTC 24
Finished Oct 15 05:10:43 AM UTC 24
Peak memory 279068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006372264 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1006372264 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_error.596349211
Short name T395
Test name
Test status
Simulation time 28517507554 ps
CPU time 609.77 seconds
Started Oct 15 05:08:22 AM UTC 24
Finished Oct 15 05:18:39 AM UTC 24
Peak memory 621216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596349211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.596349211 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.2689809946
Short name T312
Test name
Test status
Simulation time 568500311 ps
CPU time 8.46 seconds
Started Oct 15 05:08:25 AM UTC 24
Finished Oct 15 05:08:34 AM UTC 24
Peak memory 232252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689809946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2689809946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.1838624517
Short name T659
Test name
Test status
Simulation time 76585946178 ps
CPU time 2474.07 seconds
Started Oct 15 05:07:26 AM UTC 24
Finished Oct 15 05:49:09 AM UTC 24
Peak memory 1319664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838624517 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.1838624517 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.3394656106
Short name T333
Test name
Test status
Simulation time 4182451491 ps
CPU time 199.7 seconds
Started Oct 15 05:07:26 AM UTC 24
Finished Oct 15 05:10:49 AM UTC 24
Peak memory 340704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394656106 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.3394656106 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload_invalid.43747467
Short name T306
Test name
Test status
Simulation time 992316617 ps
CPU time 11 seconds
Started Oct 15 05:07:35 AM UTC 24
Finished Oct 15 05:07:47 AM UTC 24
Peak memory 236848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43747467 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload_invalid.43747467 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.1649741460
Short name T309
Test name
Test status
Simulation time 2215913164 ps
CPU time 56.86 seconds
Started Oct 15 05:07:25 AM UTC 24
Finished Oct 15 05:08:24 AM UTC 24
Peak memory 236572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649741460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1649741460 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.138582873
Short name T385
Test name
Test status
Simulation time 13916539424 ps
CPU time 529.46 seconds
Started Oct 15 05:08:35 AM UTC 24
Finished Oct 15 05:17:32 AM UTC 24
Peak memory 697472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138582873 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.138582873 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.2532161413
Short name T327
Test name
Test status
Simulation time 20960710 ps
CPU time 1.24 seconds
Started Oct 15 05:10:10 AM UTC 24
Finished Oct 15 05:10:13 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532161413 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2532161413 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_app.2533470107
Short name T343
Test name
Test status
Simulation time 4402751799 ps
CPU time 154.62 seconds
Started Oct 15 05:09:35 AM UTC 24
Finished Oct 15 05:12:12 AM UTC 24
Peak memory 285260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533470107 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2533470107 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.548095764
Short name T372
Test name
Test status
Simulation time 8015563060 ps
CPU time 358.06 seconds
Started Oct 15 05:09:29 AM UTC 24
Finished Oct 15 05:15:32 AM UTC 24
Peak memory 248564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548095764 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.548095764 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.2713440693
Short name T323
Test name
Test status
Simulation time 31228103 ps
CPU time 1.33 seconds
Started Oct 15 05:09:56 AM UTC 24
Finished Oct 15 05:09:59 AM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713440693 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2713440693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.2553983116
Short name T325
Test name
Test status
Simulation time 25890835 ps
CPU time 1.74 seconds
Started Oct 15 05:09:59 AM UTC 24
Finished Oct 15 05:10:02 AM UTC 24
Peak memory 230128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553983116 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2553983116 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.3368357627
Short name T326
Test name
Test status
Simulation time 1292344650 ps
CPU time 26.55 seconds
Started Oct 15 05:09:42 AM UTC 24
Finished Oct 15 05:10:10 AM UTC 24
Peak memory 238000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368357627 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.3368357627 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_error.799599814
Short name T368
Test name
Test status
Simulation time 68042450752 ps
CPU time 288.29 seconds
Started Oct 15 05:09:51 AM UTC 24
Finished Oct 15 05:14:43 AM UTC 24
Peak memory 434784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799599814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.799599814 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.1158929569
Short name T322
Test name
Test status
Simulation time 1471436815 ps
CPU time 2.09 seconds
Started Oct 15 05:09:52 AM UTC 24
Finished Oct 15 05:09:55 AM UTC 24
Peak memory 229796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158929569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1158929569 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.3625185765
Short name T329
Test name
Test status
Simulation time 493170024 ps
CPU time 28.33 seconds
Started Oct 15 05:10:02 AM UTC 24
Finished Oct 15 05:10:32 AM UTC 24
Peak memory 254564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625185765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.3625185765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.1077585201
Short name T315
Test name
Test status
Simulation time 475745119 ps
CPU time 22.32 seconds
Started Oct 15 05:08:57 AM UTC 24
Finished Oct 15 05:09:21 AM UTC 24
Peak memory 264748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077585201 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.1077585201 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.1335266395
Short name T390
Test name
Test status
Simulation time 15003971865 ps
CPU time 494.38 seconds
Started Oct 15 05:09:22 AM UTC 24
Finished Oct 15 05:17:43 AM UTC 24
Peak memory 586340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335266395 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1335266395 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload_invalid.2198118884
Short name T318
Test name
Test status
Simulation time 403306039 ps
CPU time 3.77 seconds
Started Oct 15 05:09:29 AM UTC 24
Finished Oct 15 05:09:34 AM UTC 24
Peak memory 235020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198118884 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload_invalid.2198118884 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.57647736
Short name T324
Test name
Test status
Simulation time 6021868547 ps
CPU time 77.68 seconds
Started Oct 15 05:08:42 AM UTC 24
Finished Oct 15 05:10:02 AM UTC 24
Peak memory 234584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57647736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.57647736 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.1883853378
Short name T360
Test name
Test status
Simulation time 9932595958 ps
CPU time 223.55 seconds
Started Oct 15 05:10:03 AM UTC 24
Finished Oct 15 05:13:50 AM UTC 24
Peak memory 277612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883853378 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.1883853378 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.4244249841
Short name T342
Test name
Test status
Simulation time 21328501 ps
CPU time 1.17 seconds
Started Oct 15 05:11:47 AM UTC 24
Finished Oct 15 05:11:49 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244249841 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.4244249841 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_app.2379527829
Short name T346
Test name
Test status
Simulation time 7234099182 ps
CPU time 95.91 seconds
Started Oct 15 05:10:50 AM UTC 24
Finished Oct 15 05:12:28 AM UTC 24
Peak memory 262824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379527829 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2379527829 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.1819314590
Short name T413
Test name
Test status
Simulation time 13148410919 ps
CPU time 581.43 seconds
Started Oct 15 05:10:47 AM UTC 24
Finished Oct 15 05:20:36 AM UTC 24
Peak memory 254676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819314590 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.1819314590 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.2330926167
Short name T338
Test name
Test status
Simulation time 106194263 ps
CPU time 1.29 seconds
Started Oct 15 05:11:31 AM UTC 24
Finished Oct 15 05:11:34 AM UTC 24
Peak memory 229940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330926167 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2330926167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.703506811
Short name T339
Test name
Test status
Simulation time 15154413 ps
CPU time 1.25 seconds
Started Oct 15 05:11:34 AM UTC 24
Finished Oct 15 05:11:36 AM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703506811 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.703506811 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.3433274192
Short name T369
Test name
Test status
Simulation time 10906053381 ps
CPU time 265.54 seconds
Started Oct 15 05:10:50 AM UTC 24
Finished Oct 15 05:15:19 AM UTC 24
Peak memory 408340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433274192 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3433274192 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_error.2205862765
Short name T380
Test name
Test status
Simulation time 3146820457 ps
CPU time 342.85 seconds
Started Oct 15 05:10:56 AM UTC 24
Finished Oct 15 05:16:44 AM UTC 24
Peak memory 332328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205862765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2205862765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.2937551628
Short name T337
Test name
Test status
Simulation time 1433092979 ps
CPU time 4.78 seconds
Started Oct 15 05:11:26 AM UTC 24
Finished Oct 15 05:11:32 AM UTC 24
Peak memory 230320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937551628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2937551628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.90495516
Short name T61
Test name
Test status
Simulation time 1109829726 ps
CPU time 20.55 seconds
Started Oct 15 05:11:35 AM UTC 24
Finished Oct 15 05:11:56 AM UTC 24
Peak memory 248424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90495516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.90495516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.29951344
Short name T742
Test name
Test status
Simulation time 327431001293 ps
CPU time 3160.97 seconds
Started Oct 15 05:10:28 AM UTC 24
Finished Oct 15 06:03:42 AM UTC 24
Peak memory 3314336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29951344 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.29951344 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.212023718
Short name T348
Test name
Test status
Simulation time 6923996736 ps
CPU time 129.8 seconds
Started Oct 15 05:10:33 AM UTC 24
Finished Oct 15 05:12:45 AM UTC 24
Peak memory 283232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212023718 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.212023718 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload_invalid.3497586134
Short name T332
Test name
Test status
Simulation time 268104414 ps
CPU time 3.71 seconds
Started Oct 15 05:10:44 AM UTC 24
Finished Oct 15 05:10:49 AM UTC 24
Peak memory 237140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497586134 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload_invalid.3497586134 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.2285647089
Short name T334
Test name
Test status
Simulation time 2057834757 ps
CPU time 40.57 seconds
Started Oct 15 05:10:13 AM UTC 24
Finished Oct 15 05:10:56 AM UTC 24
Peak memory 238248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285647089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2285647089 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.978091763
Short name T675
Test name
Test status
Simulation time 114933679318 ps
CPU time 2357.29 seconds
Started Oct 15 05:11:37 AM UTC 24
Finished Oct 15 05:51:21 AM UTC 24
Peak memory 1240112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978091763 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.978091763 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.3837898817
Short name T353
Test name
Test status
Simulation time 16285398 ps
CPU time 1.3 seconds
Started Oct 15 05:13:09 AM UTC 24
Finished Oct 15 05:13:11 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837898817 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3837898817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_app.972330029
Short name T373
Test name
Test status
Simulation time 3873889317 ps
CPU time 187.49 seconds
Started Oct 15 05:12:21 AM UTC 24
Finished Oct 15 05:15:32 AM UTC 24
Peak memory 299576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972330029 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.972330029 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.2516351792
Short name T363
Test name
Test status
Simulation time 2426972836 ps
CPU time 122.67 seconds
Started Oct 15 05:12:17 AM UTC 24
Finished Oct 15 05:14:22 AM UTC 24
Peak memory 238124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516351792 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2516351792 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.611139868
Short name T358
Test name
Test status
Simulation time 6013344806 ps
CPU time 40.1 seconds
Started Oct 15 05:12:59 AM UTC 24
Finished Oct 15 05:13:40 AM UTC 24
Peak memory 237984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611139868 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.611139868 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.1211697351
Short name T351
Test name
Test status
Simulation time 96505312 ps
CPU time 1.73 seconds
Started Oct 15 05:13:00 AM UTC 24
Finished Oct 15 05:13:03 AM UTC 24
Peak memory 230076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211697351 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.1211697351 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.1103700795
Short name T354
Test name
Test status
Simulation time 1521991949 ps
CPU time 46.26 seconds
Started Oct 15 05:12:28 AM UTC 24
Finished Oct 15 05:13:17 AM UTC 24
Peak memory 246160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103700795 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1103700795 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_error.3215568288
Short name T379
Test name
Test status
Simulation time 2867359799 ps
CPU time 248.23 seconds
Started Oct 15 05:12:28 AM UTC 24
Finished Oct 15 05:16:41 AM UTC 24
Peak memory 320048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215568288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3215568288 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.310240624
Short name T350
Test name
Test status
Simulation time 1103251215 ps
CPU time 12.38 seconds
Started Oct 15 05:12:46 AM UTC 24
Finished Oct 15 05:12:59 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310240624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.310240624 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.1004995138
Short name T352
Test name
Test status
Simulation time 25381615 ps
CPU time 2.19 seconds
Started Oct 15 05:13:04 AM UTC 24
Finished Oct 15 05:13:08 AM UTC 24
Peak memory 236416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004995138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1004995138 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.1490632395
Short name T698
Test name
Test status
Simulation time 41836377124 ps
CPU time 2495.32 seconds
Started Oct 15 05:11:50 AM UTC 24
Finished Oct 15 05:53:53 AM UTC 24
Peak memory 1419932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490632395 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1490632395 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.3821999442
Short name T405
Test name
Test status
Simulation time 15871314211 ps
CPU time 460.77 seconds
Started Oct 15 05:11:57 AM UTC 24
Finished Oct 15 05:19:44 AM UTC 24
Peak memory 584236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821999442 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3821999442 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload_invalid.2999395749
Short name T344
Test name
Test status
Simulation time 105228369 ps
CPU time 1.92 seconds
Started Oct 15 05:12:13 AM UTC 24
Finished Oct 15 05:12:16 AM UTC 24
Peak memory 236148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999395749 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload_invalid.2999395749 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.1390578633
Short name T347
Test name
Test status
Simulation time 1819721371 ps
CPU time 39.65 seconds
Started Oct 15 05:11:47 AM UTC 24
Finished Oct 15 05:12:28 AM UTC 24
Peak memory 238120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390578633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.1390578633 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.4164398009
Short name T367
Test name
Test status
Simulation time 52059096 ps
CPU time 1.31 seconds
Started Oct 15 05:14:32 AM UTC 24
Finished Oct 15 05:14:34 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164398009 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.4164398009 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_app.3922792584
Short name T377
Test name
Test status
Simulation time 14408957622 ps
CPU time 171.17 seconds
Started Oct 15 05:13:41 AM UTC 24
Finished Oct 15 05:16:35 AM UTC 24
Peak memory 359020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922792584 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3922792584 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.3815380605
Short name T462
Test name
Test status
Simulation time 27940851413 ps
CPU time 807.2 seconds
Started Oct 15 05:13:36 AM UTC 24
Finished Oct 15 05:27:13 AM UTC 24
Peak memory 254572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815380605 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3815380605 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.1355033807
Short name T364
Test name
Test status
Simulation time 37718640 ps
CPU time 1.64 seconds
Started Oct 15 05:14:23 AM UTC 24
Finished Oct 15 05:14:25 AM UTC 24
Peak memory 230076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355033807 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1355033807 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.2580229978
Short name T365
Test name
Test status
Simulation time 83143118 ps
CPU time 1.93 seconds
Started Oct 15 05:14:24 AM UTC 24
Finished Oct 15 05:14:27 AM UTC 24
Peak memory 230076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580229978 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2580229978 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.3157675723
Short name T425
Test name
Test status
Simulation time 55474234560 ps
CPU time 473.48 seconds
Started Oct 15 05:13:50 AM UTC 24
Finished Oct 15 05:21:50 AM UTC 24
Peak memory 551528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157675723 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3157675723 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_error.703992163
Short name T383
Test name
Test status
Simulation time 13522718961 ps
CPU time 191.47 seconds
Started Oct 15 05:13:51 AM UTC 24
Finished Oct 15 05:17:06 AM UTC 24
Peak memory 383728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703992163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.703992163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.1141322937
Short name T362
Test name
Test status
Simulation time 3990685919 ps
CPU time 12.64 seconds
Started Oct 15 05:14:07 AM UTC 24
Finished Oct 15 05:14:21 AM UTC 24
Peak memory 230132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141322937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.1141322937 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.171009495
Short name T366
Test name
Test status
Simulation time 535523762 ps
CPU time 3.93 seconds
Started Oct 15 05:14:26 AM UTC 24
Finished Oct 15 05:14:31 AM UTC 24
Peak memory 237460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171009495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.171009495 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.1414869924
Short name T715
Test name
Test status
Simulation time 39279014862 ps
CPU time 2579.19 seconds
Started Oct 15 05:13:18 AM UTC 24
Finished Oct 15 05:56:46 AM UTC 24
Peak memory 1321552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414869924 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.1414869924 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.199916294
Short name T399
Test name
Test status
Simulation time 49010206440 ps
CPU time 353.33 seconds
Started Oct 15 05:13:20 AM UTC 24
Finished Oct 15 05:19:18 AM UTC 24
Peak memory 498392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199916294 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.199916294 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload_invalid.4264947683
Short name T357
Test name
Test status
Simulation time 182181374 ps
CPU time 5.03 seconds
Started Oct 15 05:13:29 AM UTC 24
Finished Oct 15 05:13:35 AM UTC 24
Peak memory 236908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264947683 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload_invalid.4264947683 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.3356820156
Short name T356
Test name
Test status
Simulation time 310194623 ps
CPU time 15.1 seconds
Started Oct 15 05:13:12 AM UTC 24
Finished Oct 15 05:13:28 AM UTC 24
Peak memory 238172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356820156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3356820156 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.3580311528
Short name T394
Test name
Test status
Simulation time 7044709952 ps
CPU time 232.87 seconds
Started Oct 15 05:14:28 AM UTC 24
Finished Oct 15 05:18:24 AM UTC 24
Peak memory 283376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580311528 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3580311528 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.2575192233
Short name T102
Test name
Test status
Simulation time 47715225 ps
CPU time 1.26 seconds
Started Oct 15 04:49:37 AM UTC 24
Finished Oct 15 04:49:39 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575192233 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2575192233 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_app.995029765
Short name T31
Test name
Test status
Simulation time 56895231817 ps
CPU time 520.41 seconds
Started Oct 15 04:48:35 AM UTC 24
Finished Oct 15 04:57:22 AM UTC 24
Peak memory 559868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995029765 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.995029765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.483917650
Short name T212
Test name
Test status
Simulation time 57451248652 ps
CPU time 330.28 seconds
Started Oct 15 04:48:38 AM UTC 24
Finished Oct 15 04:54:13 AM UTC 24
Peak memory 416372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483917650 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.483917650 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.2166343391
Short name T310
Test name
Test status
Simulation time 83879002983 ps
CPU time 1222.47 seconds
Started Oct 15 04:47:50 AM UTC 24
Finished Oct 15 05:08:27 AM UTC 24
Peak memory 256756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166343391 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2166343391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.1950692029
Short name T103
Test name
Test status
Simulation time 2570491267 ps
CPU time 45.19 seconds
Started Oct 15 04:49:04 AM UTC 24
Finished Oct 15 04:49:51 AM UTC 24
Peak memory 237936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950692029 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1950692029 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.4203958163
Short name T57
Test name
Test status
Simulation time 1541110410 ps
CPU time 36.07 seconds
Started Oct 15 04:49:06 AM UTC 24
Finished Oct 15 04:49:44 AM UTC 24
Peak memory 236636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203958163 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.4203958163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.59029432
Short name T6
Test name
Test status
Simulation time 2711316328 ps
CPU time 50.15 seconds
Started Oct 15 04:49:08 AM UTC 24
Finished Oct 15 04:49:59 AM UTC 24
Peak memory 236784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59029432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.59029432 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_error.2550283724
Short name T23
Test name
Test status
Simulation time 1838219554 ps
CPU time 139.71 seconds
Started Oct 15 04:48:55 AM UTC 24
Finished Oct 15 04:51:18 AM UTC 24
Peak memory 299756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550283724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2550283724 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.2041296939
Short name T56
Test name
Test status
Simulation time 838404042 ps
CPU time 6.5 seconds
Started Oct 15 04:48:57 AM UTC 24
Finished Oct 15 04:49:05 AM UTC 24
Peak memory 230200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041296939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.2041296939 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.755079465
Short name T470
Test name
Test status
Simulation time 19251616284 ps
CPU time 2420.16 seconds
Started Oct 15 04:47:47 AM UTC 24
Finished Oct 15 05:28:34 AM UTC 24
Peak memory 1389160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755079465 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.755079465 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.3859970245
Short name T95
Test name
Test status
Simulation time 82471926822 ps
CPU time 252.7 seconds
Started Oct 15 04:48:53 AM UTC 24
Finished Oct 15 04:53:09 AM UTC 24
Peak memory 320488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859970245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3859970245 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.4154782355
Short name T46
Test name
Test status
Simulation time 9250706000 ps
CPU time 116.76 seconds
Started Oct 15 04:49:36 AM UTC 24
Finished Oct 15 04:51:35 AM UTC 24
Peak memory 323248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154782355 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.4154782355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.1233412286
Short name T26
Test name
Test status
Simulation time 55107933013 ps
CPU time 388.27 seconds
Started Oct 15 04:47:47 AM UTC 24
Finished Oct 15 04:54:20 AM UTC 24
Peak memory 526956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233412286 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1233412286 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload_invalid.1664777187
Short name T17
Test name
Test status
Simulation time 42567986 ps
CPU time 2.7 seconds
Started Oct 15 04:47:49 AM UTC 24
Finished Oct 15 04:47:53 AM UTC 24
Peak memory 236668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664777187 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload_invalid.1664777187 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.3658394312
Short name T71
Test name
Test status
Simulation time 10693195001 ps
CPU time 55.65 seconds
Started Oct 15 04:47:47 AM UTC 24
Finished Oct 15 04:48:44 AM UTC 24
Peak memory 238248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658394312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3658394312 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.948407375
Short name T429
Test name
Test status
Simulation time 213921479604 ps
CPU time 1964.46 seconds
Started Oct 15 04:49:14 AM UTC 24
Finished Oct 15 05:22:21 AM UTC 24
Peak memory 1070060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948407375 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.948407375 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.1413472958
Short name T79
Test name
Test status
Simulation time 614925594 ps
CPU time 14.96 seconds
Started Oct 15 04:49:20 AM UTC 24
Finished Oct 15 04:49:36 AM UTC 24
Peak memory 254156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1413472958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_r
and_reset.1413472958 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.3891086544
Short name T105
Test name
Test status
Simulation time 265079036 ps
CPU time 3.25 seconds
Started Oct 15 04:48:27 AM UTC 24
Finished Oct 15 04:48:32 AM UTC 24
Peak memory 232424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891086544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.3891086544 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.934263176
Short name T189
Test name
Test status
Simulation time 253049101 ps
CPU time 2.85 seconds
Started Oct 15 04:48:33 AM UTC 24
Finished Oct 15 04:48:37 AM UTC 24
Peak memory 232392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934263176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vector
s_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.934263176 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.1488817828
Short name T489
Test name
Test status
Simulation time 260563304235 ps
CPU time 2513.39 seconds
Started Oct 15 04:47:53 AM UTC 24
Finished Oct 15 05:30:15 AM UTC 24
Peak memory 1206672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488817828 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.1488817828 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.2753560690
Short name T101
Test name
Test status
Simulation time 27732307305 ps
CPU time 67.76 seconds
Started Oct 15 04:47:53 AM UTC 24
Finished Oct 15 04:49:03 AM UTC 24
Peak memory 260592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753560690 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2753560690 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.1849769909
Short name T100
Test name
Test status
Simulation time 8433974802 ps
CPU time 52.13 seconds
Started Oct 15 04:48:01 AM UTC 24
Finished Oct 15 04:48:54 AM UTC 24
Peak memory 246316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849769909 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1849769909 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.3434119858
Short name T75
Test name
Test status
Simulation time 4973964245 ps
CPU time 30.02 seconds
Started Oct 15 04:48:02 AM UTC 24
Finished Oct 15 04:48:33 AM UTC 24
Peak memory 236672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434119858 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3434119858 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.567745270
Short name T185
Test name
Test status
Simulation time 10134265355 ps
CPU time 225.73 seconds
Started Oct 15 04:48:20 AM UTC 24
Finished Oct 15 04:52:09 AM UTC 24
Peak memory 246356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567745270 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.567745270 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.4104638224
Short name T378
Test name
Test status
Simulation time 57746271 ps
CPU time 1.24 seconds
Started Oct 15 05:16:34 AM UTC 24
Finished Oct 15 05:16:37 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104638224 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.4104638224 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_app.3998473972
Short name T403
Test name
Test status
Simulation time 3764383031 ps
CPU time 236.39 seconds
Started Oct 15 05:15:33 AM UTC 24
Finished Oct 15 05:19:33 AM UTC 24
Peak memory 322348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998473972 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3998473972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.2835014192
Short name T388
Test name
Test status
Simulation time 3652591570 ps
CPU time 121.89 seconds
Started Oct 15 05:15:33 AM UTC 24
Finished Oct 15 05:17:37 AM UTC 24
Peak memory 248372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835014192 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2835014192 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.3856084466
Short name T384
Test name
Test status
Simulation time 6519858958 ps
CPU time 108.21 seconds
Started Oct 15 05:15:33 AM UTC 24
Finished Oct 15 05:17:23 AM UTC 24
Peak memory 301740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856084466 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.3856084466 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_error.1474609050
Short name T428
Test name
Test status
Simulation time 13396242102 ps
CPU time 374.49 seconds
Started Oct 15 05:15:44 AM UTC 24
Finished Oct 15 05:22:03 AM UTC 24
Peak memory 549428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474609050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1474609050 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.3943772365
Short name T376
Test name
Test status
Simulation time 525796013 ps
CPU time 7.92 seconds
Started Oct 15 05:16:17 AM UTC 24
Finished Oct 15 05:16:26 AM UTC 24
Peak memory 232116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943772365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3943772365 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.691279777
Short name T73
Test name
Test status
Simulation time 198931860 ps
CPU time 4.79 seconds
Started Oct 15 05:16:27 AM UTC 24
Finished Oct 15 05:16:33 AM UTC 24
Peak memory 244748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691279777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.691279777 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.3200916278
Short name T501
Test name
Test status
Simulation time 100792318951 ps
CPU time 1043.26 seconds
Started Oct 15 05:14:44 AM UTC 24
Finished Oct 15 05:32:19 AM UTC 24
Peak memory 1393260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200916278 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.3200916278 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.476098617
Short name T408
Test name
Test status
Simulation time 101069801628 ps
CPU time 297.77 seconds
Started Oct 15 05:15:20 AM UTC 24
Finished Oct 15 05:20:22 AM UTC 24
Peak memory 479924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476098617 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.476098617 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload_invalid.1766425131
Short name T371
Test name
Test status
Simulation time 92341017 ps
CPU time 8.65 seconds
Started Oct 15 05:15:22 AM UTC 24
Finished Oct 15 05:15:31 AM UTC 24
Peak memory 237044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766425131 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload_invalid.1766425131 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.374980100
Short name T370
Test name
Test status
Simulation time 3880473954 ps
CPU time 44.04 seconds
Started Oct 15 05:14:35 AM UTC 24
Finished Oct 15 05:15:20 AM UTC 24
Peak memory 238184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374980100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.374980100 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.2171182911
Short name T619
Test name
Test status
Simulation time 206340185763 ps
CPU time 1686.62 seconds
Started Oct 15 05:16:28 AM UTC 24
Finished Oct 15 05:44:53 AM UTC 24
Peak memory 1260048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171182911 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2171182911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.217670825
Short name T389
Test name
Test status
Simulation time 20863049 ps
CPU time 1.2 seconds
Started Oct 15 05:17:38 AM UTC 24
Finished Oct 15 05:17:40 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217670825 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.217670825 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_app.98753904
Short name T393
Test name
Test status
Simulation time 3531620827 ps
CPU time 79.1 seconds
Started Oct 15 05:17:00 AM UTC 24
Finished Oct 15 05:18:20 AM UTC 24
Peak memory 264796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98753904 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.98753904 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.4195075810
Short name T598
Test name
Test status
Simulation time 31983919086 ps
CPU time 1522.61 seconds
Started Oct 15 05:16:58 AM UTC 24
Finished Oct 15 05:42:38 AM UTC 24
Peak memory 277092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195075810 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.4195075810 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.2834731015
Short name T88
Test name
Test status
Simulation time 9621824314 ps
CPU time 193.75 seconds
Started Oct 15 05:17:07 AM UTC 24
Finished Oct 15 05:20:23 AM UTC 24
Peak memory 394020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834731015 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2834731015 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_error.2760083889
Short name T465
Test name
Test status
Simulation time 6604417323 ps
CPU time 618.78 seconds
Started Oct 15 05:17:17 AM UTC 24
Finished Oct 15 05:27:43 AM UTC 24
Peak memory 397928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760083889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.2760083889 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.2476677907
Short name T386
Test name
Test status
Simulation time 671537882 ps
CPU time 7.49 seconds
Started Oct 15 05:17:24 AM UTC 24
Finished Oct 15 05:17:32 AM UTC 24
Peak memory 230036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476677907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2476677907 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.1319433534
Short name T387
Test name
Test status
Simulation time 117459155 ps
CPU time 2.82 seconds
Started Oct 15 05:17:33 AM UTC 24
Finished Oct 15 05:17:37 AM UTC 24
Peak memory 236392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319433534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1319433534 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.2327027190
Short name T760
Test name
Test status
Simulation time 92292114964 ps
CPU time 3786.69 seconds
Started Oct 15 05:16:38 AM UTC 24
Finished Oct 15 06:20:26 AM UTC 24
Peak memory 3707608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327027190 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.2327027190 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.1136031108
Short name T407
Test name
Test status
Simulation time 53565594796 ps
CPU time 208.07 seconds
Started Oct 15 05:16:41 AM UTC 24
Finished Oct 15 05:20:13 AM UTC 24
Peak memory 330344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136031108 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1136031108 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload_invalid.2684111348
Short name T381
Test name
Test status
Simulation time 147497333 ps
CPU time 10.98 seconds
Started Oct 15 05:16:45 AM UTC 24
Finished Oct 15 05:16:57 AM UTC 24
Peak memory 236908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684111348 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload_invalid.2684111348 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.307986001
Short name T382
Test name
Test status
Simulation time 2321136235 ps
CPU time 21.2 seconds
Started Oct 15 05:16:36 AM UTC 24
Finished Oct 15 05:16:59 AM UTC 24
Peak memory 238192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307986001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.307986001 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.756819264
Short name T492
Test name
Test status
Simulation time 22195019055 ps
CPU time 765.79 seconds
Started Oct 15 05:17:33 AM UTC 24
Finished Oct 15 05:30:28 AM UTC 24
Peak memory 587000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756819264 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.756819264 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.2260399637
Short name T401
Test name
Test status
Simulation time 29039082 ps
CPU time 1.29 seconds
Started Oct 15 05:19:19 AM UTC 24
Finished Oct 15 05:19:22 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260399637 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2260399637 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_app.1024306065
Short name T412
Test name
Test status
Simulation time 2968536293 ps
CPU time 123.84 seconds
Started Oct 15 05:18:22 AM UTC 24
Finished Oct 15 05:20:28 AM UTC 24
Peak memory 301668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024306065 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.1024306065 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.1945959472
Short name T537
Test name
Test status
Simulation time 80578401833 ps
CPU time 1023.36 seconds
Started Oct 15 05:18:06 AM UTC 24
Finished Oct 15 05:35:22 AM UTC 24
Peak memory 264816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945959472 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1945959472 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.3742226580
Short name T423
Test name
Test status
Simulation time 12421049813 ps
CPU time 196.75 seconds
Started Oct 15 05:18:25 AM UTC 24
Finished Oct 15 05:21:45 AM UTC 24
Peak memory 277172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742226580 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3742226580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_error.2941634982
Short name T402
Test name
Test status
Simulation time 980798171 ps
CPU time 40.15 seconds
Started Oct 15 05:18:41 AM UTC 24
Finished Oct 15 05:19:22 AM UTC 24
Peak memory 264740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941634982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2941634982 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.297220760
Short name T397
Test name
Test status
Simulation time 4608948533 ps
CPU time 16.55 seconds
Started Oct 15 05:18:58 AM UTC 24
Finished Oct 15 05:19:16 AM UTC 24
Peak memory 230072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297220760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.297220760 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.2652930407
Short name T400
Test name
Test status
Simulation time 49577399 ps
CPU time 2.16 seconds
Started Oct 15 05:19:17 AM UTC 24
Finished Oct 15 05:19:20 AM UTC 24
Peak memory 234284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652930407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2652930407 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.3693852815
Short name T743
Test name
Test status
Simulation time 158830559289 ps
CPU time 2754.62 seconds
Started Oct 15 05:17:41 AM UTC 24
Finished Oct 15 06:04:05 AM UTC 24
Peak memory 3001080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693852815 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.3693852815 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.2163707971
Short name T442
Test name
Test status
Simulation time 31245643600 ps
CPU time 415.53 seconds
Started Oct 15 05:17:43 AM UTC 24
Finished Oct 15 05:24:44 AM UTC 24
Peak memory 571948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163707971 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2163707971 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload_invalid.3171634100
Short name T392
Test name
Test status
Simulation time 232300470 ps
CPU time 5.21 seconds
Started Oct 15 05:17:59 AM UTC 24
Finished Oct 15 05:18:06 AM UTC 24
Peak memory 236848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171634100 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload_invalid.3171634100 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.2250104881
Short name T398
Test name
Test status
Simulation time 9267998178 ps
CPU time 96.46 seconds
Started Oct 15 05:17:38 AM UTC 24
Finished Oct 15 05:19:17 AM UTC 24
Peak memory 234604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250104881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.2250104881 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.3448932047
Short name T451
Test name
Test status
Simulation time 50651678151 ps
CPU time 404.11 seconds
Started Oct 15 05:19:17 AM UTC 24
Finished Oct 15 05:26:06 AM UTC 24
Peak memory 410228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448932047 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3448932047 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.3243636046
Short name T411
Test name
Test status
Simulation time 20399515 ps
CPU time 1.29 seconds
Started Oct 15 05:20:24 AM UTC 24
Finished Oct 15 05:20:26 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243636046 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3243636046 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_app.1609725754
Short name T437
Test name
Test status
Simulation time 27189817742 ps
CPU time 252.9 seconds
Started Oct 15 05:19:45 AM UTC 24
Finished Oct 15 05:24:02 AM UTC 24
Peak memory 307760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609725754 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1609725754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.1298477021
Short name T587
Test name
Test status
Simulation time 28364606109 ps
CPU time 1302.19 seconds
Started Oct 15 05:19:39 AM UTC 24
Finished Oct 15 05:41:36 AM UTC 24
Peak memory 258920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298477021 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.1298477021 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.685465583
Short name T452
Test name
Test status
Simulation time 29799738849 ps
CPU time 380.58 seconds
Started Oct 15 05:19:55 AM UTC 24
Finished Oct 15 05:26:21 AM UTC 24
Peak memory 322292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685465583 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.685465583 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_error.4288500823
Short name T420
Test name
Test status
Simulation time 6010504430 ps
CPU time 79.24 seconds
Started Oct 15 05:20:14 AM UTC 24
Finished Oct 15 05:21:35 AM UTC 24
Peak memory 314096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288500823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.4288500823 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.283910359
Short name T410
Test name
Test status
Simulation time 586422338 ps
CPU time 4.69 seconds
Started Oct 15 05:20:19 AM UTC 24
Finished Oct 15 05:20:24 AM UTC 24
Peak memory 232244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283910359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.283910359 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.2065645340
Short name T416
Test name
Test status
Simulation time 6921648089 ps
CPU time 19.21 seconds
Started Oct 15 05:20:24 AM UTC 24
Finished Oct 15 05:20:44 AM UTC 24
Peak memory 264948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065645340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2065645340 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.1814966237
Short name T479
Test name
Test status
Simulation time 5968980159 ps
CPU time 590.56 seconds
Started Oct 15 05:19:22 AM UTC 24
Finished Oct 15 05:29:20 AM UTC 24
Peak memory 584356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814966237 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.1814966237 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.577205726
Short name T446
Test name
Test status
Simulation time 14868595359 ps
CPU time 355.24 seconds
Started Oct 15 05:19:23 AM UTC 24
Finished Oct 15 05:25:24 AM UTC 24
Peak memory 563956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577205726 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.577205726 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload_invalid.2624668977
Short name T404
Test name
Test status
Simulation time 48661955 ps
CPU time 2.55 seconds
Started Oct 15 05:19:34 AM UTC 24
Finished Oct 15 05:19:37 AM UTC 24
Peak memory 234940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624668977 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload_invalid.2624668977 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.544028728
Short name T406
Test name
Test status
Simulation time 4584402630 ps
CPU time 30.88 seconds
Started Oct 15 05:19:21 AM UTC 24
Finished Oct 15 05:19:54 AM UTC 24
Peak memory 238256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544028728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.544028728 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.298405183
Short name T557
Test name
Test status
Simulation time 22932656874 ps
CPU time 1091.77 seconds
Started Oct 15 05:20:24 AM UTC 24
Finished Oct 15 05:38:49 AM UTC 24
Peak memory 576504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298405183 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.298405183 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.1479315665
Short name T422
Test name
Test status
Simulation time 15989446 ps
CPU time 1.3 seconds
Started Oct 15 05:21:37 AM UTC 24
Finished Oct 15 05:21:39 AM UTC 24
Peak memory 226984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479315665 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.1479315665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_app.1711378368
Short name T463
Test name
Test status
Simulation time 149581313560 ps
CPU time 397.51 seconds
Started Oct 15 05:20:43 AM UTC 24
Finished Oct 15 05:27:26 AM UTC 24
Peak memory 543324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711378368 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1711378368 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.3212474845
Short name T460
Test name
Test status
Simulation time 74456655472 ps
CPU time 376.22 seconds
Started Oct 15 05:20:40 AM UTC 24
Finished Oct 15 05:27:02 AM UTC 24
Peak memory 248416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212474845 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3212474845 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.631726136
Short name T474
Test name
Test status
Simulation time 96227725402 ps
CPU time 471.26 seconds
Started Oct 15 05:20:45 AM UTC 24
Finished Oct 15 05:28:43 AM UTC 24
Peak memory 557616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631726136 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.631726136 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_error.45830099
Short name T468
Test name
Test status
Simulation time 9189789960 ps
CPU time 425.54 seconds
Started Oct 15 05:21:09 AM UTC 24
Finished Oct 15 05:28:21 AM UTC 24
Peak memory 387740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45830099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.45830099 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.3906078935
Short name T421
Test name
Test status
Simulation time 1162725538 ps
CPU time 6.74 seconds
Started Oct 15 05:21:28 AM UTC 24
Finished Oct 15 05:21:36 AM UTC 24
Peak memory 230004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906078935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3906078935 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.980181387
Short name T62
Test name
Test status
Simulation time 52107486 ps
CPU time 2.26 seconds
Started Oct 15 05:21:34 AM UTC 24
Finished Oct 15 05:21:37 AM UTC 24
Peak memory 236500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980181387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.980181387 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.1146215068
Short name T682
Test name
Test status
Simulation time 14733348086 ps
CPU time 1866.55 seconds
Started Oct 15 05:20:27 AM UTC 24
Finished Oct 15 05:51:55 AM UTC 24
Peak memory 1051296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146215068 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.1146215068 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.1598607536
Short name T445
Test name
Test status
Simulation time 25853959797 ps
CPU time 282.79 seconds
Started Oct 15 05:20:29 AM UTC 24
Finished Oct 15 05:25:16 AM UTC 24
Peak memory 391836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598607536 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1598607536 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload_invalid.4038112537
Short name T415
Test name
Test status
Simulation time 74229382 ps
CPU time 5.73 seconds
Started Oct 15 05:20:36 AM UTC 24
Finished Oct 15 05:20:43 AM UTC 24
Peak memory 236924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038112537 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload_invalid.4038112537 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.2453694410
Short name T418
Test name
Test status
Simulation time 5650164292 ps
CPU time 60.08 seconds
Started Oct 15 05:20:25 AM UTC 24
Finished Oct 15 05:21:27 AM UTC 24
Peak memory 238316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453694410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2453694410 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.261636226
Short name T506
Test name
Test status
Simulation time 34345328348 ps
CPU time 653.48 seconds
Started Oct 15 05:21:36 AM UTC 24
Finished Oct 15 05:32:37 AM UTC 24
Peak memory 436832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261636226 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.261636226 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.433271856
Short name T433
Test name
Test status
Simulation time 20210811 ps
CPU time 1.35 seconds
Started Oct 15 05:22:34 AM UTC 24
Finished Oct 15 05:22:36 AM UTC 24
Peak memory 226872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433271856 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.433271856 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_app.3739288984
Short name T467
Test name
Test status
Simulation time 10883527510 ps
CPU time 362.27 seconds
Started Oct 15 05:21:56 AM UTC 24
Finished Oct 15 05:28:04 AM UTC 24
Peak memory 455332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739288984 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3739288984 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.1542826751
Short name T517
Test name
Test status
Simulation time 7070068235 ps
CPU time 689.36 seconds
Started Oct 15 05:21:50 AM UTC 24
Finished Oct 15 05:33:28 AM UTC 24
Peak memory 254508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542826751 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.1542826751 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.2546002621
Short name T459
Test name
Test status
Simulation time 6774783239 ps
CPU time 298.2 seconds
Started Oct 15 05:21:59 AM UTC 24
Finished Oct 15 05:27:01 AM UTC 24
Peak memory 332328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546002621 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2546002621 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_error.2327572583
Short name T475
Test name
Test status
Simulation time 4724482501 ps
CPU time 399.4 seconds
Started Oct 15 05:22:05 AM UTC 24
Finished Oct 15 05:28:49 AM UTC 24
Peak memory 385828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327572583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2327572583 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.3564980235
Short name T431
Test name
Test status
Simulation time 9008495420 ps
CPU time 10.4 seconds
Started Oct 15 05:22:22 AM UTC 24
Finished Oct 15 05:22:33 AM UTC 24
Peak memory 230236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564980235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3564980235 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.1901587338
Short name T66
Test name
Test status
Simulation time 29284651 ps
CPU time 1.86 seconds
Started Oct 15 05:22:25 AM UTC 24
Finished Oct 15 05:22:28 AM UTC 24
Peak memory 233892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901587338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1901587338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.1115002942
Short name T679
Test name
Test status
Simulation time 293232644720 ps
CPU time 1790.54 seconds
Started Oct 15 05:21:40 AM UTC 24
Finished Oct 15 05:51:50 AM UTC 24
Peak memory 2011884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115002942 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.1115002942 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.3163459159
Short name T432
Test name
Test status
Simulation time 2549825067 ps
CPU time 47.44 seconds
Started Oct 15 05:21:45 AM UTC 24
Finished Oct 15 05:22:34 AM UTC 24
Peak memory 258656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163459159 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3163459159 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload_invalid.3691712532
Short name T426
Test name
Test status
Simulation time 108182184 ps
CPU time 8.21 seconds
Started Oct 15 05:21:46 AM UTC 24
Finished Oct 15 05:21:56 AM UTC 24
Peak memory 236872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691712532 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload_invalid.3691712532 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.4225071598
Short name T430
Test name
Test status
Simulation time 4412725353 ps
CPU time 44.9 seconds
Started Oct 15 05:21:38 AM UTC 24
Finished Oct 15 05:22:24 AM UTC 24
Peak memory 238180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225071598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.4225071598 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.1874107486
Short name T439
Test name
Test status
Simulation time 2966017676 ps
CPU time 94.74 seconds
Started Oct 15 05:22:29 AM UTC 24
Finished Oct 15 05:24:06 AM UTC 24
Peak memory 297936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874107486 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.1874107486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.3168046725
Short name T443
Test name
Test status
Simulation time 48515866 ps
CPU time 1.23 seconds
Started Oct 15 05:25:09 AM UTC 24
Finished Oct 15 05:25:12 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168046725 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.3168046725 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_app.1209962331
Short name T444
Test name
Test status
Simulation time 5684990278 ps
CPU time 69.11 seconds
Started Oct 15 05:24:03 AM UTC 24
Finished Oct 15 05:25:14 AM UTC 24
Peak memory 258668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209962331 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1209962331 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.285724636
Short name T621
Test name
Test status
Simulation time 46344018089 ps
CPU time 1289.41 seconds
Started Oct 15 05:23:32 AM UTC 24
Finished Oct 15 05:45:16 AM UTC 24
Peak memory 262904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285724636 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.285724636 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.3097152907
Short name T500
Test name
Test status
Simulation time 77364927230 ps
CPU time 485.74 seconds
Started Oct 15 05:24:03 AM UTC 24
Finished Oct 15 05:32:15 AM UTC 24
Peak memory 545524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097152907 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3097152907 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_error.4125531385
Short name T456
Test name
Test status
Simulation time 45742651590 ps
CPU time 165.72 seconds
Started Oct 15 05:24:07 AM UTC 24
Finished Oct 15 05:26:56 AM UTC 24
Peak memory 330396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125531385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.4125531385 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.1481735474
Short name T441
Test name
Test status
Simulation time 522218619 ps
CPU time 5.69 seconds
Started Oct 15 05:24:32 AM UTC 24
Finished Oct 15 05:24:39 AM UTC 24
Peak memory 231988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481735474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1481735474 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.776033564
Short name T74
Test name
Test status
Simulation time 2968712856 ps
CPU time 26.68 seconds
Started Oct 15 05:24:40 AM UTC 24
Finished Oct 15 05:25:08 AM UTC 24
Peak memory 266936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776033564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.776033564 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.3718056018
Short name T487
Test name
Test status
Simulation time 15360605094 ps
CPU time 446.61 seconds
Started Oct 15 05:22:37 AM UTC 24
Finished Oct 15 05:30:10 AM UTC 24
Peak memory 465564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718056018 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.3718056018 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.3404120593
Short name T469
Test name
Test status
Simulation time 17088070272 ps
CPU time 325.38 seconds
Started Oct 15 05:23:02 AM UTC 24
Finished Oct 15 05:28:32 AM UTC 24
Peak memory 424560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404120593 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.3404120593 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload_invalid.3256287723
Short name T436
Test name
Test status
Simulation time 422257898 ps
CPU time 9.47 seconds
Started Oct 15 05:23:21 AM UTC 24
Finished Oct 15 05:23:31 AM UTC 24
Peak memory 236808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256287723 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload_invalid.3256287723 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.4110735618
Short name T434
Test name
Test status
Simulation time 3792467120 ps
CPU time 25.19 seconds
Started Oct 15 05:22:35 AM UTC 24
Finished Oct 15 05:23:02 AM UTC 24
Peak memory 234500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110735618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.4110735618 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.3663217415
Short name T507
Test name
Test status
Simulation time 77696355566 ps
CPU time 483.11 seconds
Started Oct 15 05:24:45 AM UTC 24
Finished Oct 15 05:32:54 AM UTC 24
Peak memory 336824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663217415 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3663217415 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.300591058
Short name T455
Test name
Test status
Simulation time 55180888 ps
CPU time 1.33 seconds
Started Oct 15 05:26:41 AM UTC 24
Finished Oct 15 05:26:43 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300591058 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.300591058 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_app.494138345
Short name T480
Test name
Test status
Simulation time 11181466373 ps
CPU time 221.63 seconds
Started Oct 15 05:25:35 AM UTC 24
Finished Oct 15 05:29:20 AM UTC 24
Peak memory 289520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494138345 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.494138345 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.3864616237
Short name T687
Test name
Test status
Simulation time 17008789220 ps
CPU time 1583.99 seconds
Started Oct 15 05:25:30 AM UTC 24
Finished Oct 15 05:52:13 AM UTC 24
Peak memory 260624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864616237 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3864616237 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3793280878
Short name T450
Test name
Test status
Simulation time 373072335 ps
CPU time 14 seconds
Started Oct 15 05:25:36 AM UTC 24
Finished Oct 15 05:25:51 AM UTC 24
Peak memory 250408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793280878 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3793280878 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_error.2028935211
Short name T457
Test name
Test status
Simulation time 1539930683 ps
CPU time 61.93 seconds
Started Oct 15 05:25:52 AM UTC 24
Finished Oct 15 05:26:56 AM UTC 24
Peak memory 281120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028935211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2028935211 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.1079559624
Short name T453
Test name
Test status
Simulation time 5889277903 ps
CPU time 21.39 seconds
Started Oct 15 05:26:07 AM UTC 24
Finished Oct 15 05:26:30 AM UTC 24
Peak memory 232116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079559624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1079559624 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.1566959549
Short name T454
Test name
Test status
Simulation time 362822720 ps
CPU time 16.24 seconds
Started Oct 15 05:26:21 AM UTC 24
Finished Oct 15 05:26:40 AM UTC 24
Peak memory 254492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566959549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1566959549 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.1725613538
Short name T756
Test name
Test status
Simulation time 188151982460 ps
CPU time 2986.88 seconds
Started Oct 15 05:25:15 AM UTC 24
Finished Oct 15 06:15:34 AM UTC 24
Peak memory 1677868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725613538 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.1725613538 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.3825303335
Short name T503
Test name
Test status
Simulation time 49712894247 ps
CPU time 421.8 seconds
Started Oct 15 05:25:17 AM UTC 24
Finished Oct 15 05:32:24 AM UTC 24
Peak memory 557664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825303335 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3825303335 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload_invalid.1832482518
Short name T449
Test name
Test status
Simulation time 473496436 ps
CPU time 9.4 seconds
Started Oct 15 05:25:25 AM UTC 24
Finished Oct 15 05:25:35 AM UTC 24
Peak memory 237008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832482518 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload_invalid.1832482518 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.1116634490
Short name T448
Test name
Test status
Simulation time 1629454803 ps
CPU time 20.42 seconds
Started Oct 15 05:25:13 AM UTC 24
Finished Oct 15 05:25:34 AM UTC 24
Peak memory 238124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116634490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.1116634490 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.373022900
Short name T597
Test name
Test status
Simulation time 9597531440 ps
CPU time 952.63 seconds
Started Oct 15 05:26:31 AM UTC 24
Finished Oct 15 05:42:34 AM UTC 24
Peak memory 629796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373022900 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.373022900 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.1635817941
Short name T466
Test name
Test status
Simulation time 52008901 ps
CPU time 1.14 seconds
Started Oct 15 05:27:46 AM UTC 24
Finished Oct 15 05:27:48 AM UTC 24
Peak memory 227224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635817941 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1635817941 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_app.2845867201
Short name T472
Test name
Test status
Simulation time 3187628869 ps
CPU time 95.93 seconds
Started Oct 15 05:27:03 AM UTC 24
Finished Oct 15 05:28:41 AM UTC 24
Peak memory 258664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845867201 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2845867201 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.3189726739
Short name T498
Test name
Test status
Simulation time 12758832969 ps
CPU time 293.13 seconds
Started Oct 15 05:27:02 AM UTC 24
Finished Oct 15 05:31:59 AM UTC 24
Peak memory 242492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189726739 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3189726739 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.2995703067
Short name T484
Test name
Test status
Simulation time 11878802371 ps
CPU time 147.19 seconds
Started Oct 15 05:27:09 AM UTC 24
Finished Oct 15 05:29:39 AM UTC 24
Peak memory 274996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995703067 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.2995703067 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_error.3170475015
Short name T482
Test name
Test status
Simulation time 24765142446 ps
CPU time 136.39 seconds
Started Oct 15 05:27:14 AM UTC 24
Finished Oct 15 05:29:33 AM UTC 24
Peak memory 342632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170475015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.3170475015 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.1061416487
Short name T464
Test name
Test status
Simulation time 2054885032 ps
CPU time 12.87 seconds
Started Oct 15 05:27:26 AM UTC 24
Finished Oct 15 05:27:40 AM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061416487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1061416487 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.4238643982
Short name T63
Test name
Test status
Simulation time 63815959 ps
CPU time 1.83 seconds
Started Oct 15 05:27:42 AM UTC 24
Finished Oct 15 05:27:45 AM UTC 24
Peak memory 235884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238643982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.4238643982 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.2045875264
Short name T759
Test name
Test status
Simulation time 124375627209 ps
CPU time 3166.45 seconds
Started Oct 15 05:26:57 AM UTC 24
Finished Oct 15 06:20:19 AM UTC 24
Peak memory 1751644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045875264 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.2045875264 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.3340917075
Short name T515
Test name
Test status
Simulation time 9545302076 ps
CPU time 367.48 seconds
Started Oct 15 05:26:57 AM UTC 24
Finished Oct 15 05:33:09 AM UTC 24
Peak memory 367136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340917075 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3340917075 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload_invalid.2512226366
Short name T461
Test name
Test status
Simulation time 230527182 ps
CPU time 7.05 seconds
Started Oct 15 05:27:00 AM UTC 24
Finished Oct 15 05:27:08 AM UTC 24
Peak memory 236872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512226366 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload_invalid.2512226366 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.949326879
Short name T458
Test name
Test status
Simulation time 1885577725 ps
CPU time 14.22 seconds
Started Oct 15 05:26:44 AM UTC 24
Finished Oct 15 05:26:59 AM UTC 24
Peak memory 234428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949326879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.949326879 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.3518255797
Short name T551
Test name
Test status
Simulation time 26076635094 ps
CPU time 583.1 seconds
Started Oct 15 05:27:45 AM UTC 24
Finished Oct 15 05:37:35 AM UTC 24
Peak memory 467940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518255797 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.3518255797 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.809045643
Short name T478
Test name
Test status
Simulation time 20208046 ps
CPU time 1.15 seconds
Started Oct 15 05:29:00 AM UTC 24
Finished Oct 15 05:29:02 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809045643 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.809045643 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_app.1701937305
Short name T522
Test name
Test status
Simulation time 16949051582 ps
CPU time 326.88 seconds
Started Oct 15 05:28:40 AM UTC 24
Finished Oct 15 05:34:12 AM UTC 24
Peak memory 350772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701937305 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1701937305 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.921610030
Short name T639
Test name
Test status
Simulation time 10446477727 ps
CPU time 1092.01 seconds
Started Oct 15 05:28:35 AM UTC 24
Finished Oct 15 05:47:00 AM UTC 24
Peak memory 254764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921610030 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.921610030 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.1780680818
Short name T488
Test name
Test status
Simulation time 8961886890 ps
CPU time 89.16 seconds
Started Oct 15 05:28:42 AM UTC 24
Finished Oct 15 05:30:14 AM UTC 24
Peak memory 256676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780680818 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1780680818 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_error.1340361600
Short name T532
Test name
Test status
Simulation time 11158641232 ps
CPU time 383.72 seconds
Started Oct 15 05:28:43 AM UTC 24
Finished Oct 15 05:35:11 AM UTC 24
Peak memory 516820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340361600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1340361600 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.1546875440
Short name T477
Test name
Test status
Simulation time 5954178445 ps
CPU time 14.18 seconds
Started Oct 15 05:28:44 AM UTC 24
Finished Oct 15 05:28:59 AM UTC 24
Peak memory 230076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546875440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.1546875440 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.573903602
Short name T476
Test name
Test status
Simulation time 128004330 ps
CPU time 2.07 seconds
Started Oct 15 05:28:51 AM UTC 24
Finished Oct 15 05:28:54 AM UTC 24
Peak memory 236408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573903602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.573903602 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.399518229
Short name T658
Test name
Test status
Simulation time 14462620971 ps
CPU time 1228.69 seconds
Started Oct 15 05:28:05 AM UTC 24
Finished Oct 15 05:48:49 AM UTC 24
Peak memory 887344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399518229 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.399518229 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.2558906000
Short name T530
Test name
Test status
Simulation time 13904375433 ps
CPU time 392.66 seconds
Started Oct 15 05:28:22 AM UTC 24
Finished Oct 15 05:35:00 AM UTC 24
Peak memory 522796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558906000 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2558906000 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload_invalid.870853772
Short name T473
Test name
Test status
Simulation time 149109204 ps
CPU time 7.66 seconds
Started Oct 15 05:28:33 AM UTC 24
Finished Oct 15 05:28:42 AM UTC 24
Peak memory 235028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870853772 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload_invalid.870853772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.2753799122
Short name T471
Test name
Test status
Simulation time 3968225133 ps
CPU time 49.11 seconds
Started Oct 15 05:27:49 AM UTC 24
Finished Oct 15 05:28:39 AM UTC 24
Peak memory 234556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753799122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.2753799122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.4266548298
Short name T593
Test name
Test status
Simulation time 39567597995 ps
CPU time 788.22 seconds
Started Oct 15 05:28:55 AM UTC 24
Finished Oct 15 05:42:12 AM UTC 24
Peak memory 478228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266548298 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.4266548298 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.1762107436
Short name T194
Test name
Test status
Simulation time 48619375 ps
CPU time 1.28 seconds
Started Oct 15 04:51:08 AM UTC 24
Finished Oct 15 04:51:11 AM UTC 24
Peak memory 226864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762107436 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1762107436 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_app.2440985640
Short name T195
Test name
Test status
Simulation time 1294581652 ps
CPU time 49.59 seconds
Started Oct 15 04:50:24 AM UTC 24
Finished Oct 15 04:51:16 AM UTC 24
Peak memory 254648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440985640 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2440985640 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.835830782
Short name T200
Test name
Test status
Simulation time 1933042387 ps
CPU time 109.29 seconds
Started Oct 15 04:50:28 AM UTC 24
Finished Oct 15 04:52:20 AM UTC 24
Peak memory 266736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835830782 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.835830782 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.3544909072
Short name T308
Test name
Test status
Simulation time 71259122154 ps
CPU time 1089.51 seconds
Started Oct 15 04:49:57 AM UTC 24
Finished Oct 15 05:08:20 AM UTC 24
Peak memory 266968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544909072 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3544909072 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.4284886375
Short name T87
Test name
Test status
Simulation time 95827896 ps
CPU time 1.65 seconds
Started Oct 15 04:50:55 AM UTC 24
Finished Oct 15 04:50:57 AM UTC 24
Peak memory 230132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284886375 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.4284886375 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.2699825961
Short name T91
Test name
Test status
Simulation time 15568788 ps
CPU time 1.34 seconds
Started Oct 15 04:50:57 AM UTC 24
Finished Oct 15 04:50:59 AM UTC 24
Peak memory 226688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699825961 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2699825961 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.3003165199
Short name T196
Test name
Test status
Simulation time 14607200294 ps
CPU time 64.48 seconds
Started Oct 15 04:50:58 AM UTC 24
Finished Oct 15 04:52:04 AM UTC 24
Peak memory 236584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003165199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.3003165199 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.526769867
Short name T81
Test name
Test status
Simulation time 59550177363 ps
CPU time 230.71 seconds
Started Oct 15 04:50:30 AM UTC 24
Finished Oct 15 04:54:24 AM UTC 24
Peak memory 311912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526769867 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.526769867 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_error.299963873
Short name T70
Test name
Test status
Simulation time 68784027263 ps
CPU time 106.24 seconds
Started Oct 15 04:50:44 AM UTC 24
Finished Oct 15 04:52:32 AM UTC 24
Peak memory 336616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299963873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.299963873 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.1902208644
Short name T193
Test name
Test status
Simulation time 3333162650 ps
CPU time 14.84 seconds
Started Oct 15 04:50:52 AM UTC 24
Finished Oct 15 04:51:08 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902208644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1902208644 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.3333209780
Short name T285
Test name
Test status
Simulation time 48021906554 ps
CPU time 955.63 seconds
Started Oct 15 04:49:41 AM UTC 24
Finished Oct 15 05:05:48 AM UTC 24
Peak memory 1309404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333209780 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.3333209780 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.1647700787
Short name T36
Test name
Test status
Simulation time 2251858355 ps
CPU time 71.95 seconds
Started Oct 15 04:50:38 AM UTC 24
Finished Oct 15 04:51:52 AM UTC 24
Peak memory 254900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647700787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1647700787 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.415484519
Short name T126
Test name
Test status
Simulation time 9330009953 ps
CPU time 68.14 seconds
Started Oct 15 04:51:06 AM UTC 24
Finished Oct 15 04:52:16 AM UTC 24
Peak memory 280348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415484519 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.415484519 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.4181460454
Short name T58
Test name
Test status
Simulation time 1087827042 ps
CPU time 18.75 seconds
Started Oct 15 04:49:44 AM UTC 24
Finished Oct 15 04:50:04 AM UTC 24
Peak memory 236552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181460454 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.4181460454 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.4076299610
Short name T139
Test name
Test status
Simulation time 1625681108 ps
CPU time 21.77 seconds
Started Oct 15 04:49:40 AM UTC 24
Finished Oct 15 04:50:03 AM UTC 24
Peak memory 234424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076299610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.4076299610 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.1616115871
Short name T396
Test name
Test status
Simulation time 277121824394 ps
CPU time 1653.89 seconds
Started Oct 15 04:51:04 AM UTC 24
Finished Oct 15 05:18:57 AM UTC 24
Peak memory 681060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616115871 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1616115871 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.1865951085
Short name T59
Test name
Test status
Simulation time 379085978 ps
CPU time 3.1 seconds
Started Oct 15 04:50:19 AM UTC 24
Finished Oct 15 04:50:24 AM UTC 24
Peak memory 232428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865951085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.1865951085 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.3869015490
Short name T190
Test name
Test status
Simulation time 161726159 ps
CPU time 4.48 seconds
Started Oct 15 04:50:24 AM UTC 24
Finished Oct 15 04:50:30 AM UTC 24
Peak memory 232456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869015490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3869015490 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.1299351367
Short name T627
Test name
Test status
Simulation time 259051186931 ps
CPU time 3300.47 seconds
Started Oct 15 04:50:00 AM UTC 24
Finished Oct 15 05:45:38 AM UTC 24
Peak memory 3043924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299351367 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1299351367 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.894658502
Short name T180
Test name
Test status
Simulation time 28576544187 ps
CPU time 47.2 seconds
Started Oct 15 04:50:02 AM UTC 24
Finished Oct 15 04:50:51 AM UTC 24
Peak memory 260632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894658502 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.894658502 +enable
_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.2998939063
Short name T192
Test name
Test status
Simulation time 25964308944 ps
CPU time 37.39 seconds
Started Oct 15 04:50:03 AM UTC 24
Finished Oct 15 04:50:43 AM UTC 24
Peak memory 244252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998939063 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2998939063 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.3015075526
Short name T191
Test name
Test status
Simulation time 2009037525 ps
CPU time 31.47 seconds
Started Oct 15 04:50:04 AM UTC 24
Finished Oct 15 04:50:37 AM UTC 24
Peak memory 236476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015075526 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3015075526 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3045451398
Short name T184
Test name
Test status
Simulation time 3693656973 ps
CPU time 170.09 seconds
Started Oct 15 04:50:05 AM UTC 24
Finished Oct 15 04:52:58 AM UTC 24
Peak memory 295656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045451398 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3045451398 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.3066157727
Short name T179
Test name
Test status
Simulation time 7426854773 ps
CPU time 142.59 seconds
Started Oct 15 04:50:13 AM UTC 24
Finished Oct 15 04:52:38 AM UTC 24
Peak memory 365092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066157727 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3066157727 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.3025864215
Short name T491
Test name
Test status
Simulation time 20358870 ps
CPU time 1.25 seconds
Started Oct 15 05:30:15 AM UTC 24
Finished Oct 15 05:30:17 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025864215 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.3025864215 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_app.1310095947
Short name T490
Test name
Test status
Simulation time 462471405 ps
CPU time 36.21 seconds
Started Oct 15 05:29:38 AM UTC 24
Finished Oct 15 05:30:16 AM UTC 24
Peak memory 242292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310095947 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.1310095947 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.2524261977
Short name T519
Test name
Test status
Simulation time 2407720407 ps
CPU time 254.3 seconds
Started Oct 15 05:29:34 AM UTC 24
Finished Oct 15 05:33:52 AM UTC 24
Peak memory 242276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524261977 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2524261977 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.3084431627
Short name T495
Test name
Test status
Simulation time 13748992784 ps
CPU time 106.22 seconds
Started Oct 15 05:29:39 AM UTC 24
Finished Oct 15 05:31:28 AM UTC 24
Peak memory 309924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084431627 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.3084431627 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_error.3192651835
Short name T496
Test name
Test status
Simulation time 17334201888 ps
CPU time 107.96 seconds
Started Oct 15 05:29:49 AM UTC 24
Finished Oct 15 05:31:39 AM UTC 24
Peak memory 318056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192651835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3192651835 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.3262450008
Short name T493
Test name
Test status
Simulation time 1824131672 ps
CPU time 19.18 seconds
Started Oct 15 05:30:08 AM UTC 24
Finished Oct 15 05:30:28 AM UTC 24
Peak memory 230068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262450008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3262450008 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.624424382
Short name T739
Test name
Test status
Simulation time 71011823299 ps
CPU time 2016.96 seconds
Started Oct 15 05:29:21 AM UTC 24
Finished Oct 15 06:03:21 AM UTC 24
Peak memory 1239652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624424382 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.624424382 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.778363327
Short name T552
Test name
Test status
Simulation time 23311868377 ps
CPU time 488.29 seconds
Started Oct 15 05:29:21 AM UTC 24
Finished Oct 15 05:37:36 AM UTC 24
Peak memory 391956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778363327 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.778363327 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload_invalid.2571473770
Short name T483
Test name
Test status
Simulation time 41325184 ps
CPU time 2.44 seconds
Started Oct 15 05:29:34 AM UTC 24
Finished Oct 15 05:29:38 AM UTC 24
Peak memory 236724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571473770 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload_invalid.2571473770 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.1142499219
Short name T481
Test name
Test status
Simulation time 1264771939 ps
CPU time 28.79 seconds
Started Oct 15 05:29:03 AM UTC 24
Finished Oct 15 05:29:33 AM UTC 24
Peak memory 236536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142499219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1142499219 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.3232788491
Short name T666
Test name
Test status
Simulation time 78158485883 ps
CPU time 1161.64 seconds
Started Oct 15 05:30:15 AM UTC 24
Finished Oct 15 05:49:50 AM UTC 24
Peak memory 1174048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232788491 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3232788491 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.1801110625
Short name T499
Test name
Test status
Simulation time 34241353 ps
CPU time 1.16 seconds
Started Oct 15 05:32:00 AM UTC 24
Finished Oct 15 05:32:03 AM UTC 24
Peak memory 228364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801110625 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1801110625 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_app.3527758033
Short name T540
Test name
Test status
Simulation time 41651472200 ps
CPU time 320.89 seconds
Started Oct 15 05:30:29 AM UTC 24
Finished Oct 15 05:35:55 AM UTC 24
Peak memory 467700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527758033 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3527758033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.1149614788
Short name T545
Test name
Test status
Simulation time 4880084703 ps
CPU time 379.33 seconds
Started Oct 15 05:30:29 AM UTC 24
Finished Oct 15 05:36:54 AM UTC 24
Peak memory 242204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149614788 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1149614788 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.1002675067
Short name T508
Test name
Test status
Simulation time 24803937361 ps
CPU time 143.06 seconds
Started Oct 15 05:30:30 AM UTC 24
Finished Oct 15 05:32:56 AM UTC 24
Peak memory 334384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002675067 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.1002675067 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_error.920053930
Short name T525
Test name
Test status
Simulation time 27501613293 ps
CPU time 169.83 seconds
Started Oct 15 05:31:29 AM UTC 24
Finished Oct 15 05:34:22 AM UTC 24
Peak memory 406060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920053930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.920053930 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.3291420518
Short name T497
Test name
Test status
Simulation time 3089265387 ps
CPU time 7.31 seconds
Started Oct 15 05:31:40 AM UTC 24
Finished Oct 15 05:31:48 AM UTC 24
Peak memory 230132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291420518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3291420518 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.1365719918
Short name T77
Test name
Test status
Simulation time 67130285 ps
CPU time 2.21 seconds
Started Oct 15 05:31:49 AM UTC 24
Finished Oct 15 05:31:52 AM UTC 24
Peak memory 236360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365719918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1365719918 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.3397231492
Short name T560
Test name
Test status
Simulation time 42563357446 ps
CPU time 513.52 seconds
Started Oct 15 05:30:17 AM UTC 24
Finished Oct 15 05:38:57 AM UTC 24
Peak memory 738096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397231492 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.3397231492 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload_invalid.3058314686
Short name T494
Test name
Test status
Simulation time 118913956 ps
CPU time 6.07 seconds
Started Oct 15 05:30:22 AM UTC 24
Finished Oct 15 05:30:29 AM UTC 24
Peak memory 236904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058314686 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload_invalid.3058314686 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.3045382399
Short name T504
Test name
Test status
Simulation time 34715931552 ps
CPU time 130.26 seconds
Started Oct 15 05:30:16 AM UTC 24
Finished Oct 15 05:32:29 AM UTC 24
Peak memory 238372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045382399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3045382399 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.2160056583
Short name T613
Test name
Test status
Simulation time 22006126356 ps
CPU time 745.61 seconds
Started Oct 15 05:31:53 AM UTC 24
Finished Oct 15 05:44:27 AM UTC 24
Peak memory 594972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160056583 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2160056583 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.1089213479
Short name T512
Test name
Test status
Simulation time 29164509 ps
CPU time 1.26 seconds
Started Oct 15 05:33:01 AM UTC 24
Finished Oct 15 05:33:04 AM UTC 24
Peak memory 226824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089213479 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1089213479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_app.51457659
Short name T566
Test name
Test status
Simulation time 116456316647 ps
CPU time 400.98 seconds
Started Oct 15 05:32:30 AM UTC 24
Finished Oct 15 05:39:16 AM UTC 24
Peak memory 512628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51457659 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.51457659 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.2642977364
Short name T526
Test name
Test status
Simulation time 2805046182 ps
CPU time 127.57 seconds
Started Oct 15 05:32:25 AM UTC 24
Finished Oct 15 05:34:35 AM UTC 24
Peak memory 238180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642977364 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2642977364 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.12403812
Short name T89
Test name
Test status
Simulation time 8900631578 ps
CPU time 491.49 seconds
Started Oct 15 05:32:33 AM UTC 24
Finished Oct 15 05:40:51 AM UTC 24
Peak memory 348784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12403812 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.12403812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_error.3766433652
Short name T531
Test name
Test status
Simulation time 8205729209 ps
CPU time 142.04 seconds
Started Oct 15 05:32:38 AM UTC 24
Finished Oct 15 05:35:02 AM UTC 24
Peak memory 287328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766433652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.3766433652 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.565006031
Short name T511
Test name
Test status
Simulation time 2170166553 ps
CPU time 4.69 seconds
Started Oct 15 05:32:55 AM UTC 24
Finished Oct 15 05:33:01 AM UTC 24
Peak memory 230076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565006031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.565006031 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.434148232
Short name T510
Test name
Test status
Simulation time 118015537 ps
CPU time 2.01 seconds
Started Oct 15 05:32:57 AM UTC 24
Finished Oct 15 05:33:00 AM UTC 24
Peak memory 235956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434148232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.434148232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.1282950447
Short name T723
Test name
Test status
Simulation time 183835866203 ps
CPU time 1547.14 seconds
Started Oct 15 05:32:15 AM UTC 24
Finished Oct 15 05:58:20 AM UTC 24
Peak memory 1976928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282950447 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.1282950447 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.1599685246
Short name T561
Test name
Test status
Simulation time 3960863509 ps
CPU time 392.47 seconds
Started Oct 15 05:32:20 AM UTC 24
Finished Oct 15 05:38:57 AM UTC 24
Peak memory 344808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599685246 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1599685246 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload_invalid.1069601672
Short name T505
Test name
Test status
Simulation time 289229982 ps
CPU time 6.34 seconds
Started Oct 15 05:32:25 AM UTC 24
Finished Oct 15 05:32:32 AM UTC 24
Peak memory 236876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069601672 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload_invalid.1069601672 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.2123034703
Short name T509
Test name
Test status
Simulation time 3773029789 ps
CPU time 52.1 seconds
Started Oct 15 05:32:03 AM UTC 24
Finished Oct 15 05:32:57 AM UTC 24
Peak memory 236664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123034703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.2123034703 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.2793792251
Short name T527
Test name
Test status
Simulation time 3222758958 ps
CPU time 95.85 seconds
Started Oct 15 05:32:58 AM UTC 24
Finished Oct 15 05:34:36 AM UTC 24
Peak memory 263156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793792251 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2793792251 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.273774239
Short name T524
Test name
Test status
Simulation time 39085798 ps
CPU time 1.25 seconds
Started Oct 15 05:34:12 AM UTC 24
Finished Oct 15 05:34:15 AM UTC 24
Peak memory 228064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273774239 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.273774239 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_app.156257428
Short name T529
Test name
Test status
Simulation time 4711235198 ps
CPU time 81.2 seconds
Started Oct 15 05:33:22 AM UTC 24
Finished Oct 15 05:34:45 AM UTC 24
Peak memory 252720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156257428 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.156257428 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.4111418697
Short name T676
Test name
Test status
Simulation time 10716060577 ps
CPU time 1085.87 seconds
Started Oct 15 05:33:10 AM UTC 24
Finished Oct 15 05:51:28 AM UTC 24
Peak memory 254712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111418697 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.4111418697 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.641297290
Short name T523
Test name
Test status
Simulation time 7342690717 ps
CPU time 43.16 seconds
Started Oct 15 05:33:29 AM UTC 24
Finished Oct 15 05:34:14 AM UTC 24
Peak memory 254512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641297290 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.641297290 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_error.3681859673
Short name T554
Test name
Test status
Simulation time 80504916769 ps
CPU time 280.09 seconds
Started Oct 15 05:33:31 AM UTC 24
Finished Oct 15 05:38:15 AM UTC 24
Peak memory 414308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681859673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3681859673 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.2655393975
Short name T520
Test name
Test status
Simulation time 338236175 ps
CPU time 5.48 seconds
Started Oct 15 05:33:53 AM UTC 24
Finished Oct 15 05:34:00 AM UTC 24
Peak memory 230004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655393975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2655393975 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.4152905326
Short name T521
Test name
Test status
Simulation time 47214124 ps
CPU time 2.14 seconds
Started Oct 15 05:34:00 AM UTC 24
Finished Oct 15 05:34:03 AM UTC 24
Peak memory 234368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152905326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.4152905326 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.3352391534
Short name T749
Test name
Test status
Simulation time 80550003925 ps
CPU time 2207.88 seconds
Started Oct 15 05:33:04 AM UTC 24
Finished Oct 15 06:10:17 AM UTC 24
Peak memory 1380920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352391534 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.3352391534 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.2670787399
Short name T573
Test name
Test status
Simulation time 18924217102 ps
CPU time 397.08 seconds
Started Oct 15 05:33:08 AM UTC 24
Finished Oct 15 05:39:50 AM UTC 24
Peak memory 367120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670787399 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.2670787399 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload_invalid.1551110105
Short name T516
Test name
Test status
Simulation time 1239886634 ps
CPU time 11.6 seconds
Started Oct 15 05:33:09 AM UTC 24
Finished Oct 15 05:33:21 AM UTC 24
Peak memory 236924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551110105 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload_invalid.1551110105 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.1165409989
Short name T513
Test name
Test status
Simulation time 474821092 ps
CPU time 4.24 seconds
Started Oct 15 05:33:01 AM UTC 24
Finished Oct 15 05:33:07 AM UTC 24
Peak memory 238168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165409989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.1165409989 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.51012881
Short name T542
Test name
Test status
Simulation time 3987135013 ps
CPU time 124.68 seconds
Started Oct 15 05:34:04 AM UTC 24
Finished Oct 15 05:36:11 AM UTC 24
Peak memory 318540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51012881 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.51012881 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.3410902989
Short name T536
Test name
Test status
Simulation time 16074634 ps
CPU time 1.29 seconds
Started Oct 15 05:35:16 AM UTC 24
Finished Oct 15 05:35:19 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410902989 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3410902989 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_app.992352266
Short name T578
Test name
Test status
Simulation time 25022046565 ps
CPU time 378.06 seconds
Started Oct 15 05:34:42 AM UTC 24
Finished Oct 15 05:41:05 AM UTC 24
Peak memory 488020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992352266 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.992352266 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.1371612144
Short name T649
Test name
Test status
Simulation time 62161866368 ps
CPU time 789.85 seconds
Started Oct 15 05:34:37 AM UTC 24
Finished Oct 15 05:47:56 AM UTC 24
Peak memory 256616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371612144 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1371612144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.3947205986
Short name T591
Test name
Test status
Simulation time 65732882576 ps
CPU time 424.91 seconds
Started Oct 15 05:34:46 AM UTC 24
Finished Oct 15 05:41:57 AM UTC 24
Peak memory 467572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947205986 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3947205986 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_error.3405211938
Short name T577
Test name
Test status
Simulation time 8654358510 ps
CPU time 350.5 seconds
Started Oct 15 05:35:01 AM UTC 24
Finished Oct 15 05:40:56 AM UTC 24
Peak memory 465444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405211938 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.3405211938 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.3761579277
Short name T535
Test name
Test status
Simulation time 2301038186 ps
CPU time 11.04 seconds
Started Oct 15 05:35:03 AM UTC 24
Finished Oct 15 05:35:15 AM UTC 24
Peak memory 230052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761579277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3761579277 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.4288563556
Short name T533
Test name
Test status
Simulation time 27367468 ps
CPU time 2.04 seconds
Started Oct 15 05:35:12 AM UTC 24
Finished Oct 15 05:35:15 AM UTC 24
Peak memory 236476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288563556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.4288563556 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.4125782026
Short name T538
Test name
Test status
Simulation time 3310446993 ps
CPU time 72.93 seconds
Started Oct 15 05:34:16 AM UTC 24
Finished Oct 15 05:35:30 AM UTC 24
Peak memory 260652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125782026 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.4125782026 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.3464961100
Short name T583
Test name
Test status
Simulation time 5323732498 ps
CPU time 423.05 seconds
Started Oct 15 05:34:23 AM UTC 24
Finished Oct 15 05:41:31 AM UTC 24
Peak memory 379632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464961100 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3464961100 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload_invalid.312016171
Short name T528
Test name
Test status
Simulation time 54645983 ps
CPU time 4.72 seconds
Started Oct 15 05:34:36 AM UTC 24
Finished Oct 15 05:34:42 AM UTC 24
Peak memory 236876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312016171 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload_invalid.312016171 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.3355976671
Short name T534
Test name
Test status
Simulation time 4967092981 ps
CPU time 59.23 seconds
Started Oct 15 05:34:14 AM UTC 24
Finished Oct 15 05:35:15 AM UTC 24
Peak memory 238180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355976671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.3355976671 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.793038842
Short name T584
Test name
Test status
Simulation time 54176464038 ps
CPU time 369.78 seconds
Started Oct 15 05:35:16 AM UTC 24
Finished Oct 15 05:41:31 AM UTC 24
Peak memory 386032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793038842 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.793038842 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.3897626341
Short name T547
Test name
Test status
Simulation time 18028671 ps
CPU time 1.21 seconds
Started Oct 15 05:36:57 AM UTC 24
Finished Oct 15 05:36:59 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897626341 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3897626341 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_app.94841428
Short name T574
Test name
Test status
Simulation time 16828915924 ps
CPU time 238.47 seconds
Started Oct 15 05:35:56 AM UTC 24
Finished Oct 15 05:39:58 AM UTC 24
Peak memory 313976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94841428 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.94841428 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.3580109553
Short name T549
Test name
Test status
Simulation time 2715638752 ps
CPU time 93.08 seconds
Started Oct 15 05:35:43 AM UTC 24
Finished Oct 15 05:37:18 AM UTC 24
Peak memory 254500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580109553 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3580109553 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.938662712
Short name T555
Test name
Test status
Simulation time 2912178833 ps
CPU time 133.44 seconds
Started Oct 15 05:36:10 AM UTC 24
Finished Oct 15 05:38:26 AM UTC 24
Peak memory 274992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938662712 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.938662712 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_error.2509153341
Short name T572
Test name
Test status
Simulation time 2595707118 ps
CPU time 211.2 seconds
Started Oct 15 05:36:12 AM UTC 24
Finished Oct 15 05:39:47 AM UTC 24
Peak memory 313956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509153341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2509153341 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.4122105064
Short name T544
Test name
Test status
Simulation time 1881570984 ps
CPU time 13.06 seconds
Started Oct 15 05:36:37 AM UTC 24
Finished Oct 15 05:36:52 AM UTC 24
Peak memory 230056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122105064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.4122105064 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.1191318760
Short name T546
Test name
Test status
Simulation time 32714740 ps
CPU time 2 seconds
Started Oct 15 05:36:52 AM UTC 24
Finished Oct 15 05:36:55 AM UTC 24
Peak memory 233948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191318760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1191318760 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.973742194
Short name T564
Test name
Test status
Simulation time 2735260663 ps
CPU time 230.39 seconds
Started Oct 15 05:35:20 AM UTC 24
Finished Oct 15 05:39:14 AM UTC 24
Peak memory 363040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973742194 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.973742194 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.1378543925
Short name T543
Test name
Test status
Simulation time 10308170307 ps
CPU time 71.48 seconds
Started Oct 15 05:35:24 AM UTC 24
Finished Oct 15 05:36:37 AM UTC 24
Peak memory 287528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378543925 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1378543925 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload_invalid.459873497
Short name T539
Test name
Test status
Simulation time 681427944 ps
CPU time 9.78 seconds
Started Oct 15 05:35:31 AM UTC 24
Finished Oct 15 05:35:42 AM UTC 24
Peak memory 238460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459873497 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload_invalid.459873497 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.4086352706
Short name T548
Test name
Test status
Simulation time 3959387437 ps
CPU time 111.59 seconds
Started Oct 15 05:35:17 AM UTC 24
Finished Oct 15 05:37:10 AM UTC 24
Peak memory 238120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086352706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.4086352706 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.732168213
Short name T712
Test name
Test status
Simulation time 70440951790 ps
CPU time 1140.7 seconds
Started Oct 15 05:36:55 AM UTC 24
Finished Oct 15 05:56:09 AM UTC 24
Peak memory 1280748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732168213 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.732168213 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.1079189182
Short name T559
Test name
Test status
Simulation time 59353088 ps
CPU time 1.37 seconds
Started Oct 15 05:38:54 AM UTC 24
Finished Oct 15 05:38:56 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079189182 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1079189182 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_app.3972206205
Short name T600
Test name
Test status
Simulation time 20069665060 ps
CPU time 308.49 seconds
Started Oct 15 05:37:37 AM UTC 24
Finished Oct 15 05:42:50 AM UTC 24
Peak memory 440884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972206205 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3972206205 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.2538250052
Short name T604
Test name
Test status
Simulation time 7164275429 ps
CPU time 373.09 seconds
Started Oct 15 05:37:36 AM UTC 24
Finished Oct 15 05:43:54 AM UTC 24
Peak memory 248500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538250052 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2538250052 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.2433086063
Short name T628
Test name
Test status
Simulation time 8221996668 ps
CPU time 463.67 seconds
Started Oct 15 05:37:48 AM UTC 24
Finished Oct 15 05:45:38 AM UTC 24
Peak memory 359020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433086063 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.2433086063 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_error.1572223558
Short name T634
Test name
Test status
Simulation time 115639764174 ps
CPU time 479.19 seconds
Started Oct 15 05:38:17 AM UTC 24
Finished Oct 15 05:46:22 AM UTC 24
Peak memory 647780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572223558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.1572223558 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.566235579
Short name T558
Test name
Test status
Simulation time 9340470964 ps
CPU time 25.57 seconds
Started Oct 15 05:38:27 AM UTC 24
Finished Oct 15 05:38:54 AM UTC 24
Peak memory 232176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566235579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.566235579 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.2007664656
Short name T562
Test name
Test status
Simulation time 1057085861 ps
CPU time 19.64 seconds
Started Oct 15 05:38:46 AM UTC 24
Finished Oct 15 05:39:07 AM UTC 24
Peak memory 253828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007664656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2007664656 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.1053676004
Short name T731
Test name
Test status
Simulation time 52592744693 ps
CPU time 1405.19 seconds
Started Oct 15 05:37:11 AM UTC 24
Finished Oct 15 06:00:52 AM UTC 24
Peak memory 1669744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053676004 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.1053676004 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.1013008624
Short name T623
Test name
Test status
Simulation time 15348050833 ps
CPU time 481.64 seconds
Started Oct 15 05:37:19 AM UTC 24
Finished Oct 15 05:45:27 AM UTC 24
Peak memory 631396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013008624 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1013008624 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload_invalid.1989156697
Short name T553
Test name
Test status
Simulation time 1342969388 ps
CPU time 11.21 seconds
Started Oct 15 05:37:35 AM UTC 24
Finished Oct 15 05:37:47 AM UTC 24
Peak memory 236940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989156697 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload_invalid.1989156697 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.2196219429
Short name T550
Test name
Test status
Simulation time 6869956679 ps
CPU time 33.49 seconds
Started Oct 15 05:37:00 AM UTC 24
Finished Oct 15 05:37:34 AM UTC 24
Peak memory 236652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196219429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2196219429 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.1921934210
Short name T674
Test name
Test status
Simulation time 54561619898 ps
CPU time 724.16 seconds
Started Oct 15 05:38:50 AM UTC 24
Finished Oct 15 05:51:03 AM UTC 24
Peak memory 451624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921934210 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1921934210 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.172796439
Short name T571
Test name
Test status
Simulation time 44888897 ps
CPU time 1.17 seconds
Started Oct 15 05:39:33 AM UTC 24
Finished Oct 15 05:39:35 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172796439 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.172796439 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_app.888959987
Short name T615
Test name
Test status
Simulation time 12045249096 ps
CPU time 316.97 seconds
Started Oct 15 05:39:14 AM UTC 24
Finished Oct 15 05:44:36 AM UTC 24
Peak memory 447128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888959987 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.888959987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.4413344
Short name T727
Test name
Test status
Simulation time 87419782279 ps
CPU time 1190.92 seconds
Started Oct 15 05:39:08 AM UTC 24
Finished Oct 15 05:59:13 AM UTC 24
Peak memory 254560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4413344 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.4413344 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.1748745024
Short name T567
Test name
Test status
Simulation time 545640715 ps
CPU time 3.34 seconds
Started Oct 15 05:39:15 AM UTC 24
Finished Oct 15 05:39:19 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748745024 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.1748745024 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_error.1852103799
Short name T603
Test name
Test status
Simulation time 59318827529 ps
CPU time 264.46 seconds
Started Oct 15 05:39:17 AM UTC 24
Finished Oct 15 05:43:45 AM UTC 24
Peak memory 439024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852103799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.1852103799 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.3441513971
Short name T568
Test name
Test status
Simulation time 118119532 ps
CPU time 2.48 seconds
Started Oct 15 05:39:20 AM UTC 24
Finished Oct 15 05:39:23 AM UTC 24
Peak memory 229924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441513971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3441513971 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.2439275555
Short name T569
Test name
Test status
Simulation time 41828148 ps
CPU time 2.03 seconds
Started Oct 15 05:39:24 AM UTC 24
Finished Oct 15 05:39:27 AM UTC 24
Peak memory 234312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439275555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.2439275555 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.229923639
Short name T758
Test name
Test status
Simulation time 995050507027 ps
CPU time 2366.52 seconds
Started Oct 15 05:38:58 AM UTC 24
Finished Oct 15 06:18:52 AM UTC 24
Peak memory 2542248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229923639 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.229923639 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.1492960678
Short name T601
Test name
Test status
Simulation time 19313900799 ps
CPU time 237.15 seconds
Started Oct 15 05:38:58 AM UTC 24
Finished Oct 15 05:42:59 AM UTC 24
Peak memory 387684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492960678 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.1492960678 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload_invalid.1589053539
Short name T565
Test name
Test status
Simulation time 125748967 ps
CPU time 5.27 seconds
Started Oct 15 05:39:07 AM UTC 24
Finished Oct 15 05:39:14 AM UTC 24
Peak memory 234832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589053539 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload_invalid.1589053539 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.3238299118
Short name T570
Test name
Test status
Simulation time 717056803 ps
CPU time 33.08 seconds
Started Oct 15 05:38:57 AM UTC 24
Finished Oct 15 05:39:32 AM UTC 24
Peak memory 234424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238299118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3238299118 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.2888634832
Short name T668
Test name
Test status
Simulation time 7244089128 ps
CPU time 632.24 seconds
Started Oct 15 05:39:28 AM UTC 24
Finished Oct 15 05:50:08 AM UTC 24
Peak memory 271512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888634832 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2888634832 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.82512308
Short name T582
Test name
Test status
Simulation time 38658446 ps
CPU time 1.22 seconds
Started Oct 15 05:41:28 AM UTC 24
Finished Oct 15 05:41:31 AM UTC 24
Peak memory 228612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82512308 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10
_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.82512308 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_app.119988890
Short name T581
Test name
Test status
Simulation time 4015795769 ps
CPU time 70.92 seconds
Started Oct 15 05:40:15 AM UTC 24
Finished Oct 15 05:41:27 AM UTC 24
Peak memory 272936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119988890 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.119988890 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.1123202744
Short name T744
Test name
Test status
Simulation time 102814505801 ps
CPU time 1563.02 seconds
Started Oct 15 05:40:05 AM UTC 24
Finished Oct 15 06:06:26 AM UTC 24
Peak memory 275180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123202744 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.1123202744 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.2512039868
Short name T609
Test name
Test status
Simulation time 25496201339 ps
CPU time 191.78 seconds
Started Oct 15 05:40:52 AM UTC 24
Finished Oct 15 05:44:07 AM UTC 24
Peak memory 293452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512039868 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2512039868 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_error.2329285776
Short name T653
Test name
Test status
Simulation time 13018659072 ps
CPU time 419.37 seconds
Started Oct 15 05:40:57 AM UTC 24
Finished Oct 15 05:48:02 AM UTC 24
Peak memory 586316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329285776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2329285776 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.2054677913
Short name T579
Test name
Test status
Simulation time 142073783 ps
CPU time 1.95 seconds
Started Oct 15 05:41:06 AM UTC 24
Finished Oct 15 05:41:09 AM UTC 24
Peak memory 230012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054677913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.2054677913 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.2036832621
Short name T580
Test name
Test status
Simulation time 61758517 ps
CPU time 2.09 seconds
Started Oct 15 05:41:10 AM UTC 24
Finished Oct 15 05:41:13 AM UTC 24
Peak memory 236416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036832621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2036832621 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.3675706647
Short name T755
Test name
Test status
Simulation time 346604005818 ps
CPU time 2096.26 seconds
Started Oct 15 05:39:47 AM UTC 24
Finished Oct 15 06:15:06 AM UTC 24
Peak memory 2349612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675706647 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.3675706647 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.2189440450
Short name T640
Test name
Test status
Simulation time 22666544981 ps
CPU time 428.96 seconds
Started Oct 15 05:39:50 AM UTC 24
Finished Oct 15 05:47:05 AM UTC 24
Peak memory 391712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189440450 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.2189440450 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload_invalid.71842101
Short name T575
Test name
Test status
Simulation time 80274694 ps
CPU time 4.72 seconds
Started Oct 15 05:39:58 AM UTC 24
Finished Oct 15 05:40:04 AM UTC 24
Peak memory 234620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71842101 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload_invalid.71842101 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.1337974117
Short name T588
Test name
Test status
Simulation time 43145124280 ps
CPU time 124.88 seconds
Started Oct 15 05:39:36 AM UTC 24
Finished Oct 15 05:41:43 AM UTC 24
Peak memory 238120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337974117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.1337974117 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.3353506584
Short name T763
Test name
Test status
Simulation time 270092151003 ps
CPU time 3126.32 seconds
Started Oct 15 05:41:14 AM UTC 24
Finished Oct 15 06:33:55 AM UTC 24
Peak memory 1389472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353506584 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.3353506584 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.186572906
Short name T595
Test name
Test status
Simulation time 18140204 ps
CPU time 1.31 seconds
Started Oct 15 05:42:15 AM UTC 24
Finished Oct 15 05:42:17 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186572906 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.186572906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_app.1055727670
Short name T612
Test name
Test status
Simulation time 6486599427 ps
CPU time 156.97 seconds
Started Oct 15 05:41:44 AM UTC 24
Finished Oct 15 05:44:24 AM UTC 24
Peak memory 363056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055727670 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.1055727670 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.1543495456
Short name T720
Test name
Test status
Simulation time 93091211414 ps
CPU time 947.98 seconds
Started Oct 15 05:41:37 AM UTC 24
Finished Oct 15 05:57:36 AM UTC 24
Peak memory 262764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543495456 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1543495456 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.1273841790
Short name T645
Test name
Test status
Simulation time 12993283570 ps
CPU time 334.11 seconds
Started Oct 15 05:41:46 AM UTC 24
Finished Oct 15 05:47:25 AM UTC 24
Peak memory 490208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273841790 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1273841790 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_error.3147736133
Short name T616
Test name
Test status
Simulation time 5695750647 ps
CPU time 176.61 seconds
Started Oct 15 05:41:46 AM UTC 24
Finished Oct 15 05:44:46 AM UTC 24
Peak memory 299680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147736133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3147736133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.793694436
Short name T592
Test name
Test status
Simulation time 2692825561 ps
CPU time 9.27 seconds
Started Oct 15 05:41:57 AM UTC 24
Finished Oct 15 05:42:08 AM UTC 24
Peak memory 232120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793694436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.793694436 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.2069856104
Short name T594
Test name
Test status
Simulation time 118569022 ps
CPU time 4.41 seconds
Started Oct 15 05:42:08 AM UTC 24
Finished Oct 15 05:42:14 AM UTC 24
Peak memory 238236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069856104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2069856104 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.1537113070
Short name T767
Test name
Test status
Simulation time 1085598019888 ps
CPU time 4388.79 seconds
Started Oct 15 05:41:33 AM UTC 24
Finished Oct 15 06:55:30 AM UTC 24
Peak memory 4078296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537113070 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.1537113070 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.1276044397
Short name T636
Test name
Test status
Simulation time 68083488702 ps
CPU time 297.87 seconds
Started Oct 15 05:41:33 AM UTC 24
Finished Oct 15 05:46:34 AM UTC 24
Peak memory 473672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276044397 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1276044397 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload_invalid.2637498612
Short name T590
Test name
Test status
Simulation time 1000855263 ps
CPU time 10.82 seconds
Started Oct 15 05:41:34 AM UTC 24
Finished Oct 15 05:41:46 AM UTC 24
Peak memory 236936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637498612 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload_invalid.2637498612 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.3198481129
Short name T589
Test name
Test status
Simulation time 1381025120 ps
CPU time 12.69 seconds
Started Oct 15 05:41:31 AM UTC 24
Finished Oct 15 05:41:45 AM UTC 24
Peak memory 238116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198481129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.3198481129 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.2949449572
Short name T611
Test name
Test status
Simulation time 8709289792 ps
CPU time 126.77 seconds
Started Oct 15 05:42:13 AM UTC 24
Finished Oct 15 05:44:22 AM UTC 24
Peak memory 275484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949449572 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2949449572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.3591997905
Short name T202
Test name
Test status
Simulation time 42800241 ps
CPU time 1.27 seconds
Started Oct 15 04:52:31 AM UTC 24
Finished Oct 15 04:52:34 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591997905 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3591997905 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_app.2383660561
Short name T235
Test name
Test status
Simulation time 13253920735 ps
CPU time 390.35 seconds
Started Oct 15 04:52:06 AM UTC 24
Finished Oct 15 04:58:42 AM UTC 24
Peak memory 344624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383660561 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2383660561 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.766236541
Short name T207
Test name
Test status
Simulation time 4672504901 ps
CPU time 96.64 seconds
Started Oct 15 04:52:08 AM UTC 24
Finished Oct 15 04:53:47 AM UTC 24
Peak memory 299568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766236541 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.766236541 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.2812867973
Short name T148
Test name
Test status
Simulation time 177399525276 ps
CPU time 954.28 seconds
Started Oct 15 04:51:20 AM UTC 24
Finished Oct 15 05:07:25 AM UTC 24
Peak memory 252460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812867973 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.2812867973 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.1807691871
Short name T203
Test name
Test status
Simulation time 1035322209 ps
CPU time 24.72 seconds
Started Oct 15 04:52:17 AM UTC 24
Finished Oct 15 04:52:43 AM UTC 24
Peak memory 248168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807691871 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1807691871 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.2790568601
Short name T93
Test name
Test status
Simulation time 24368841 ps
CPU time 1.23 seconds
Started Oct 15 04:52:20 AM UTC 24
Finished Oct 15 04:52:22 AM UTC 24
Peak memory 228608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790568601 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2790568601 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.1394798662
Short name T205
Test name
Test status
Simulation time 13724662249 ps
CPU time 74.06 seconds
Started Oct 15 04:52:23 AM UTC 24
Finished Oct 15 04:53:39 AM UTC 24
Peak memory 238116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394798662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1394798662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3408326259
Short name T209
Test name
Test status
Simulation time 2806540132 ps
CPU time 98.03 seconds
Started Oct 15 04:52:10 AM UTC 24
Finished Oct 15 04:53:50 AM UTC 24
Peak memory 268908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408326259 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3408326259 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_error.3868210560
Short name T25
Test name
Test status
Simulation time 3371371435 ps
CPU time 117.87 seconds
Started Oct 15 04:52:11 AM UTC 24
Finished Oct 15 04:54:11 AM UTC 24
Peak memory 328292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868210560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.3868210560 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.3778013489
Short name T201
Test name
Test status
Simulation time 2772289314 ps
CPU time 9.19 seconds
Started Oct 15 04:52:15 AM UTC 24
Finished Oct 15 04:52:25 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778013489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.3778013489 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.2953458976
Short name T44
Test name
Test status
Simulation time 77280428 ps
CPU time 2.11 seconds
Started Oct 15 04:52:26 AM UTC 24
Finished Oct 15 04:52:29 AM UTC 24
Peak memory 234320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953458976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2953458976 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.504546280
Short name T586
Test name
Test status
Simulation time 393263885369 ps
CPU time 2988.46 seconds
Started Oct 15 04:51:11 AM UTC 24
Finished Oct 15 05:41:32 AM UTC 24
Peak memory 3172972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504546280 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.504546280 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.3853766452
Short name T32
Test name
Test status
Simulation time 45457766930 ps
CPU time 161.92 seconds
Started Oct 15 04:52:11 AM UTC 24
Finished Oct 15 04:54:56 AM UTC 24
Peak memory 332972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853766452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3853766452 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.2034143826
Short name T127
Test name
Test status
Simulation time 2794834140 ps
CPU time 46.31 seconds
Started Oct 15 04:52:30 AM UTC 24
Finished Oct 15 04:53:19 AM UTC 24
Peak memory 280300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034143826 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2034143826 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.3256409221
Short name T240
Test name
Test status
Simulation time 54385769077 ps
CPU time 464.04 seconds
Started Oct 15 04:51:13 AM UTC 24
Finished Oct 15 04:59:03 AM UTC 24
Peak memory 600684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256409221 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3256409221 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload_invalid.3832126263
Short name T43
Test name
Test status
Simulation time 406061584 ps
CPU time 5.54 seconds
Started Oct 15 04:51:17 AM UTC 24
Finished Oct 15 04:51:23 AM UTC 24
Peak memory 234796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832126263 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload_invalid.3832126263 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.504543167
Short name T186
Test name
Test status
Simulation time 6978438145 ps
CPU time 95.31 seconds
Started Oct 15 04:51:09 AM UTC 24
Finished Oct 15 04:52:47 AM UTC 24
Peak memory 240240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504543167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.504543167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.1339102240
Short name T745
Test name
Test status
Simulation time 944002406553 ps
CPU time 4413.65 seconds
Started Oct 15 04:52:28 AM UTC 24
Finished Oct 15 06:06:52 AM UTC 24
Peak memory 1743980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339102240 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1339102240 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.4167168798
Short name T197
Test name
Test status
Simulation time 39505711 ps
CPU time 3.1 seconds
Started Oct 15 04:52:02 AM UTC 24
Finished Oct 15 04:52:07 AM UTC 24
Peak memory 232424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167168798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.4167168798 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.3021769946
Short name T198
Test name
Test status
Simulation time 54022130 ps
CPU time 3.43 seconds
Started Oct 15 04:52:06 AM UTC 24
Finished Oct 15 04:52:10 AM UTC 24
Peak memory 232392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021769946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vecto
rs_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3021769946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.18947116
Short name T182
Test name
Test status
Simulation time 1134407298 ps
CPU time 44.95 seconds
Started Oct 15 04:51:24 AM UTC 24
Finished Oct 15 04:52:10 AM UTC 24
Peak memory 237160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18947116 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.18947116 +enable_m
asking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.2817822029
Short name T518
Test name
Test status
Simulation time 61989059643 ps
CPU time 2485.46 seconds
Started Oct 15 04:51:36 AM UTC 24
Finished Oct 15 05:33:30 AM UTC 24
Peak memory 3015252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817822029 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.2817822029 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.1150096178
Short name T199
Test name
Test status
Simulation time 1426741637 ps
CPU time 35.01 seconds
Started Oct 15 04:51:38 AM UTC 24
Finished Oct 15 04:52:15 AM UTC 24
Peak memory 244256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150096178 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.1150096178 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.3480793280
Short name T336
Test name
Test status
Simulation time 19778248124 ps
CPU time 1172.22 seconds
Started Oct 15 04:51:44 AM UTC 24
Finished Oct 15 05:11:30 AM UTC 24
Peak memory 715212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480793280 -assert nopostp
roc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3480793280 +enab
le_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.2483315865
Short name T221
Test name
Test status
Simulation time 9693635705 ps
CPU time 241.84 seconds
Started Oct 15 04:51:53 AM UTC 24
Finished Oct 15 04:55:59 AM UTC 24
Peak memory 446916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483315865 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.2483315865 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.3025092439
Short name T247
Test name
Test status
Simulation time 24435492364 ps
CPU time 523.11 seconds
Started Oct 15 04:51:56 AM UTC 24
Finished Oct 15 05:00:47 AM UTC 24
Peak memory 371292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025092439 -assert nopost
proc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3025092439 +e
nable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.627210139
Short name T607
Test name
Test status
Simulation time 35232304 ps
CPU time 1.27 seconds
Started Oct 15 05:44:03 AM UTC 24
Finished Oct 15 05:44:05 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627210139 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.627210139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_app.1012934834
Short name T670
Test name
Test status
Simulation time 16152350068 ps
CPU time 433.09 seconds
Started Oct 15 05:42:51 AM UTC 24
Finished Oct 15 05:50:10 AM UTC 24
Peak memory 549452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012934834 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1012934834 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.2614103074
Short name T733
Test name
Test status
Simulation time 44324812635 ps
CPU time 1140.99 seconds
Started Oct 15 05:42:46 AM UTC 24
Finished Oct 15 06:02:00 AM UTC 24
Peak memory 256616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614103074 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2614103074 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.640804204
Short name T657
Test name
Test status
Simulation time 161532728644 ps
CPU time 338.94 seconds
Started Oct 15 05:43:00 AM UTC 24
Finished Oct 15 05:48:44 AM UTC 24
Peak memory 492128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640804204 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.640804204 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_error.3900855643
Short name T643
Test name
Test status
Simulation time 12248882392 ps
CPU time 208.26 seconds
Started Oct 15 05:43:44 AM UTC 24
Finished Oct 15 05:47:15 AM UTC 24
Peak memory 385576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900855643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3900855643 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.147386328
Short name T606
Test name
Test status
Simulation time 1099862320 ps
CPU time 14.53 seconds
Started Oct 15 05:43:47 AM UTC 24
Finished Oct 15 05:44:03 AM UTC 24
Peak memory 230140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147386328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.147386328 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.828135320
Short name T605
Test name
Test status
Simulation time 117867230 ps
CPU time 2.28 seconds
Started Oct 15 05:43:55 AM UTC 24
Finished Oct 15 05:43:58 AM UTC 24
Peak memory 236556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828135320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.828135320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.3886111680
Short name T769
Test name
Test status
Simulation time 454607873731 ps
CPU time 4974.04 seconds
Started Oct 15 05:42:27 AM UTC 24
Finished Oct 15 07:06:17 AM UTC 24
Peak memory 4545224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886111680 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.3886111680 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.4035231747
Short name T626
Test name
Test status
Simulation time 3323922312 ps
CPU time 174.86 seconds
Started Oct 15 05:42:35 AM UTC 24
Finished Oct 15 05:45:33 AM UTC 24
Peak memory 293476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035231747 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.4035231747 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload_invalid.3224244440
Short name T599
Test name
Test status
Simulation time 227965317 ps
CPU time 5.19 seconds
Started Oct 15 05:42:39 AM UTC 24
Finished Oct 15 05:42:45 AM UTC 24
Peak memory 236808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224244440 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload_invalid.3224244440 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.3695310531
Short name T608
Test name
Test status
Simulation time 6617904387 ps
CPU time 105.39 seconds
Started Oct 15 05:42:18 AM UTC 24
Finished Oct 15 05:44:05 AM UTC 24
Peak memory 238188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695310531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3695310531 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.2107088753
Short name T716
Test name
Test status
Simulation time 293978975954 ps
CPU time 765.32 seconds
Started Oct 15 05:43:59 AM UTC 24
Finished Oct 15 05:56:54 AM UTC 24
Peak memory 680484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107088753 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2107088753 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.1376981186
Short name T620
Test name
Test status
Simulation time 29943152 ps
CPU time 1.29 seconds
Started Oct 15 05:44:50 AM UTC 24
Finished Oct 15 05:44:53 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376981186 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1376981186 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_app.2130892821
Short name T622
Test name
Test status
Simulation time 7232864871 ps
CPU time 55.49 seconds
Started Oct 15 05:44:25 AM UTC 24
Finished Oct 15 05:45:22 AM UTC 24
Peak memory 272952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130892821 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2130892821 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.3003382762
Short name T633
Test name
Test status
Simulation time 8311249460 ps
CPU time 95.79 seconds
Started Oct 15 05:44:23 AM UTC 24
Finished Oct 15 05:46:00 AM UTC 24
Peak memory 248620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003382762 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3003382762 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.3655658078
Short name T650
Test name
Test status
Simulation time 31849686090 ps
CPU time 204.82 seconds
Started Oct 15 05:44:29 AM UTC 24
Finished Oct 15 05:47:57 AM UTC 24
Peak memory 326380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655658078 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.3655658078 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_error.3059453890
Short name T656
Test name
Test status
Simulation time 11585410575 ps
CPU time 219.45 seconds
Started Oct 15 05:44:34 AM UTC 24
Finished Oct 15 05:48:17 AM UTC 24
Peak memory 320240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059453890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3059453890 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.860138814
Short name T617
Test name
Test status
Simulation time 1976510548 ps
CPU time 9.2 seconds
Started Oct 15 05:44:37 AM UTC 24
Finished Oct 15 05:44:47 AM UTC 24
Peak memory 230072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860138814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.860138814 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.3020651593
Short name T618
Test name
Test status
Simulation time 49363797 ps
CPU time 2.39 seconds
Started Oct 15 05:44:46 AM UTC 24
Finished Oct 15 05:44:50 AM UTC 24
Peak memory 234288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020651593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3020651593 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.769623204
Short name T689
Test name
Test status
Simulation time 8424611186 ps
CPU time 490.33 seconds
Started Oct 15 05:44:06 AM UTC 24
Finished Oct 15 05:52:23 AM UTC 24
Peak memory 483944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769623204 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.769623204 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.1163426983
Short name T624
Test name
Test status
Simulation time 4498490438 ps
CPU time 81.31 seconds
Started Oct 15 05:44:07 AM UTC 24
Finished Oct 15 05:45:30 AM UTC 24
Peak memory 258736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163426983 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1163426983 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload_invalid.1360424361
Short name T614
Test name
Test status
Simulation time 1149703859 ps
CPU time 11.43 seconds
Started Oct 15 05:44:20 AM UTC 24
Finished Oct 15 05:44:33 AM UTC 24
Peak memory 237072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360424361 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload_invalid.1360424361 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.412163129
Short name T610
Test name
Test status
Simulation time 1021371945 ps
CPU time 11.91 seconds
Started Oct 15 05:44:06 AM UTC 24
Finished Oct 15 05:44:19 AM UTC 24
Peak memory 234400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412163129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.412163129 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.2102983064
Short name T752
Test name
Test status
Simulation time 20401697968 ps
CPU time 1657.49 seconds
Started Oct 15 05:44:48 AM UTC 24
Finished Oct 15 06:12:45 AM UTC 24
Peak memory 744548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102983064 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.2102983064 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.1183800376
Short name T632
Test name
Test status
Simulation time 34901832 ps
CPU time 1.04 seconds
Started Oct 15 05:45:52 AM UTC 24
Finished Oct 15 05:45:54 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183800376 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1183800376 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_app.3496802457
Short name T585
Test name
Test status
Simulation time 35698697840 ps
CPU time 278.43 seconds
Started Oct 15 05:45:31 AM UTC 24
Finished Oct 15 05:50:14 AM UTC 24
Peak memory 399980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496802457 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3496802457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.1029941272
Short name T734
Test name
Test status
Simulation time 20096719109 ps
CPU time 997.69 seconds
Started Oct 15 05:45:28 AM UTC 24
Finished Oct 15 06:02:18 AM UTC 24
Peak memory 260844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029941272 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.1029941272 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.2046710299
Short name T660
Test name
Test status
Simulation time 39865401551 ps
CPU time 219.36 seconds
Started Oct 15 05:45:32 AM UTC 24
Finished Oct 15 05:49:15 AM UTC 24
Peak memory 348784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046710299 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2046710299 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_error.1643347490
Short name T694
Test name
Test status
Simulation time 8217350514 ps
CPU time 450.3 seconds
Started Oct 15 05:45:33 AM UTC 24
Finished Oct 15 05:53:10 AM UTC 24
Peak memory 356940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643347490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1643347490 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.2320098426
Short name T630
Test name
Test status
Simulation time 1011452038 ps
CPU time 10.92 seconds
Started Oct 15 05:45:39 AM UTC 24
Finished Oct 15 05:45:51 AM UTC 24
Peak memory 232244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320098426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.2320098426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.4121627869
Short name T629
Test name
Test status
Simulation time 96848892 ps
CPU time 2.38 seconds
Started Oct 15 05:45:40 AM UTC 24
Finished Oct 15 05:45:43 AM UTC 24
Peak memory 234504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121627869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.4121627869 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.247258412
Short name T748
Test name
Test status
Simulation time 12372226024 ps
CPU time 1469.77 seconds
Started Oct 15 05:44:54 AM UTC 24
Finished Oct 15 06:09:40 AM UTC 24
Peak memory 989860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247258412 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.247258412 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.184043145
Short name T637
Test name
Test status
Simulation time 1204782402 ps
CPU time 78.07 seconds
Started Oct 15 05:45:17 AM UTC 24
Finished Oct 15 05:46:37 AM UTC 24
Peak memory 252648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184043145 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.184043145 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload_invalid.2181385965
Short name T625
Test name
Test status
Simulation time 967639577 ps
CPU time 7.71 seconds
Started Oct 15 05:45:23 AM UTC 24
Finished Oct 15 05:45:32 AM UTC 24
Peak memory 238452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181385965 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload_invalid.2181385965 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.2184514204
Short name T631
Test name
Test status
Simulation time 5078884171 ps
CPU time 56.5 seconds
Started Oct 15 05:44:54 AM UTC 24
Finished Oct 15 05:45:52 AM UTC 24
Peak memory 238132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184514204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.2184514204 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.2721925422
Short name T765
Test name
Test status
Simulation time 695307517894 ps
CPU time 3513.7 seconds
Started Oct 15 05:45:44 AM UTC 24
Finished Oct 15 06:44:58 AM UTC 24
Peak memory 1376872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721925422 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.2721925422 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.2471668113
Short name T641
Test name
Test status
Simulation time 33549082 ps
CPU time 1.34 seconds
Started Oct 15 05:47:06 AM UTC 24
Finished Oct 15 05:47:08 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471668113 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2471668113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_app.1058702232
Short name T647
Test name
Test status
Simulation time 10270466035 ps
CPU time 67.12 seconds
Started Oct 15 05:46:32 AM UTC 24
Finished Oct 15 05:47:41 AM UTC 24
Peak memory 277104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058702232 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1058702232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.3437462878
Short name T750
Test name
Test status
Simulation time 24655150378 ps
CPU time 1436.21 seconds
Started Oct 15 05:46:29 AM UTC 24
Finished Oct 15 06:10:41 AM UTC 24
Peak memory 270896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437462878 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3437462878 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.2625932959
Short name T638
Test name
Test status
Simulation time 751783988 ps
CPU time 17.33 seconds
Started Oct 15 05:46:36 AM UTC 24
Finished Oct 15 05:46:54 AM UTC 24
Peak memory 238120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625932959 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.2625932959 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_error.2372008587
Short name T646
Test name
Test status
Simulation time 7846200654 ps
CPU time 56.71 seconds
Started Oct 15 05:46:38 AM UTC 24
Finished Oct 15 05:47:36 AM UTC 24
Peak memory 268840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372008587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2372008587 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.3275934590
Short name T642
Test name
Test status
Simulation time 1448383563 ps
CPU time 17.61 seconds
Started Oct 15 05:46:55 AM UTC 24
Finished Oct 15 05:47:14 AM UTC 24
Peak memory 230044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275934590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3275934590 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.1586233832
Short name T67
Test name
Test status
Simulation time 256229661 ps
CPU time 3.24 seconds
Started Oct 15 05:47:00 AM UTC 24
Finished Oct 15 05:47:05 AM UTC 24
Peak memory 237132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586233832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1586233832 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.966362774
Short name T766
Test name
Test status
Simulation time 29665991458 ps
CPU time 3730.26 seconds
Started Oct 15 05:45:55 AM UTC 24
Finished Oct 15 06:48:46 AM UTC 24
Peak memory 1960496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966362774 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.966362774 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.4091224698
Short name T717
Test name
Test status
Simulation time 41450571453 ps
CPU time 659.12 seconds
Started Oct 15 05:46:01 AM UTC 24
Finished Oct 15 05:57:09 AM UTC 24
Peak memory 643684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091224698 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.4091224698 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload_invalid.346893870
Short name T635
Test name
Test status
Simulation time 93732266 ps
CPU time 4.07 seconds
Started Oct 15 05:46:22 AM UTC 24
Finished Oct 15 05:46:28 AM UTC 24
Peak memory 236884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346893870 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload_invalid.346893870 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.2800061187
Short name T644
Test name
Test status
Simulation time 18775148799 ps
CPU time 88.87 seconds
Started Oct 15 05:45:53 AM UTC 24
Finished Oct 15 05:47:24 AM UTC 24
Peak memory 238112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800061187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.2800061187 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.2706437586
Short name T690
Test name
Test status
Simulation time 19980204856 ps
CPU time 314.69 seconds
Started Oct 15 05:47:06 AM UTC 24
Finished Oct 15 05:52:25 AM UTC 24
Peak memory 252520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706437586 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2706437586 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.3124147840
Short name T652
Test name
Test status
Simulation time 32523899 ps
CPU time 1.3 seconds
Started Oct 15 05:47:59 AM UTC 24
Finished Oct 15 05:48:02 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124147840 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3124147840 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_app.3581115817
Short name T678
Test name
Test status
Simulation time 38587316500 ps
CPU time 242.51 seconds
Started Oct 15 05:47:37 AM UTC 24
Finished Oct 15 05:51:44 AM UTC 24
Peak memory 387696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581115817 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3581115817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.2748558152
Short name T747
Test name
Test status
Simulation time 31915947864 ps
CPU time 1306.74 seconds
Started Oct 15 05:47:26 AM UTC 24
Finished Oct 15 06:09:28 AM UTC 24
Peak memory 275236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748558152 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.2748558152 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.3742272247
Short name T692
Test name
Test status
Simulation time 19786514758 ps
CPU time 289.65 seconds
Started Oct 15 05:47:39 AM UTC 24
Finished Oct 15 05:52:32 AM UTC 24
Peak memory 397856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742272247 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3742272247 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_error.1549357736
Short name T685
Test name
Test status
Simulation time 10647638148 ps
CPU time 254.34 seconds
Started Oct 15 05:47:42 AM UTC 24
Finished Oct 15 05:52:00 AM UTC 24
Peak memory 463444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549357736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1549357736 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.734122595
Short name T655
Test name
Test status
Simulation time 1450801914 ps
CPU time 18.15 seconds
Started Oct 15 05:47:52 AM UTC 24
Finished Oct 15 05:48:11 AM UTC 24
Peak memory 232188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734122595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.734122595 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.343323684
Short name T654
Test name
Test status
Simulation time 157740268 ps
CPU time 8.29 seconds
Started Oct 15 05:47:57 AM UTC 24
Finished Oct 15 05:48:06 AM UTC 24
Peak memory 244768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343323684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.343323684 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.936499307
Short name T768
Test name
Test status
Simulation time 81230919275 ps
CPU time 4267.64 seconds
Started Oct 15 05:47:15 AM UTC 24
Finished Oct 15 06:59:09 AM UTC 24
Peak memory 3912436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936499307 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.936499307 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.3729052170
Short name T671
Test name
Test status
Simulation time 4088402796 ps
CPU time 182.4 seconds
Started Oct 15 05:47:16 AM UTC 24
Finished Oct 15 05:50:21 AM UTC 24
Peak memory 346724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729052170 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3729052170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.3193620905
Short name T648
Test name
Test status
Simulation time 5641123948 ps
CPU time 40.9 seconds
Started Oct 15 05:47:09 AM UTC 24
Finished Oct 15 05:47:51 AM UTC 24
Peak memory 238124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193620905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3193620905 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.109451902
Short name T757
Test name
Test status
Simulation time 85887220611 ps
CPU time 1783.9 seconds
Started Oct 15 05:47:58 AM UTC 24
Finished Oct 15 06:18:02 AM UTC 24
Peak memory 644024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109451902 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.109451902 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.1695220583
Short name T664
Test name
Test status
Simulation time 79594970 ps
CPU time 1.26 seconds
Started Oct 15 05:49:21 AM UTC 24
Finished Oct 15 05:49:23 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695220583 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1695220583 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_app.1078982720
Short name T711
Test name
Test status
Simulation time 12742732405 ps
CPU time 430.1 seconds
Started Oct 15 05:48:25 AM UTC 24
Finished Oct 15 05:55:41 AM UTC 24
Peak memory 522860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078982720 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.1078982720 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.2608955659
Short name T728
Test name
Test status
Simulation time 6850515502 ps
CPU time 650.61 seconds
Started Oct 15 05:48:18 AM UTC 24
Finished Oct 15 05:59:16 AM UTC 24
Peak memory 250412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608955659 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2608955659 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.3825618327
Short name T697
Test name
Test status
Simulation time 6348273406 ps
CPU time 298.77 seconds
Started Oct 15 05:48:44 AM UTC 24
Finished Oct 15 05:53:47 AM UTC 24
Peak memory 340456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825618327 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.3825618327 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_error.2095647505
Short name T702
Test name
Test status
Simulation time 54284394464 ps
CPU time 334.86 seconds
Started Oct 15 05:48:49 AM UTC 24
Finished Oct 15 05:54:30 AM UTC 24
Peak memory 522828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095647505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2095647505 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.2872738855
Short name T662
Test name
Test status
Simulation time 4419105132 ps
CPU time 9.14 seconds
Started Oct 15 05:49:10 AM UTC 24
Finished Oct 15 05:49:20 AM UTC 24
Peak memory 230104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872738855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.2872738855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.2852207217
Short name T661
Test name
Test status
Simulation time 54648186 ps
CPU time 2.17 seconds
Started Oct 15 05:49:17 AM UTC 24
Finished Oct 15 05:49:20 AM UTC 24
Peak memory 236416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852207217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2852207217 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.830574656
Short name T764
Test name
Test status
Simulation time 23753468663 ps
CPU time 3083.37 seconds
Started Oct 15 05:48:03 AM UTC 24
Finished Oct 15 06:40:00 AM UTC 24
Peak memory 1630896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830574656 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.830574656 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.459739193
Short name T684
Test name
Test status
Simulation time 29150771075 ps
CPU time 228.33 seconds
Started Oct 15 05:48:08 AM UTC 24
Finished Oct 15 05:52:00 AM UTC 24
Peak memory 377388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459739193 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.459739193 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload_invalid.2694526515
Short name T20
Test name
Test status
Simulation time 163060261 ps
CPU time 11.35 seconds
Started Oct 15 05:48:12 AM UTC 24
Finished Oct 15 05:48:24 AM UTC 24
Peak memory 236936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694526515 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload_invalid.2694526515 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.765921113
Short name T663
Test name
Test status
Simulation time 3110814957 ps
CPU time 77.92 seconds
Started Oct 15 05:48:02 AM UTC 24
Finished Oct 15 05:49:22 AM UTC 24
Peak memory 236536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765921113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.765921113 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.810156117
Short name T753
Test name
Test status
Simulation time 39866822617 ps
CPU time 1411.18 seconds
Started Oct 15 05:49:21 AM UTC 24
Finished Oct 15 06:13:08 AM UTC 24
Peak memory 396240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810156117 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.810156117 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.1836457593
Short name T673
Test name
Test status
Simulation time 46879076 ps
CPU time 1.04 seconds
Started Oct 15 05:50:35 AM UTC 24
Finished Oct 15 05:50:37 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836457593 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1836457593 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_app.4210651405
Short name T681
Test name
Test status
Simulation time 22670827896 ps
CPU time 101.71 seconds
Started Oct 15 05:50:09 AM UTC 24
Finished Oct 15 05:51:53 AM UTC 24
Peak memory 287316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210651405 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.4210651405 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.1416278786
Short name T721
Test name
Test status
Simulation time 15944173483 ps
CPU time 459.9 seconds
Started Oct 15 05:50:01 AM UTC 24
Finished Oct 15 05:57:47 AM UTC 24
Peak memory 254640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416278786 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.1416278786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.2296949647
Short name T704
Test name
Test status
Simulation time 7790042298 ps
CPU time 282.54 seconds
Started Oct 15 05:50:11 AM UTC 24
Finished Oct 15 05:54:58 AM UTC 24
Peak memory 316016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296949647 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.2296949647 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_error.2595249458
Short name T729
Test name
Test status
Simulation time 85274208865 ps
CPU time 597.99 seconds
Started Oct 15 05:50:11 AM UTC 24
Finished Oct 15 06:00:17 AM UTC 24
Peak memory 680660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595249458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.2595249458 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.2630063317
Short name T672
Test name
Test status
Simulation time 4849579468 ps
CPU time 18.02 seconds
Started Oct 15 05:50:14 AM UTC 24
Finished Oct 15 05:50:34 AM UTC 24
Peak memory 232184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630063317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2630063317 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.1549723720
Short name T78
Test name
Test status
Simulation time 78209140 ps
CPU time 1.97 seconds
Started Oct 15 05:50:22 AM UTC 24
Finished Oct 15 05:50:25 AM UTC 24
Peak memory 233916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549723720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.1549723720 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_long_msg_and_output.1108140515
Short name T746
Test name
Test status
Simulation time 481019672261 ps
CPU time 1080.23 seconds
Started Oct 15 05:49:24 AM UTC 24
Finished Oct 15 06:07:37 AM UTC 24
Peak memory 1352484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108140515 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_and_output.1108140515 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.813086879
Short name T699
Test name
Test status
Simulation time 30336904481 ps
CPU time 266.67 seconds
Started Oct 15 05:49:44 AM UTC 24
Finished Oct 15 05:54:15 AM UTC 24
Peak memory 444984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813086879 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.813086879 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload_invalid.3900767931
Short name T667
Test name
Test status
Simulation time 682915677 ps
CPU time 8.61 seconds
Started Oct 15 05:49:51 AM UTC 24
Finished Oct 15 05:50:00 AM UTC 24
Peak memory 236904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900767931 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload_invalid.3900767931 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.2503583748
Short name T669
Test name
Test status
Simulation time 1121983166 ps
CPU time 45.6 seconds
Started Oct 15 05:49:23 AM UTC 24
Finished Oct 15 05:50:10 AM UTC 24
Peak memory 238056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503583748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2503583748 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.1224663380
Short name T735
Test name
Test status
Simulation time 23307846156 ps
CPU time 712.06 seconds
Started Oct 15 05:50:26 AM UTC 24
Finished Oct 15 06:02:27 AM UTC 24
Peak memory 969372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224663380 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1224663380 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.1639331632
Short name T686
Test name
Test status
Simulation time 46760445 ps
CPU time 1.46 seconds
Started Oct 15 05:52:00 AM UTC 24
Finished Oct 15 05:52:03 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639331632 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1639331632 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_app.1931351176
Short name T703
Test name
Test status
Simulation time 6371928308 ps
CPU time 186.39 seconds
Started Oct 15 05:51:45 AM UTC 24
Finished Oct 15 05:54:54 AM UTC 24
Peak memory 367212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931351176 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.1931351176 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.1056901335
Short name T732
Test name
Test status
Simulation time 13592329009 ps
CPU time 612.29 seconds
Started Oct 15 05:51:34 AM UTC 24
Finished Oct 15 06:01:55 AM UTC 24
Peak memory 254572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056901335 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1056901335 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.4293903564
Short name T701
Test name
Test status
Simulation time 8271954497 ps
CPU time 146.1 seconds
Started Oct 15 05:51:52 AM UTC 24
Finished Oct 15 05:54:20 AM UTC 24
Peak memory 281140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293903564 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.4293903564 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_error.673667439
Short name T719
Test name
Test status
Simulation time 9005630633 ps
CPU time 329.23 seconds
Started Oct 15 05:51:52 AM UTC 24
Finished Oct 15 05:57:26 AM UTC 24
Peak memory 356968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673667439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.673667439 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.2951408001
Short name T683
Test name
Test status
Simulation time 348137601 ps
CPU time 3.49 seconds
Started Oct 15 05:51:54 AM UTC 24
Finished Oct 15 05:51:59 AM UTC 24
Peak memory 230008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951408001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.2951408001 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.54654169
Short name T688
Test name
Test status
Simulation time 2590430707 ps
CPU time 23.18 seconds
Started Oct 15 05:51:56 AM UTC 24
Finished Oct 15 05:52:21 AM UTC 24
Peak memory 250972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54654169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.54654169 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.4167225434
Short name T762
Test name
Test status
Simulation time 73339901758 ps
CPU time 2170.59 seconds
Started Oct 15 05:51:04 AM UTC 24
Finished Oct 15 06:27:40 AM UTC 24
Peak memory 1292904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167225434 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.4167225434 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.303722451
Short name T730
Test name
Test status
Simulation time 85921053598 ps
CPU time 546.24 seconds
Started Oct 15 05:51:22 AM UTC 24
Finished Oct 15 06:00:36 AM UTC 24
Peak memory 621304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303722451 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.303722451 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload_invalid.2063349149
Short name T677
Test name
Test status
Simulation time 69045218 ps
CPU time 2.85 seconds
Started Oct 15 05:51:29 AM UTC 24
Finished Oct 15 05:51:33 AM UTC 24
Peak memory 236868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063349149 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload_invalid.2063349149 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.3584452459
Short name T680
Test name
Test status
Simulation time 14854934620 ps
CPU time 71.52 seconds
Started Oct 15 05:50:38 AM UTC 24
Finished Oct 15 05:51:51 AM UTC 24
Peak memory 238184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584452459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3584452459 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.4068981874
Short name T722
Test name
Test status
Simulation time 72821310098 ps
CPU time 365.69 seconds
Started Oct 15 05:51:59 AM UTC 24
Finished Oct 15 05:58:10 AM UTC 24
Peak memory 311828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068981874 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.4068981874 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.2436635255
Short name T696
Test name
Test status
Simulation time 12475323 ps
CPU time 1.24 seconds
Started Oct 15 05:53:23 AM UTC 24
Finished Oct 15 05:53:25 AM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436635255 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2436635255 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_app.4187727809
Short name T707
Test name
Test status
Simulation time 9353457119 ps
CPU time 177.55 seconds
Started Oct 15 05:52:26 AM UTC 24
Finished Oct 15 05:55:27 AM UTC 24
Peak memory 279152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187727809 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.4187727809 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.2934248596
Short name T713
Test name
Test status
Simulation time 1803456474 ps
CPU time 228.05 seconds
Started Oct 15 05:52:24 AM UTC 24
Finished Oct 15 05:56:16 AM UTC 24
Peak memory 238112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934248596 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2934248596 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.2872788173
Short name T725
Test name
Test status
Simulation time 15861120051 ps
CPU time 381.73 seconds
Started Oct 15 05:52:28 AM UTC 24
Finished Oct 15 05:58:55 AM UTC 24
Peak memory 518752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872788173 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2872788173 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_error.1795167338
Short name T724
Test name
Test status
Simulation time 9153288306 ps
CPU time 352.38 seconds
Started Oct 15 05:52:33 AM UTC 24
Finished Oct 15 05:58:31 AM UTC 24
Peak memory 361068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795167338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1795167338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.3193148353
Short name T695
Test name
Test status
Simulation time 796650938 ps
CPU time 11.98 seconds
Started Oct 15 05:53:09 AM UTC 24
Finished Oct 15 05:53:22 AM UTC 24
Peak memory 232112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193148353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3193148353 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.3918190502
Short name T738
Test name
Test status
Simulation time 24017620215 ps
CPU time 647.21 seconds
Started Oct 15 05:52:05 AM UTC 24
Finished Oct 15 06:03:00 AM UTC 24
Peak memory 586348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918190502 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.3918190502 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.1099961846
Short name T709
Test name
Test status
Simulation time 14671860153 ps
CPU time 199.14 seconds
Started Oct 15 05:52:14 AM UTC 24
Finished Oct 15 05:55:36 AM UTC 24
Peak memory 314088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099961846 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1099961846 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload_invalid.3589180743
Short name T691
Test name
Test status
Simulation time 76080466 ps
CPU time 4.06 seconds
Started Oct 15 05:52:22 AM UTC 24
Finished Oct 15 05:52:27 AM UTC 24
Peak memory 236912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589180743 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload_invalid.3589180743 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.20474989
Short name T693
Test name
Test status
Simulation time 6770582576 ps
CPU time 65 seconds
Started Oct 15 05:52:00 AM UTC 24
Finished Oct 15 05:53:07 AM UTC 24
Peak memory 238288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20474989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.20474989 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.775697725
Short name T761
Test name
Test status
Simulation time 158816461196 ps
CPU time 1823.36 seconds
Started Oct 15 05:53:15 AM UTC 24
Finished Oct 15 06:23:59 AM UTC 24
Peak memory 1057752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775697725 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.775697725 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.4112621854
Short name T708
Test name
Test status
Simulation time 72147382 ps
CPU time 1.4 seconds
Started Oct 15 05:55:28 AM UTC 24
Finished Oct 15 05:55:30 AM UTC 24
Peak memory 226804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112621854 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.4112621854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_app.2192516375
Short name T718
Test name
Test status
Simulation time 2552585453 ps
CPU time 178.08 seconds
Started Oct 15 05:54:22 AM UTC 24
Finished Oct 15 05:57:23 AM UTC 24
Peak memory 283288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192516375 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2192516375 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.964701808
Short name T751
Test name
Test status
Simulation time 8126197112 ps
CPU time 979.69 seconds
Started Oct 15 05:54:20 AM UTC 24
Finished Oct 15 06:10:51 AM UTC 24
Peak memory 250536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964701808 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.964701808 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.1584691295
Short name T737
Test name
Test status
Simulation time 19687664758 ps
CPU time 486.2 seconds
Started Oct 15 05:54:31 AM UTC 24
Finished Oct 15 06:02:44 AM UTC 24
Peak memory 590572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584691295 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1584691295 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_error.3492246740
Short name T740
Test name
Test status
Simulation time 15175870302 ps
CPU time 510.62 seconds
Started Oct 15 05:54:55 AM UTC 24
Finished Oct 15 06:03:32 AM UTC 24
Peak memory 590436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492246740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3492246740 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.23049072
Short name T705
Test name
Test status
Simulation time 225940660 ps
CPU time 3.9 seconds
Started Oct 15 05:54:58 AM UTC 24
Finished Oct 15 05:55:03 AM UTC 24
Peak memory 230068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23049072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.23049072 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.448869322
Short name T710
Test name
Test status
Simulation time 3417914102 ps
CPU time 33.79 seconds
Started Oct 15 05:55:04 AM UTC 24
Finished Oct 15 05:55:40 AM UTC 24
Peak memory 259356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448869322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.448869322 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.3966781638
Short name T714
Test name
Test status
Simulation time 16533114719 ps
CPU time 161.42 seconds
Started Oct 15 05:53:48 AM UTC 24
Finished Oct 15 05:56:32 AM UTC 24
Peak memory 442980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966781638 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.3966781638 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.614502354
Short name T726
Test name
Test status
Simulation time 14714681668 ps
CPU time 301.22 seconds
Started Oct 15 05:53:53 AM UTC 24
Finished Oct 15 05:58:59 AM UTC 24
Peak memory 442928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614502354 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.614502354 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload_invalid.2299567274
Short name T700
Test name
Test status
Simulation time 50571789 ps
CPU time 2.19 seconds
Started Oct 15 05:54:16 AM UTC 24
Finished Oct 15 05:54:19 AM UTC 24
Peak memory 232576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299567274 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload_invalid.2299567274 +enable_masking=1 +sw
_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.19499513
Short name T706
Test name
Test status
Simulation time 4527353694 ps
CPU time 99.45 seconds
Started Oct 15 05:53:26 AM UTC 24
Finished Oct 15 05:55:08 AM UTC 24
Peak memory 238092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19499513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.19499513 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.846739442
Short name T754
Test name
Test status
Simulation time 59287493110 ps
CPU time 1086.42 seconds
Started Oct 15 05:55:09 AM UTC 24
Finished Oct 15 06:13:28 AM UTC 24
Peak memory 674752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846739442 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.846739442 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.3067338908
Short name T211
Test name
Test status
Simulation time 21634572 ps
CPU time 1.38 seconds
Started Oct 15 04:53:51 AM UTC 24
Finished Oct 15 04:53:53 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067338908 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3067338908 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_app.4073258862
Short name T234
Test name
Test status
Simulation time 5935232745 ps
CPU time 348.52 seconds
Started Oct 15 04:52:47 AM UTC 24
Finished Oct 15 04:58:40 AM UTC 24
Peak memory 350828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073258862 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.4073258862 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.851920669
Short name T220
Test name
Test status
Simulation time 3514917227 ps
CPU time 172.04 seconds
Started Oct 15 04:52:48 AM UTC 24
Finished Oct 15 04:55:43 AM UTC 24
Peak memory 293620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851920669 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.851920669 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.2175046189
Short name T349
Test name
Test status
Simulation time 11656371623 ps
CPU time 1199.06 seconds
Started Oct 15 04:52:45 AM UTC 24
Finished Oct 15 05:12:58 AM UTC 24
Peak memory 256624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175046189 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2175046189 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.1729670286
Short name T210
Test name
Test status
Simulation time 833240520 ps
CPU time 14.99 seconds
Started Oct 15 04:53:33 AM UTC 24
Finished Oct 15 04:53:50 AM UTC 24
Peak memory 234244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729670286 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1729670286 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.1710455651
Short name T206
Test name
Test status
Simulation time 47946168 ps
CPU time 1.83 seconds
Started Oct 15 04:53:40 AM UTC 24
Finished Oct 15 04:53:43 AM UTC 24
Peak memory 230068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710455651 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1710455651 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.1379158813
Short name T213
Test name
Test status
Simulation time 13105851570 ps
CPU time 39.62 seconds
Started Oct 15 04:53:44 AM UTC 24
Finished Oct 15 04:54:25 AM UTC 24
Peak memory 234668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379158813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1379158813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.1658071065
Short name T84
Test name
Test status
Simulation time 16124272927 ps
CPU time 182.84 seconds
Started Oct 15 04:52:59 AM UTC 24
Finished Oct 15 04:56:05 AM UTC 24
Peak memory 279092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658071065 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.1658071065 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_error.3080721916
Short name T40
Test name
Test status
Simulation time 3996340456 ps
CPU time 302.35 seconds
Started Oct 15 04:53:19 AM UTC 24
Finished Oct 15 04:58:26 AM UTC 24
Peak memory 352868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080721916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.3080721916 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.1534253055
Short name T208
Test name
Test status
Simulation time 3297770509 ps
CPU time 20.49 seconds
Started Oct 15 04:53:27 AM UTC 24
Finished Oct 15 04:53:49 AM UTC 24
Peak memory 230232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534253055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1534253055 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.368156402
Short name T49
Test name
Test status
Simulation time 122730823 ps
CPU time 2.07 seconds
Started Oct 15 04:53:48 AM UTC 24
Finished Oct 15 04:53:51 AM UTC 24
Peak memory 234520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368156402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.368156402 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.2137858882
Short name T440
Test name
Test status
Simulation time 472100891368 ps
CPU time 1896.3 seconds
Started Oct 15 04:52:34 AM UTC 24
Finished Oct 15 05:24:32 AM UTC 24
Peak memory 2507308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137858882 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.2137858882 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.3221940515
Short name T96
Test name
Test status
Simulation time 3500353967 ps
CPU time 84.5 seconds
Started Oct 15 04:53:10 AM UTC 24
Finished Oct 15 04:54:37 AM UTC 24
Peak memory 295916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221940515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3221940515 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.4198599445
Short name T29
Test name
Test status
Simulation time 2832775995 ps
CPU time 107.12 seconds
Started Oct 15 04:52:37 AM UTC 24
Finished Oct 15 04:54:27 AM UTC 24
Peak memory 303888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198599445 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.4198599445 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload_invalid.1186033518
Short name T123
Test name
Test status
Simulation time 143747120 ps
CPU time 5.46 seconds
Started Oct 15 04:52:40 AM UTC 24
Finished Oct 15 04:52:46 AM UTC 24
Peak memory 235016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186033518 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload_invalid.1186033518 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.3833820117
Short name T188
Test name
Test status
Simulation time 4154354594 ps
CPU time 82.42 seconds
Started Oct 15 04:52:32 AM UTC 24
Finished Oct 15 04:53:57 AM UTC 24
Peak memory 240176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833820117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.3833820117 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.2647144078
Short name T435
Test name
Test status
Simulation time 193897461687 ps
CPU time 1750.6 seconds
Started Oct 15 04:53:50 AM UTC 24
Finished Oct 15 05:23:19 AM UTC 24
Peak memory 1160276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647144078 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2647144078 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.1789280833
Short name T218
Test name
Test status
Simulation time 73265533 ps
CPU time 1.26 seconds
Started Oct 15 04:55:04 AM UTC 24
Finished Oct 15 04:55:06 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789280833 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1789280833 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_app.4162249804
Short name T28
Test name
Test status
Simulation time 5506956934 ps
CPU time 147.93 seconds
Started Oct 15 04:54:16 AM UTC 24
Finished Oct 15 04:56:47 AM UTC 24
Peak memory 285236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162249804 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4162249804 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.913978878
Short name T27
Test name
Test status
Simulation time 2766656314 ps
CPU time 121.4 seconds
Started Oct 15 04:54:22 AM UTC 24
Finished Oct 15 04:56:25 AM UTC 24
Peak memory 270964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913978878 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.913978878 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.1835731175
Short name T145
Test name
Test status
Simulation time 6521838128 ps
CPU time 95.96 seconds
Started Oct 15 04:54:13 AM UTC 24
Finished Oct 15 04:55:52 AM UTC 24
Peak memory 236672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835731175 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.1835731175 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.4177697504
Short name T215
Test name
Test status
Simulation time 64646655 ps
CPU time 1.31 seconds
Started Oct 15 04:54:58 AM UTC 24
Finished Oct 15 04:55:00 AM UTC 24
Peak memory 230000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177697504 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.4177697504 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.3461721939
Short name T217
Test name
Test status
Simulation time 28951080 ps
CPU time 1.53 seconds
Started Oct 15 04:55:01 AM UTC 24
Finished Oct 15 04:55:03 AM UTC 24
Peak memory 226688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461721939 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.3461721939 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.4033014136
Short name T219
Test name
Test status
Simulation time 3537398518 ps
CPU time 23.42 seconds
Started Oct 15 04:55:01 AM UTC 24
Finished Oct 15 04:55:26 AM UTC 24
Peak memory 234616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033014136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.4033014136 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.826359275
Short name T85
Test name
Test status
Simulation time 21464878541 ps
CPU time 148.31 seconds
Started Oct 15 04:54:26 AM UTC 24
Finished Oct 15 04:56:57 AM UTC 24
Peak memory 303724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826359275 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.826359275 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_error.2890257327
Short name T242
Test name
Test status
Simulation time 13698761615 ps
CPU time 340.55 seconds
Started Oct 15 04:54:28 AM UTC 24
Finished Oct 15 05:00:13 AM UTC 24
Peak memory 352812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890257327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.2890257327 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.173746189
Short name T214
Test name
Test status
Simulation time 2867973586 ps
CPU time 19.38 seconds
Started Oct 15 04:54:39 AM UTC 24
Finished Oct 15 04:54:59 AM UTC 24
Peak memory 230132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173746189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.173746189 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.888138135
Short name T45
Test name
Test status
Simulation time 60050539 ps
CPU time 1.33 seconds
Started Oct 15 04:55:01 AM UTC 24
Finished Oct 15 04:55:03 AM UTC 24
Peak memory 231884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888138135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.888138135 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.472124803
Short name T419
Test name
Test status
Simulation time 13960137647 ps
CPU time 1640.61 seconds
Started Oct 15 04:53:54 AM UTC 24
Finished Oct 15 05:21:33 AM UTC 24
Peak memory 1026672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472124803 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.472124803 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.2716625995
Short name T97
Test name
Test status
Simulation time 4915422033 ps
CPU time 160.8 seconds
Started Oct 15 04:54:26 AM UTC 24
Finished Oct 15 04:57:09 AM UTC 24
Peak memory 277628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716625995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2716625995 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.2410256680
Short name T250
Test name
Test status
Simulation time 13571293826 ps
CPU time 421.57 seconds
Started Oct 15 04:53:58 AM UTC 24
Finished Oct 15 05:01:05 AM UTC 24
Peak memory 522804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410256680 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2410256680 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload_invalid.944160725
Short name T124
Test name
Test status
Simulation time 49597353 ps
CPU time 2.62 seconds
Started Oct 15 04:54:12 AM UTC 24
Finished Oct 15 04:54:16 AM UTC 24
Peak memory 235000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944160725 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload_invalid.944160725 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.2434514472
Short name T216
Test name
Test status
Simulation time 1971995191 ps
CPU time 66.66 seconds
Started Oct 15 04:53:52 AM UTC 24
Finished Oct 15 04:55:00 AM UTC 24
Peak memory 234484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434514472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2434514472 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.4005994859
Short name T414
Test name
Test status
Simulation time 64568749965 ps
CPU time 1519.94 seconds
Started Oct 15 04:55:01 AM UTC 24
Finished Oct 15 05:20:40 AM UTC 24
Peak memory 511052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005994859 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.4005994859 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.3225948633
Short name T225
Test name
Test status
Simulation time 48095969 ps
CPU time 1.31 seconds
Started Oct 15 04:56:58 AM UTC 24
Finished Oct 15 04:57:01 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225948633 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3225948633 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_app.3932472381
Short name T160
Test name
Test status
Simulation time 17826771029 ps
CPU time 420.03 seconds
Started Oct 15 04:55:47 AM UTC 24
Finished Oct 15 05:02:52 AM UTC 24
Peak memory 551540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932472381 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.3932472381 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.3474925206
Short name T227
Test name
Test status
Simulation time 3296770911 ps
CPU time 94.44 seconds
Started Oct 15 04:55:53 AM UTC 24
Finished Oct 15 04:57:29 AM UTC 24
Peak memory 287420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474925206 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.3474925206 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.181409581
Short name T146
Test name
Test status
Simulation time 7589021263 ps
CPU time 100.22 seconds
Started Oct 15 04:55:44 AM UTC 24
Finished Oct 15 04:57:26 AM UTC 24
Peak memory 248360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181409581 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.181409581 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.4114192043
Short name T33
Test name
Test status
Simulation time 5433249873 ps
CPU time 55.69 seconds
Started Oct 15 04:56:25 AM UTC 24
Finished Oct 15 04:57:23 AM UTC 24
Peak memory 238000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114192043 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.4114192043 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.3482902406
Short name T224
Test name
Test status
Simulation time 20021038 ps
CPU time 1.59 seconds
Started Oct 15 04:56:26 AM UTC 24
Finished Oct 15 04:56:29 AM UTC 24
Peak memory 230076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482902406 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.3482902406 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.1878910693
Short name T229
Test name
Test status
Simulation time 13179513528 ps
CPU time 85.33 seconds
Started Oct 15 04:56:29 AM UTC 24
Finished Oct 15 04:57:57 AM UTC 24
Peak memory 238132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878910693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1878910693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.3937408959
Short name T82
Test name
Test status
Simulation time 23602013037 ps
CPU time 164.07 seconds
Started Oct 15 04:56:00 AM UTC 24
Finished Oct 15 04:58:47 AM UTC 24
Peak memory 328440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937408959 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.3937408959 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_error.1267417555
Short name T152
Test name
Test status
Simulation time 20537914433 ps
CPU time 538.8 seconds
Started Oct 15 04:56:06 AM UTC 24
Finished Oct 15 05:05:12 AM UTC 24
Peak memory 664104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267417555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1267417555 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.22185222
Short name T223
Test name
Test status
Simulation time 507607676 ps
CPU time 4.27 seconds
Started Oct 15 04:56:19 AM UTC 24
Finished Oct 15 04:56:24 AM UTC 24
Peak memory 230236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22185222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.22185222 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.3881746364
Short name T226
Test name
Test status
Simulation time 1032517438 ps
CPU time 27.45 seconds
Started Oct 15 04:56:38 AM UTC 24
Finished Oct 15 04:57:07 AM UTC 24
Peak memory 250572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881746364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.3881746364 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.2678511484
Short name T228
Test name
Test status
Simulation time 5807786043 ps
CPU time 143.39 seconds
Started Oct 15 04:55:07 AM UTC 24
Finished Oct 15 04:57:33 AM UTC 24
Peak memory 315880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678511484 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.2678511484 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.588488181
Short name T271
Test name
Test status
Simulation time 17711551228 ps
CPU time 440.16 seconds
Started Oct 15 04:56:01 AM UTC 24
Finished Oct 15 05:03:27 AM UTC 24
Peak memory 543864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588488181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.588488181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.3478352947
Short name T178
Test name
Test status
Simulation time 1576161154 ps
CPU time 69.22 seconds
Started Oct 15 04:55:26 AM UTC 24
Finished Oct 15 04:56:38 AM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478352947 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3478352947 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload_invalid.2492508958
Short name T38
Test name
Test status
Simulation time 100503876 ps
CPU time 3.08 seconds
Started Oct 15 04:55:42 AM UTC 24
Finished Oct 15 04:55:46 AM UTC 24
Peak memory 234824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492508958 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload_invalid.2492508958 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.2336756407
Short name T222
Test name
Test status
Simulation time 24370921470 ps
CPU time 72.72 seconds
Started Oct 15 04:55:04 AM UTC 24
Finished Oct 15 04:56:19 AM UTC 24
Peak memory 238292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336756407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2336756407 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all.2062470816
Short name T244
Test name
Test status
Simulation time 4702828268 ps
CPU time 206.69 seconds
Started Oct 15 04:56:48 AM UTC 24
Finished Oct 15 05:00:18 AM UTC 24
Peak memory 297516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062470816 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2062470816 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/7.kmac_stress_all_with_rand_reset.1112298572
Short name T41
Test name
Test status
Simulation time 4751155663 ps
CPU time 106.84 seconds
Started Oct 15 04:56:50 AM UTC 24
Finished Oct 15 04:58:39 AM UTC 24
Peak memory 285636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1112298572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_r
and_reset.1112298572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.2360380335
Short name T236
Test name
Test status
Simulation time 19347476 ps
CPU time 1.31 seconds
Started Oct 15 04:58:40 AM UTC 24
Finished Oct 15 04:58:42 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360380335 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2360380335 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_app.1593546981
Short name T273
Test name
Test status
Simulation time 30151638162 ps
CPU time 389.29 seconds
Started Oct 15 04:57:26 AM UTC 24
Finished Oct 15 05:04:01 AM UTC 24
Peak memory 486132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593546981 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1593546981 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.811811331
Short name T231
Test name
Test status
Simulation time 1217442982 ps
CPU time 40.53 seconds
Started Oct 15 04:57:29 AM UTC 24
Finished Oct 15 04:58:12 AM UTC 24
Peak memory 246288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811811331 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.811811331 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.972794325
Short name T391
Test name
Test status
Simulation time 94478889369 ps
CPU time 1221.06 seconds
Started Oct 15 04:57:23 AM UTC 24
Finished Oct 15 05:17:59 AM UTC 24
Peak memory 270892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972794325 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.972794325 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.4096667017
Short name T239
Test name
Test status
Simulation time 436846435 ps
CPU time 41.21 seconds
Started Oct 15 04:58:13 AM UTC 24
Finished Oct 15 04:58:56 AM UTC 24
Peak memory 248068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096667017 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.4096667017 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.201199005
Short name T233
Test name
Test status
Simulation time 22288818 ps
CPU time 1.44 seconds
Started Oct 15 04:58:14 AM UTC 24
Finished Oct 15 04:58:16 AM UTC 24
Peak memory 228492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201199005 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.201199005 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.3352911867
Short name T237
Test name
Test status
Simulation time 3375449727 ps
CPU time 27.75 seconds
Started Oct 15 04:58:17 AM UTC 24
Finished Oct 15 04:58:46 AM UTC 24
Peak memory 238192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352911867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3352911867 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.1786595827
Short name T243
Test name
Test status
Simulation time 8782483837 ps
CPU time 161.51 seconds
Started Oct 15 04:57:30 AM UTC 24
Finished Oct 15 05:00:15 AM UTC 24
Peak memory 270888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786595827 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1786595827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.2768139886
Short name T232
Test name
Test status
Simulation time 4406282725 ps
CPU time 11.62 seconds
Started Oct 15 04:58:00 AM UTC 24
Finished Oct 15 04:58:13 AM UTC 24
Peak memory 230264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768139886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2768139886 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.534690783
Short name T122
Test name
Test status
Simulation time 27842851 ps
CPU time 1.97 seconds
Started Oct 15 04:58:27 AM UTC 24
Finished Oct 15 04:58:30 AM UTC 24
Peak memory 233920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534690783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.534690783 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_long_msg_and_output.1393478734
Short name T741
Test name
Test status
Simulation time 193129547814 ps
CPU time 3949.2 seconds
Started Oct 15 04:57:08 AM UTC 24
Finished Oct 15 06:03:39 AM UTC 24
Peak memory 3916392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393478734 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.1393478734 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.2098251743
Short name T98
Test name
Test status
Simulation time 73364508285 ps
CPU time 180.26 seconds
Started Oct 15 04:57:35 AM UTC 24
Finished Oct 15 05:00:38 AM UTC 24
Peak memory 328636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098251743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2098251743 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.2670807337
Short name T261
Test name
Test status
Simulation time 54434795502 ps
CPU time 322.68 seconds
Started Oct 15 04:57:10 AM UTC 24
Finished Oct 15 05:02:37 AM UTC 24
Peak memory 520752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670807337 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.2670807337 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload_invalid.2747959576
Short name T39
Test name
Test status
Simulation time 82557800 ps
CPU time 4.53 seconds
Started Oct 15 04:57:23 AM UTC 24
Finished Oct 15 04:57:29 AM UTC 24
Peak memory 237064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747959576 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload_invalid.2747959576 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.2399717037
Short name T230
Test name
Test status
Simulation time 7844639860 ps
CPU time 55.81 seconds
Started Oct 15 04:57:02 AM UTC 24
Finished Oct 15 04:57:59 AM UTC 24
Peak memory 238164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399717037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2399717037 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.1333472274
Short name T447
Test name
Test status
Simulation time 185110240705 ps
CPU time 1601.75 seconds
Started Oct 15 04:58:30 AM UTC 24
Finished Oct 15 05:25:29 AM UTC 24
Peak memory 1369024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333472274 -assert nopostpr
oc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1333472274 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all_with_rand_reset.1209539071
Short name T131
Test name
Test status
Simulation time 5960433428 ps
CPU time 234.81 seconds
Started Oct 15 04:58:31 AM UTC 24
Finished Oct 15 05:02:29 AM UTC 24
Peak memory 303728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_al
l_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1209539071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_r
and_reset.1209539071 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.4103629489
Short name T246
Test name
Test status
Simulation time 84076105 ps
CPU time 1.19 seconds
Started Oct 15 05:00:39 AM UTC 24
Finished Oct 15 05:00:41 AM UTC 24
Peak memory 228604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103629489 -assert nopostproc +UVM_TESTNAM
E=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.4103629489 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_app.571064486
Short name T288
Test name
Test status
Simulation time 10970445028 ps
CPU time 420.56 seconds
Started Oct 15 04:58:54 AM UTC 24
Finished Oct 15 05:06:00 AM UTC 24
Peak memory 475900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571064486 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1
0_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.571064486 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.1435078164
Short name T284
Test name
Test status
Simulation time 38645464499 ps
CPU time 364.38 seconds
Started Oct 15 04:58:56 AM UTC 24
Finished Oct 15 05:05:05 AM UTC 24
Peak memory 361180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435078164 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.1435078164 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.1282979413
Short name T149
Test name
Test status
Simulation time 44772456074 ps
CPU time 520.06 seconds
Started Oct 15 04:58:47 AM UTC 24
Finished Oct 15 05:07:34 AM UTC 24
Peak memory 254640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282979413 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1282979413 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.3384661166
Short name T245
Test name
Test status
Simulation time 282395111 ps
CPU time 9.19 seconds
Started Oct 15 05:00:11 AM UTC 24
Finished Oct 15 05:00:22 AM UTC 24
Peak memory 237468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384661166 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3384661166 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.3852995480
Short name T248
Test name
Test status
Simulation time 5535640526 ps
CPU time 45.38 seconds
Started Oct 15 05:00:14 AM UTC 24
Finished Oct 15 05:01:01 AM UTC 24
Peak memory 237800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852995480 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
4/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3852995480 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2006155546
Short name T249
Test name
Test status
Simulation time 2441214220 ps
CPU time 46.45 seconds
Started Oct 15 05:00:16 AM UTC 24
Finished Oct 15 05:01:04 AM UTC 24
Peak memory 234560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006155546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_ma
sked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2006155546 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.1579669741
Short name T262
Test name
Test status
Simulation time 24603238449 ps
CPU time 235.31 seconds
Started Oct 15 04:58:56 AM UTC 24
Finished Oct 15 05:02:55 AM UTC 24
Peak memory 297524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579669741 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.1579669741 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_error.4216040112
Short name T264
Test name
Test status
Simulation time 2219755498 ps
CPU time 231.87 seconds
Started Oct 15 04:59:04 AM UTC 24
Finished Oct 15 05:02:59 AM UTC 24
Peak memory 316008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216040112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.4216040112 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.2355529983
Short name T241
Test name
Test status
Simulation time 3101046662 ps
CPU time 4.13 seconds
Started Oct 15 05:00:01 AM UTC 24
Finished Oct 15 05:00:10 AM UTC 24
Peak memory 230236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355529983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2355529983 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.1416616195
Short name T64
Test name
Test status
Simulation time 69511886 ps
CPU time 1.91 seconds
Started Oct 15 05:00:19 AM UTC 24
Finished Oct 15 05:00:21 AM UTC 24
Peak memory 233916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416616195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1416616195 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.2676625579
Short name T293
Test name
Test status
Simulation time 13880961519 ps
CPU time 451.89 seconds
Started Oct 15 04:58:42 AM UTC 24
Finished Oct 15 05:06:21 AM UTC 24
Peak memory 676368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676625579 -assert nopostproc +UVM_T
ESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.2676625579 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.1472238525
Short name T99
Test name
Test status
Simulation time 7644359872 ps
CPU time 159.19 seconds
Started Oct 15 04:58:57 AM UTC 24
Finished Oct 15 05:01:39 AM UTC 24
Peak memory 279680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472238525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1472238525 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.3400202054
Short name T269
Test name
Test status
Simulation time 6267794202 ps
CPU time 261.28 seconds
Started Oct 15 04:58:43 AM UTC 24
Finished Oct 15 05:03:09 AM UTC 24
Peak memory 397908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400202054 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3400202054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload_invalid.1313237772
Short name T125
Test name
Test status
Simulation time 530826897 ps
CPU time 6.62 seconds
Started Oct 15 04:58:47 AM UTC 24
Finished Oct 15 04:58:55 AM UTC 24
Peak memory 235080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313237772 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload_invalid.1313237772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_sideload_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.1047368540
Short name T238
Test name
Test status
Simulation time 856167225 ps
CPU time 13.02 seconds
Started Oct 15 04:58:41 AM UTC 24
Finished Oct 15 04:58:55 AM UTC 24
Peak memory 236672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047368540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST
_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1047368540 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.610331467
Short name T736
Test name
Test status
Simulation time 525951452259 ps
CPU time 3692.72 seconds
Started Oct 15 05:00:23 AM UTC 24
Finished Oct 15 06:02:35 AM UTC 24
Peak memory 1698420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/
scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610331467 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_14/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.610331467 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression_2024_10_14/kmac_masked-sim-vcs/9.kmac_stress_all/latest
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