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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.15 97.91 92.65 99.89 76.06 95.59 99.05 97.88


Total test records in report: 1233
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T1063 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_shake_256.1327307842 Feb 09 02:59:55 AM UTC 25 Feb 09 04:17:35 AM UTC 25 73507538399 ps
T1064 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_test_vectors_shake_128.2930502600 Feb 09 01:34:29 AM UTC 25 Feb 09 04:17:41 AM UTC 25 1362751867010 ps
T1065 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_test_vectors_shake_256.3090766683 Feb 09 02:28:25 AM UTC 25 Feb 09 04:18:14 AM UTC 25 329206382846 ps
T1066 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_shake_128.3878638250 Feb 09 02:33:00 AM UTC 25 Feb 09 04:21:10 AM UTC 25 74339164717 ps
T1067 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_shake_128.3871791259 Feb 09 02:14:09 AM UTC 25 Feb 09 04:25:15 AM UTC 25 737156588121 ps
T1068 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_shake_256.983296734 Feb 09 02:21:26 AM UTC 25 Feb 09 04:25:49 AM UTC 25 226695575463 ps
T1069 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_shake_256.1081607567 Feb 09 02:14:19 AM UTC 25 Feb 09 04:28:20 AM UTC 25 854311751926 ps
T1070 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_test_vectors_shake_128.3996975090 Feb 09 02:47:26 AM UTC 25 Feb 09 04:28:31 AM UTC 25 498046819577 ps
T1071 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_shake_128.4021234040 Feb 09 02:20:21 AM UTC 25 Feb 09 04:30:00 AM UTC 25 699714679313 ps
T1072 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_shake_256.245519496 Feb 09 03:07:10 AM UTC 25 Feb 09 04:31:33 AM UTC 25 99881346020 ps
T1073 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_shake_256.3359365360 Feb 09 02:36:08 AM UTC 25 Feb 09 04:35:36 AM UTC 25 632745898429 ps
T1074 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_shake_128.3027331476 Feb 09 03:17:01 AM UTC 25 Feb 09 04:51:46 AM UTC 25 401979377018 ps
T1075 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_shake_256.3830834009 Feb 09 03:17:55 AM UTC 25 Feb 09 05:11:07 AM UTC 25 439058939817 ps
T1076 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_shake_128.3870424071 Feb 09 02:59:04 AM UTC 25 Feb 09 05:11:37 AM UTC 25 194702897844 ps
T1077 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_test_vectors_shake_128.265859402 Feb 09 02:42:43 AM UTC 25 Feb 09 05:12:14 AM UTC 25 1079098242062 ps
T1078 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_shake_256.1465874463 Feb 09 03:10:51 AM UTC 25 Feb 09 05:22:17 AM UTC 25 908009781601 ps
T1079 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_shake_128.4205193841 Feb 09 03:07:09 AM UTC 25 Feb 09 05:35:58 AM UTC 25 1963118981594 ps
T1080 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_shake_128.3295159407 Feb 09 03:10:34 AM UTC 25 Feb 09 05:42:44 AM UTC 25 260749395510 ps
T119 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.1769146785 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 15745164 ps
T1081 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.2982572434 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:10 PM UTC 25 16889579 ps
T139 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.764390609 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:11 PM UTC 25 114549076 ps
T87 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3426515494 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:11 PM UTC 25 113449256 ps
T183 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.3380983531 Feb 08 06:47:09 PM UTC 25 Feb 08 06:47:12 PM UTC 25 21133142 ps
T120 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1218645793 Feb 08 06:47:09 PM UTC 25 Feb 08 06:47:12 PM UTC 25 17259537 ps
T90 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.321110420 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:12 PM UTC 25 471058617 ps
T112 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.3044422830 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:13 PM UTC 25 161259484 ps
T116 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.3775052304 Feb 08 06:47:08 PM UTC 25 Feb 08 06:47:14 PM UTC 25 274685440 ps
T97 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.109328521 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:15 PM UTC 25 22748566 ps
T1082 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.2632576911 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:15 PM UTC 25 10469170 ps
T121 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.1322757493 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:15 PM UTC 25 47201581 ps
T1083 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2993554749 Feb 08 06:47:12 PM UTC 25 Feb 08 06:47:15 PM UTC 25 78089982 ps
T184 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.3068514581 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:15 PM UTC 25 23127982 ps
T1084 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2672059336 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:15 PM UTC 25 61136855 ps
T140 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.719450292 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:15 PM UTC 25 495110871 ps
T1085 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.927900362 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:16 PM UTC 25 15107557 ps
T88 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1698756399 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:16 PM UTC 25 96180457 ps
T89 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3106654802 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:16 PM UTC 25 53472230 ps
T130 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1429367614 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:16 PM UTC 25 79604175 ps
T141 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.598221513 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:16 PM UTC 25 45924431 ps
T131 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.505480775 Feb 08 06:47:12 PM UTC 25 Feb 08 06:47:17 PM UTC 25 315928923 ps
T123 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.788179590 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:17 PM UTC 25 278763734 ps
T91 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2668206644 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:17 PM UTC 25 348074570 ps
T163 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.4003577052 Feb 08 06:47:15 PM UTC 25 Feb 08 06:47:17 PM UTC 25 46191427 ps
T154 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3318157661 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:17 PM UTC 25 202463335 ps
T1086 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3702401380 Feb 08 06:47:15 PM UTC 25 Feb 08 06:47:17 PM UTC 25 47787686 ps
T125 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.3093549270 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:17 PM UTC 25 373632189 ps
T1087 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1390049037 Feb 08 06:47:15 PM UTC 25 Feb 08 06:47:17 PM UTC 25 28701158 ps
T1088 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.1632152380 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:18 PM UTC 25 81656941 ps
T117 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2223458641 Feb 08 06:47:14 PM UTC 25 Feb 08 06:47:18 PM UTC 25 182698632 ps
T1089 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.3770009998 Feb 08 06:47:16 PM UTC 25 Feb 08 06:47:18 PM UTC 25 24872791 ps
T1090 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.544604896 Feb 08 06:47:16 PM UTC 25 Feb 08 06:47:18 PM UTC 25 22033331 ps
T118 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.3615862030 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:18 PM UTC 25 260915752 ps
T155 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3369172170 Feb 08 06:47:16 PM UTC 25 Feb 08 06:47:19 PM UTC 25 69156955 ps
T142 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3480512081 Feb 08 06:47:16 PM UTC 25 Feb 08 06:47:19 PM UTC 25 43922074 ps
T185 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3772776758 Feb 08 06:47:16 PM UTC 25 Feb 08 06:47:19 PM UTC 25 27666487 ps
T164 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.2982097021 Feb 08 06:47:17 PM UTC 25 Feb 08 06:47:19 PM UTC 25 16028323 ps
T1091 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.2337552484 Feb 08 06:47:17 PM UTC 25 Feb 08 06:47:20 PM UTC 25 24193263 ps
T1092 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3091606403 Feb 08 06:47:18 PM UTC 25 Feb 08 06:47:20 PM UTC 25 16300013 ps
T126 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.3111758908 Feb 08 06:47:16 PM UTC 25 Feb 08 06:47:20 PM UTC 25 294562303 ps
T1093 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.966423807 Feb 08 06:47:17 PM UTC 25 Feb 08 06:47:20 PM UTC 25 58655907 ps
T92 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.540754200 Feb 08 06:47:18 PM UTC 25 Feb 08 06:47:20 PM UTC 25 164372920 ps
T132 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1261963600 Feb 08 06:47:16 PM UTC 25 Feb 08 06:47:20 PM UTC 25 149407642 ps
T138 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1103588953 Feb 08 06:47:16 PM UTC 25 Feb 08 06:47:20 PM UTC 25 284249488 ps
T1094 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.3577488548 Feb 08 06:47:12 PM UTC 25 Feb 08 06:47:21 PM UTC 25 144810067 ps
T156 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.699997645 Feb 08 06:47:18 PM UTC 25 Feb 08 06:47:21 PM UTC 25 398820338 ps
T1095 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2068323159 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:21 PM UTC 25 49555443 ps
T165 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.1452250575 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:22 PM UTC 25 34946168 ps
T93 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.833537760 Feb 08 06:47:18 PM UTC 25 Feb 08 06:47:22 PM UTC 25 271352327 ps
T143 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.2359248972 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:22 PM UTC 25 49614201 ps
T1096 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2478236766 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:22 PM UTC 25 42228244 ps
T157 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.973588161 Feb 08 06:47:18 PM UTC 25 Feb 08 06:47:22 PM UTC 25 116175752 ps
T1097 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1033334332 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:22 PM UTC 25 79279974 ps
T124 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3013568317 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:22 PM UTC 25 53901047 ps
T166 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.1849777594 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:23 PM UTC 25 24535498 ps
T129 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.440000524 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:23 PM UTC 25 30549081 ps
T1098 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.722737698 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:23 PM UTC 25 71389262 ps
T170 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1481394034 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:23 PM UTC 25 252046170 ps
T94 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.427500360 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:23 PM UTC 25 31958314 ps
T96 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3426004914 Feb 08 06:47:20 PM UTC 25 Feb 08 06:47:24 PM UTC 25 44981082 ps
T1099 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.42558461 Feb 08 06:47:17 PM UTC 25 Feb 08 06:47:24 PM UTC 25 199904791 ps
T1100 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.851008765 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:24 PM UTC 25 83241217 ps
T127 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.1412992080 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:24 PM UTC 25 57305783 ps
T1101 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.2462540631 Feb 08 06:47:22 PM UTC 25 Feb 08 06:47:24 PM UTC 25 287745508 ps
T175 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1221781314 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:24 PM UTC 25 211374451 ps
T167 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.3674386597 Feb 08 06:47:22 PM UTC 25 Feb 08 06:47:24 PM UTC 25 41168102 ps
T1102 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.4036703644 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:25 PM UTC 25 203691258 ps
T1103 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.913632940 Feb 08 06:47:22 PM UTC 25 Feb 08 06:47:25 PM UTC 25 96163860 ps
T158 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2181338742 Feb 08 06:47:13 PM UTC 25 Feb 08 06:47:25 PM UTC 25 2920820580 ps
T1104 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1964408804 Feb 08 06:47:23 PM UTC 25 Feb 08 06:47:27 PM UTC 25 94839419 ps
T1105 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1537632780 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:25 PM UTC 25 81984920 ps
T1106 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.817104256 Feb 08 06:47:16 PM UTC 25 Feb 08 06:47:25 PM UTC 25 1065839906 ps
T95 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1370030796 Feb 08 06:47:22 PM UTC 25 Feb 08 06:47:25 PM UTC 25 54725081 ps
T168 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.1709677477 Feb 08 06:47:23 PM UTC 25 Feb 08 06:47:25 PM UTC 25 17921009 ps
T1107 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1582619254 Feb 08 06:47:22 PM UTC 25 Feb 08 06:47:25 PM UTC 25 97761518 ps
T1108 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.3602764119 Feb 08 06:47:09 PM UTC 25 Feb 08 06:47:26 PM UTC 25 3520110781 ps
T176 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.399305688 Feb 08 06:47:22 PM UTC 25 Feb 08 06:47:26 PM UTC 25 114114874 ps
T1109 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.4271744139 Feb 08 06:47:22 PM UTC 25 Feb 08 06:47:26 PM UTC 25 108210972 ps
T1110 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3689676461 Feb 08 06:47:23 PM UTC 25 Feb 08 06:47:26 PM UTC 25 17398582 ps
T128 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.1318811031 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:26 PM UTC 25 69891276 ps
T122 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.2400441995 Feb 08 06:47:21 PM UTC 25 Feb 08 06:47:26 PM UTC 25 203131587 ps
T169 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1518125799 Feb 08 06:47:25 PM UTC 25 Feb 08 06:47:27 PM UTC 25 31769217 ps
T1111 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3650741627 Feb 08 06:47:25 PM UTC 25 Feb 08 06:47:27 PM UTC 25 96872606 ps
T159 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.952340327 Feb 08 06:47:25 PM UTC 25 Feb 08 06:47:27 PM UTC 25 91137247 ps
T1112 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3326453693 Feb 08 06:47:24 PM UTC 25 Feb 08 06:47:27 PM UTC 25 55661769 ps
T160 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3939088394 Feb 08 06:47:24 PM UTC 25 Feb 08 06:47:27 PM UTC 25 234586232 ps
T161 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.834500116 Feb 08 06:47:25 PM UTC 25 Feb 08 06:47:28 PM UTC 25 63178889 ps
T1113 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.4222060240 Feb 08 06:47:25 PM UTC 25 Feb 08 06:47:28 PM UTC 25 349964752 ps
T1114 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1809291658 Feb 08 06:47:25 PM UTC 25 Feb 08 06:47:28 PM UTC 25 149555480 ps
T1115 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1533700347 Feb 08 06:47:36 PM UTC 25 Feb 08 06:47:38 PM UTC 25 67234403 ps
T1116 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2501785029 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:28 PM UTC 25 24562444 ps
T1117 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4078576203 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:28 PM UTC 25 45163572 ps
T1118 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.616667690 Feb 08 06:47:36 PM UTC 25 Feb 08 06:47:38 PM UTC 25 19138904 ps
T181 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.563123909 Feb 08 06:47:23 PM UTC 25 Feb 08 06:47:29 PM UTC 25 110103656 ps
T1119 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3026199373 Feb 08 06:47:27 PM UTC 25 Feb 08 06:47:29 PM UTC 25 13462451 ps
T1120 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3362717423 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:29 PM UTC 25 24801748 ps
T1121 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3091509976 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:29 PM UTC 25 110625415 ps
T1122 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.3510941177 Feb 08 06:47:27 PM UTC 25 Feb 08 06:47:29 PM UTC 25 19015369 ps
T1123 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.1642184296 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:29 PM UTC 25 28898292 ps
T1124 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.874200258 Feb 08 06:47:27 PM UTC 25 Feb 08 06:47:30 PM UTC 25 126848843 ps
T1125 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2868284578 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:39 PM UTC 25 189877381 ps
T1126 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.705472083 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:30 PM UTC 25 322077008 ps
T182 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1406242563 Feb 08 06:47:35 PM UTC 25 Feb 08 06:47:38 PM UTC 25 92616356 ps
T1127 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.4104139666 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:30 PM UTC 25 314541645 ps
T178 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.2767293235 Feb 08 06:47:25 PM UTC 25 Feb 08 06:47:30 PM UTC 25 837119348 ps
T1128 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.2929800280 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:30 PM UTC 25 538438561 ps
T1129 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.835651575 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:30 PM UTC 25 82082293 ps
T1130 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3205945367 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:30 PM UTC 25 1062917667 ps
T1131 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.719510812 Feb 08 06:47:28 PM UTC 25 Feb 08 06:47:30 PM UTC 25 21627276 ps
T1132 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1686063023 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:31 PM UTC 25 51843518 ps
T1133 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.15004691 Feb 08 06:47:27 PM UTC 25 Feb 08 06:47:31 PM UTC 25 250101013 ps
T1134 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1129776134 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:31 PM UTC 25 1049368398 ps
T1135 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.2090238122 Feb 08 06:47:28 PM UTC 25 Feb 08 06:47:31 PM UTC 25 22365495 ps
T1136 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1152692880 Feb 08 06:47:28 PM UTC 25 Feb 08 06:47:31 PM UTC 25 33539815 ps
T1137 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3970885301 Feb 08 06:47:28 PM UTC 25 Feb 08 06:47:31 PM UTC 25 72075809 ps
T1138 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3546197452 Feb 08 06:47:28 PM UTC 25 Feb 08 06:47:31 PM UTC 25 131672389 ps
T1139 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2585619817 Feb 08 06:47:29 PM UTC 25 Feb 08 06:47:32 PM UTC 25 16152214 ps
T1140 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.1009468481 Feb 08 06:47:26 PM UTC 25 Feb 08 06:47:32 PM UTC 25 186574997 ps
T1141 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.234527628 Feb 08 06:47:29 PM UTC 25 Feb 08 06:47:32 PM UTC 25 61369938 ps
T1142 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1441054458 Feb 08 06:47:28 PM UTC 25 Feb 08 06:47:32 PM UTC 25 283007702 ps
T1143 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3633258627 Feb 08 06:47:28 PM UTC 25 Feb 08 06:47:32 PM UTC 25 84272783 ps
T1144 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2845436106 Feb 08 06:47:28 PM UTC 25 Feb 08 06:47:32 PM UTC 25 125032621 ps
T1145 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1585823144 Feb 08 06:47:29 PM UTC 25 Feb 08 06:47:32 PM UTC 25 51831686 ps
T177 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3596589203 Feb 08 06:47:27 PM UTC 25 Feb 08 06:47:32 PM UTC 25 208315921 ps
T1146 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2963803671 Feb 08 06:47:29 PM UTC 25 Feb 08 06:47:32 PM UTC 25 75036195 ps
T1147 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.2338400549 Feb 08 06:47:31 PM UTC 25 Feb 08 06:47:33 PM UTC 25 23017831 ps
T1148 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2450215095 Feb 08 06:47:29 PM UTC 25 Feb 08 06:47:33 PM UTC 25 283534469 ps
T1149 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.837398322 Feb 08 06:47:29 PM UTC 25 Feb 08 06:47:33 PM UTC 25 218351973 ps
T1150 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.350239338 Feb 08 06:47:31 PM UTC 25 Feb 08 06:47:33 PM UTC 25 47243961 ps
T1151 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2726350717 Feb 08 06:47:30 PM UTC 25 Feb 08 06:47:33 PM UTC 25 50512407 ps
T1152 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1791029237 Feb 08 06:47:29 PM UTC 25 Feb 08 06:47:33 PM UTC 25 665666333 ps
T1153 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2523396867 Feb 08 06:47:35 PM UTC 25 Feb 08 06:47:39 PM UTC 25 114579284 ps
T179 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.2072308931 Feb 08 06:47:28 PM UTC 25 Feb 08 06:47:34 PM UTC 25 380203719 ps
T1154 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.453280077 Feb 08 06:47:30 PM UTC 25 Feb 08 06:47:34 PM UTC 25 144676133 ps
T1155 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.797346122 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:34 PM UTC 25 54253208 ps
T1156 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2108707597 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:34 PM UTC 25 83239041 ps
T1157 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.333915273 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:35 PM UTC 25 228556639 ps
T1158 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1978326791 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:35 PM UTC 25 33465850 ps
T1159 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2128998255 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:35 PM UTC 25 205172715 ps
T1160 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2936276035 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:35 PM UTC 25 42575919 ps
T1161 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2570251020 Feb 08 06:47:30 PM UTC 25 Feb 08 06:47:35 PM UTC 25 133715084 ps
T1162 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1122808408 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:35 PM UTC 25 668008969 ps
T1163 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3734341081 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:35 PM UTC 25 191297523 ps
T1164 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4284226663 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:35 PM UTC 25 140693137 ps
T180 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3392169554 Feb 08 06:47:31 PM UTC 25 Feb 08 06:47:35 PM UTC 25 193325203 ps
T1165 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1314745899 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:36 PM UTC 25 24722902 ps
T1166 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2441729732 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:36 PM UTC 25 38754874 ps
T1167 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2755093997 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:36 PM UTC 25 472929025 ps
T1168 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.790680794 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:36 PM UTC 25 82414420 ps
T1169 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1581850645 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:36 PM UTC 25 99672843 ps
T1170 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3555754610 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:36 PM UTC 25 66594343 ps
T1171 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2107854228 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:36 PM UTC 25 175491399 ps
T1172 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1748633417 Feb 08 06:47:15 PM UTC 25 Feb 08 06:47:36 PM UTC 25 5219418059 ps
T1173 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.192932534 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:36 PM UTC 25 284417230 ps
T1174 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3905362840 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:37 PM UTC 25 226930578 ps
T1175 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1156769594 Feb 08 06:47:32 PM UTC 25 Feb 08 06:47:37 PM UTC 25 126357732 ps
T1176 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1430358187 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:37 PM UTC 25 430526437 ps
T1177 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.4265989815 Feb 08 06:47:35 PM UTC 25 Feb 08 06:47:37 PM UTC 25 16808513 ps
T1178 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3318017875 Feb 08 06:47:35 PM UTC 25 Feb 08 06:47:37 PM UTC 25 83182765 ps
T1179 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.762656155 Feb 08 06:47:34 PM UTC 25 Feb 08 06:47:37 PM UTC 25 75920024 ps
T1180 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2084237320 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:37 PM UTC 25 101250026 ps
T1181 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1379334974 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:37 PM UTC 25 82690789 ps
T1182 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2197055123 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:37 PM UTC 25 242783757 ps
T1183 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.1277196585 Feb 08 06:47:17 PM UTC 25 Feb 08 06:47:38 PM UTC 25 2681525732 ps
T1184 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1397475839 Feb 08 06:47:34 PM UTC 25 Feb 08 06:47:38 PM UTC 25 309953431 ps
T1185 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2316527181 Feb 08 06:47:36 PM UTC 25 Feb 08 06:47:38 PM UTC 25 286328442 ps
T1186 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1388089618 Feb 08 06:47:33 PM UTC 25 Feb 08 06:47:39 PM UTC 25 326815914 ps
T1187 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1678268456 Feb 08 06:47:36 PM UTC 25 Feb 08 06:47:39 PM UTC 25 23640330 ps
T1188 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2042799355 Feb 08 06:47:36 PM UTC 25 Feb 08 06:47:39 PM UTC 25 25393157 ps
T1189 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.698335239 Feb 08 06:47:35 PM UTC 25 Feb 08 06:47:39 PM UTC 25 523556083 ps
T1190 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2560910264 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:39 PM UTC 25 17574907 ps
T1191 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2483335162 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:39 PM UTC 25 25541180 ps
T1192 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2779222748 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:39 PM UTC 25 76552315 ps
T1193 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.3706172758 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:39 PM UTC 25 62453418 ps
T1194 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.251993980 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:40 PM UTC 25 62762607 ps
T1195 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.650857134 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:40 PM UTC 25 54289978 ps
T1196 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3630273151 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:40 PM UTC 25 190199103 ps
T1197 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2569079840 Feb 08 06:47:36 PM UTC 25 Feb 08 06:47:40 PM UTC 25 123163879 ps
T1198 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1635950902 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:40 PM UTC 25 157993644 ps
T1199 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.553561186 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:40 PM UTC 25 280817443 ps
T1200 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.826105313 Feb 08 06:47:36 PM UTC 25 Feb 08 06:47:40 PM UTC 25 100913121 ps
T1201 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2378983011 Feb 08 06:47:36 PM UTC 25 Feb 08 06:47:41 PM UTC 25 145973388 ps
T1202 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3374991409 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 16421755 ps
T1203 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3331147340 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 14988464 ps
T1204 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2940272796 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 17053934 ps
T1205 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.113581066 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 37276556 ps
T1206 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2752290124 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 16518774 ps
T1207 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2524227078 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:41 PM UTC 25 650769550 ps
T1208 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.4050041567 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 16344737 ps
T1209 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.1260519002 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 21597732 ps
T1210 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2199457906 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:41 PM UTC 25 66375529 ps
T1211 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.4028637688 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 22612302 ps
T1212 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.794651436 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 36455329 ps
T1213 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.3442607330 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 75608852 ps
T1214 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.1886788694 Feb 08 06:47:19 PM UTC 25 Feb 08 06:47:41 PM UTC 25 1537322936 ps
T1215 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.4079218393 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 82037325 ps
T1216 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1586113818 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 20702850 ps
T1217 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3797189530 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:41 PM UTC 25 155140659 ps
T1218 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3439185858 Feb 08 06:47:39 PM UTC 25 Feb 08 06:47:41 PM UTC 25 39438454 ps
T1219 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.4037249107 Feb 08 06:47:37 PM UTC 25 Feb 08 06:47:42 PM UTC 25 485991433 ps
T1220 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2446571365 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:42 PM UTC 25 18289510 ps
T1221 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.740966753 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:42 PM UTC 25 46106447 ps
T1222 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3021049961 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:42 PM UTC 25 11192079 ps
T1223 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2165816017 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:42 PM UTC 25 18962634 ps
T1224 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2824396998 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:42 PM UTC 25 26379639 ps
T1225 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.4228450772 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:42 PM UTC 25 19409907 ps
T1226 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1329004688 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:42 PM UTC 25 41409675 ps
T1227 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2851427739 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:43 PM UTC 25 17033436 ps
T1228 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.3837226786 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:43 PM UTC 25 10744210 ps
T1229 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.3465356609 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:43 PM UTC 25 50415596 ps
T1230 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.423166151 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:43 PM UTC 25 116708973 ps
T1231 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.1756980975 Feb 08 06:47:40 PM UTC 25 Feb 08 06:47:43 PM UTC 25 14158472 ps
T1232 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1030900225 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:44 PM UTC 25 13373060 ps
T1233 /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2652816849 Feb 08 06:47:42 PM UTC 25 Feb 08 06:47:44 PM UTC 25 11649849 ps

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_app_with_partial_data.1173691405
Short name T9
Test name
Test status
Simulation time 2000776102 ps
CPU time 71.72 seconds
Started Feb 08 09:19:55 PM UTC 25
Finished Feb 08 09:21:09 PM UTC 25
Peak memory 259996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173691405 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1173691405 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_intg_err.3775052304
Short name T116
Test name
Test status
Simulation time 274685440 ps
CPU time 4.61 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:14 PM UTC 25
Peak memory 225116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775052304 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.3775052304 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_sec_cm.1119152445
Short name T16
Test name
Test status
Simulation time 13586611560 ps
CPU time 86.5 seconds
Started Feb 08 09:22:41 PM UTC 25
Finished Feb 08 09:24:10 PM UTC 25
Peak memory 285804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119152445 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1119152445 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_error.2233363032
Short name T18
Test name
Test status
Simulation time 17463928341 ps
CPU time 632.5 seconds
Started Feb 08 09:21:13 PM UTC 25
Finished Feb 08 09:31:53 PM UTC 25
Peak memory 643040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233363032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.kmac_error.2233363032 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_key_error.4250702443
Short name T7
Test name
Test status
Simulation time 1608923283 ps
CPU time 20.16 seconds
Started Feb 08 09:21:31 PM UTC 25
Finished Feb 08 09:21:52 PM UTC 25
Peak memory 227156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250702443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.kmac_key_error.4250702443 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all_with_rand_reset.2809644541
Short name T49
Test name
Test status
Simulation time 318599386647 ps
CPU time 1379.67 seconds
Started Feb 08 09:30:11 PM UTC 25
Finished Feb 08 09:53:27 PM UTC 25
Peak memory 530792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809644541 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.2809644541 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_lc_escalation.167797329
Short name T17
Test name
Test status
Simulation time 52420694 ps
CPU time 2.13 seconds
Started Feb 08 09:30:05 PM UTC 25
Finished Feb 08 09:30:08 PM UTC 25
Peak memory 231476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167797329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.167797329 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_stress_all.2694690401
Short name T12
Test name
Test status
Simulation time 1249137499 ps
CPU time 88.47 seconds
Started Feb 08 09:22:09 PM UTC 25
Finished Feb 08 09:23:39 PM UTC 25
Peak memory 258308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694690401 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2694690401 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.2668206644
Short name T91
Test name
Test status
Simulation time 348074570 ps
CPU time 2.76 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:17 PM UTC 25
Peak memory 229760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668206644 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.2668206644 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_lc_escalation.2686929416
Short name T56
Test name
Test status
Simulation time 109138715 ps
CPU time 2.16 seconds
Started Feb 08 11:08:48 PM UTC 25
Finished Feb 08 11:08:51 PM UTC 25
Peak memory 233592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686929416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.2686929416 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_ready_error.934973431
Short name T4
Test name
Test status
Simulation time 24666890449 ps
CPU time 108.01 seconds
Started Feb 08 09:22:00 PM UTC 25
Finished Feb 08 09:23:51 PM UTC 25
Peak memory 233764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934973431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_en
tropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.934973431 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_intr_test.1533700347
Short name T1115
Test name
Test status
Simulation time 67234403 ps
CPU time 0.9 seconds
Started Feb 08 06:47:36 PM UTC 25
Finished Feb 08 06:47:38 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533700347 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.1533700347 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_edn_timeout_error.2589739606
Short name T72
Test name
Test status
Simulation time 73710386 ps
CPU time 1.45 seconds
Started Feb 08 09:37:27 PM UTC 25
Finished Feb 08 09:37:29 PM UTC 25
Peak memory 227156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589739606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2589739606 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_lc_escalation.3085921362
Short name T47
Test name
Test status
Simulation time 2428834578 ps
CPU time 46.5 seconds
Started Feb 08 10:04:16 PM UTC 25
Finished Feb 08 10:05:04 PM UTC 25
Peak memory 251956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085921362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3085921362 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_lc_escalation.2724752982
Short name T64
Test name
Test status
Simulation time 48352396 ps
CPU time 2.02 seconds
Started Feb 08 10:47:22 PM UTC 25
Finished Feb 08 10:47:25 PM UTC 25
Peak memory 231540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724752982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2724752982 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_stress_all.2514433993
Short name T43
Test name
Test status
Simulation time 24394255790 ps
CPU time 697.81 seconds
Started Feb 08 09:30:09 PM UTC 25
Finished Feb 08 09:41:56 PM UTC 25
Peak memory 334128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514433993 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2514433993 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_mode_error.3011677421
Short name T37
Test name
Test status
Simulation time 42823367 ps
CPU time 1.55 seconds
Started Feb 08 09:21:57 PM UTC 25
Finished Feb 08 09:22:00 PM UTC 25
Peak memory 224152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011677421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3011677421 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_partial_access.764390609
Short name T139
Test name
Test status
Simulation time 114549076 ps
CPU time 1.31 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:11 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764390609 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.764390609 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_lc_escalation.2269824038
Short name T11
Test name
Test status
Simulation time 156563605 ps
CPU time 2.86 seconds
Started Feb 08 09:22:04 PM UTC 25
Finished Feb 08 09:22:07 PM UTC 25
Peak memory 233588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269824038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2269824038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_lc_escalation.4234672064
Short name T82
Test name
Test status
Simulation time 378001745 ps
CPU time 2.2 seconds
Started Feb 08 10:31:47 PM UTC 25
Finished Feb 08 10:31:51 PM UTC 25
Peak memory 233512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234672064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.4234672064 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_lc_escalation.3813275673
Short name T67
Test name
Test status
Simulation time 40911358 ps
CPU time 2.11 seconds
Started Feb 09 12:27:13 AM UTC 25
Finished Feb 09 12:27:16 AM UTC 25
Peak memory 231412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813275673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3813275673 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_alert_test.2041775918
Short name T39
Test name
Test status
Simulation time 98961819 ps
CPU time 1.29 seconds
Started Feb 08 09:23:40 PM UTC 25
Finished Feb 08 09:23:43 PM UTC 25
Peak memory 226228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041775918 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2041775918 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_256.2949190429
Short name T186
Test name
Test status
Simulation time 19175259069 ps
CPU time 2249.99 seconds
Started Feb 08 09:24:22 PM UTC 25
Finished Feb 08 10:02:18 PM UTC 25
Peak memory 1150816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949190429 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2949190429 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_intg_err.3596589203
Short name T177
Test name
Test status
Simulation time 208315921 ps
CPU time 4.38 seconds
Started Feb 08 06:47:27 PM UTC 25
Finished Feb 08 06:47:32 PM UTC 25
Peak memory 225180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596589203 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.3596589203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_smoke.541467360
Short name T193
Test name
Test status
Simulation time 12920899864 ps
CPU time 53.32 seconds
Started Feb 08 09:37:58 PM UTC 25
Finished Feb 08 09:38:53 PM UTC 25
Peak memory 235476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541467360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 3.kmac_smoke.541467360 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3426515494
Short name T87
Test name
Test status
Simulation time 113449256 ps
CPU time 1.69 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:11 PM UTC 25
Peak memory 225980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426515494 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.3426515494 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_refresh.3091630382
Short name T75
Test name
Test status
Simulation time 9160532098 ps
CPU time 256.01 seconds
Started Feb 08 11:13:25 PM UTC 25
Finished Feb 08 11:17:45 PM UTC 25
Peak memory 364452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091630382 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3091630382 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_intr_test.1452250575
Short name T165
Test name
Test status
Simulation time 34946168 ps
CPU time 1.16 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:22 PM UTC 25
Peak memory 223984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452250575 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1452250575 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_intg_err.3615862030
Short name T118
Test name
Test status
Simulation time 260915752 ps
CPU time 4.4 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:18 PM UTC 25
Peak memory 225172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615862030 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.3615862030 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_key_error.1213548554
Short name T98
Test name
Test status
Simulation time 1006676416 ps
CPU time 11.02 seconds
Started Feb 09 12:22:04 AM UTC 25
Finished Feb 09 12:22:16 AM UTC 25
Peak memory 229192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213548554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 24.kmac_key_error.1213548554 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_intg_err.2400441995
Short name T122
Test name
Test status
Simulation time 203131587 ps
CPU time 4.2 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:26 PM UTC 25
Peak memory 225308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400441995 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.2400441995 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_refresh.851104803
Short name T79
Test name
Test status
Simulation time 11079083985 ps
CPU time 262.26 seconds
Started Feb 08 09:26:38 PM UTC 25
Finished Feb 08 09:31:04 PM UTC 25
Peak memory 372772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851104803 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.851104803 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_stress_all.2610998780
Short name T252
Test name
Test status
Simulation time 21654584089 ps
CPU time 1927.42 seconds
Started Feb 08 09:43:30 PM UTC 25
Finished Feb 08 10:16:00 PM UTC 25
Peak memory 497964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610998780 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2610998780 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_smoke.1433995960
Short name T45
Test name
Test status
Simulation time 635214794 ps
CPU time 35.59 seconds
Started Feb 08 09:23:44 PM UTC 25
Finished Feb 08 09:24:21 PM UTC 25
Peak memory 235416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433995960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 1.kmac_smoke.1433995960 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3205945367
Short name T1130
Test name
Test status
Simulation time 1062917667 ps
CPU time 2.57 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:30 PM UTC 25
Peak memory 229696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205945367 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.3205945367 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_error.1492366891
Short name T544
Test name
Test status
Simulation time 26530725658 ps
CPU time 495.64 seconds
Started Feb 09 12:08:09 AM UTC 25
Finished Feb 09 12:16:32 AM UTC 25
Peak memory 366472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492366891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 22.kmac_error.1492366891 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_sec_cm.2544579521
Short name T34
Test name
Test status
Simulation time 3979796253 ps
CPU time 67.55 seconds
Started Feb 08 09:30:19 PM UTC 25
Finished Feb 08 09:31:28 PM UTC 25
Peak memory 281712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544579521 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2544579521 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_aliasing.3577488548
Short name T1094
Test name
Test status
Simulation time 144810067 ps
CPU time 7.65 seconds
Started Feb 08 06:47:12 PM UTC 25
Finished Feb 08 06:47:21 PM UTC 25
Peak memory 225248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577488548 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.3577488548 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_bit_bash.3602764119
Short name T1108
Test name
Test status
Simulation time 3520110781 ps
CPU time 14.79 seconds
Started Feb 08 06:47:09 PM UTC 25
Finished Feb 08 06:47:26 PM UTC 25
Peak memory 225152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602764119 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3602764119 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_hw_reset.1218645793
Short name T120
Test name
Test status
Simulation time 17259537 ps
CPU time 1.03 seconds
Started Feb 08 06:47:09 PM UTC 25
Finished Feb 08 06:47:12 PM UTC 25
Peak memory 223996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218645793 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1218645793 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.505480775
Short name T131
Test name
Test status
Simulation time 315928923 ps
CPU time 2.72 seconds
Started Feb 08 06:47:12 PM UTC 25
Finished Feb 08 06:47:17 PM UTC 25
Peak memory 229280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50
5480775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.5054
80775 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_csr_rw.3380983531
Short name T183
Test name
Test status
Simulation time 21133142 ps
CPU time 0.92 seconds
Started Feb 08 06:47:09 PM UTC 25
Finished Feb 08 06:47:12 PM UTC 25
Peak memory 223932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380983531 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3380983531 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_intr_test.1769146785
Short name T119
Test name
Test status
Simulation time 15745164 ps
CPU time 0.76 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 224108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769146785 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1769146785 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_mem_walk.2982572434
Short name T1081
Test name
Test status
Simulation time 16889579 ps
CPU time 1.04 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:10 PM UTC 25
Peak memory 224048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982572434 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2982572434 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2993554749
Short name T1083
Test name
Test status
Simulation time 78089982 ps
CPU time 1.4 seconds
Started Feb 08 06:47:12 PM UTC 25
Finished Feb 08 06:47:15 PM UTC 25
Peak memory 224052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993554749 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.2993554749 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.321110420
Short name T90
Test name
Test status
Simulation time 471058617 ps
CPU time 2.32 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:12 PM UTC 25
Peak memory 229760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321110420 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.321110420 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/0.kmac_tl_errors.3044422830
Short name T112
Test name
Test status
Simulation time 161259484 ps
CPU time 3.22 seconds
Started Feb 08 06:47:08 PM UTC 25
Finished Feb 08 06:47:13 PM UTC 25
Peak memory 225252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044422830 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3044422830 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_aliasing.1632152380
Short name T1088
Test name
Test status
Simulation time 81656941 ps
CPU time 3.88 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:18 PM UTC 25
Peak memory 225072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632152380 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.1632152380 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_bit_bash.2181338742
Short name T158
Test name
Test status
Simulation time 2920820580 ps
CPU time 10.61 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 225276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181338742 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.2181338742 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_hw_reset.2672059336
Short name T1084
Test name
Test status
Simulation time 61136855 ps
CPU time 1.26 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:15 PM UTC 25
Peak memory 223936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672059336 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2672059336 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1429367614
Short name T130
Test name
Test status
Simulation time 79604175 ps
CPU time 1.88 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:16 PM UTC 25
Peak memory 227976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14
29367614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.142
9367614 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_csr_rw.3068514581
Short name T184
Test name
Test status
Simulation time 23127982 ps
CPU time 1.2 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:15 PM UTC 25
Peak memory 223932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068514581 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3068514581 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_intr_test.1322757493
Short name T121
Test name
Test status
Simulation time 47201581 ps
CPU time 0.99 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:15 PM UTC 25
Peak memory 224000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322757493 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.1322757493 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_partial_access.719450292
Short name T140
Test name
Test status
Simulation time 495110871 ps
CPU time 1.54 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:15 PM UTC 25
Peak memory 223880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719450292 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial_access.719450292 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_mem_walk.2632576911
Short name T1082
Test name
Test status
Simulation time 10469170 ps
CPU time 1.12 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:15 PM UTC 25
Peak memory 224048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632576911 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2632576911 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3318157661
Short name T154
Test name
Test status
Simulation time 202463335 ps
CPU time 2.54 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:17 PM UTC 25
Peak memory 225184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318157661 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.3318157661 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_shadow_reg_errors.109328521
Short name T97
Test name
Test status
Simulation time 22748566 ps
CPU time 1.17 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:15 PM UTC 25
Peak memory 223876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109328521 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.109328521 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/1.kmac_tl_errors.3093549270
Short name T125
Test name
Test status
Simulation time 373632189 ps
CPU time 3.24 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:17 PM UTC 25
Peak memory 225320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093549270 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3093549270 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.15004691
Short name T1133
Test name
Test status
Simulation time 250101013 ps
CPU time 2.33 seconds
Started Feb 08 06:47:27 PM UTC 25
Finished Feb 08 06:47:31 PM UTC 25
Peak memory 231328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15
004691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1500
4691 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_csr_rw.3510941177
Short name T1122
Test name
Test status
Simulation time 19015369 ps
CPU time 1.15 seconds
Started Feb 08 06:47:27 PM UTC 25
Finished Feb 08 06:47:29 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510941177 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3510941177 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_intr_test.3026199373
Short name T1119
Test name
Test status
Simulation time 13462451 ps
CPU time 0.85 seconds
Started Feb 08 06:47:27 PM UTC 25
Finished Feb 08 06:47:29 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026199373 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3026199373 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_same_csr_outstanding.874200258
Short name T1124
Test name
Test status
Simulation time 126848843 ps
CPU time 1.57 seconds
Started Feb 08 06:47:27 PM UTC 25
Finished Feb 08 06:47:30 PM UTC 25
Peak memory 224000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874200258 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr_outstanding.874200258 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3362717423
Short name T1120
Test name
Test status
Simulation time 24801748 ps
CPU time 1.13 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:29 PM UTC 25
Peak memory 223932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362717423 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.3362717423 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/10.kmac_tl_errors.1009468481
Short name T1140
Test name
Test status
Simulation time 186574997 ps
CPU time 3.93 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:32 PM UTC 25
Peak memory 225236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009468481 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1009468481 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1441054458
Short name T1142
Test name
Test status
Simulation time 283007702 ps
CPU time 2.51 seconds
Started Feb 08 06:47:28 PM UTC 25
Finished Feb 08 06:47:32 PM UTC 25
Peak memory 229352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14
41054458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.14
41054458 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_csr_rw.2090238122
Short name T1135
Test name
Test status
Simulation time 22365495 ps
CPU time 1.2 seconds
Started Feb 08 06:47:28 PM UTC 25
Finished Feb 08 06:47:31 PM UTC 25
Peak memory 223856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090238122 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2090238122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_intr_test.719510812
Short name T1131
Test name
Test status
Simulation time 21627276 ps
CPU time 0.99 seconds
Started Feb 08 06:47:28 PM UTC 25
Finished Feb 08 06:47:30 PM UTC 25
Peak memory 223856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719510812 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.719510812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_same_csr_outstanding.3633258627
Short name T1143
Test name
Test status
Simulation time 84272783 ps
CPU time 2.59 seconds
Started Feb 08 06:47:28 PM UTC 25
Finished Feb 08 06:47:32 PM UTC 25
Peak memory 225192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633258627 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr_outstanding.3633258627 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1152692880
Short name T1136
Test name
Test status
Simulation time 33539815 ps
CPU time 1.5 seconds
Started Feb 08 06:47:28 PM UTC 25
Finished Feb 08 06:47:31 PM UTC 25
Peak memory 223888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152692880 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.1152692880 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3546197452
Short name T1138
Test name
Test status
Simulation time 131672389 ps
CPU time 1.96 seconds
Started Feb 08 06:47:28 PM UTC 25
Finished Feb 08 06:47:31 PM UTC 25
Peak memory 228032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546197452 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.3546197452 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_errors.2845436106
Short name T1144
Test name
Test status
Simulation time 125032621 ps
CPU time 3 seconds
Started Feb 08 06:47:28 PM UTC 25
Finished Feb 08 06:47:32 PM UTC 25
Peak memory 225212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845436106 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2845436106 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/11.kmac_tl_intg_err.2072308931
Short name T179
Test name
Test status
Simulation time 380203719 ps
CPU time 4.66 seconds
Started Feb 08 06:47:28 PM UTC 25
Finished Feb 08 06:47:34 PM UTC 25
Peak memory 225180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072308931 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2072308931 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2963803671
Short name T1146
Test name
Test status
Simulation time 75036195 ps
CPU time 1.65 seconds
Started Feb 08 06:47:29 PM UTC 25
Finished Feb 08 06:47:32 PM UTC 25
Peak memory 228084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29
63803671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.29
63803671 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_csr_rw.234527628
Short name T1141
Test name
Test status
Simulation time 61369938 ps
CPU time 1.09 seconds
Started Feb 08 06:47:29 PM UTC 25
Finished Feb 08 06:47:32 PM UTC 25
Peak memory 223872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234527628 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.234527628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_intr_test.2585619817
Short name T1139
Test name
Test status
Simulation time 16152214 ps
CPU time 0.91 seconds
Started Feb 08 06:47:29 PM UTC 25
Finished Feb 08 06:47:32 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585619817 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.2585619817 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1585823144
Short name T1145
Test name
Test status
Simulation time 51831686 ps
CPU time 1.62 seconds
Started Feb 08 06:47:29 PM UTC 25
Finished Feb 08 06:47:32 PM UTC 25
Peak memory 224000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585823144 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_csr_outstanding.1585823144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors.3970885301
Short name T1137
Test name
Test status
Simulation time 72075809 ps
CPU time 1.5 seconds
Started Feb 08 06:47:28 PM UTC 25
Finished Feb 08 06:47:31 PM UTC 25
Peak memory 225980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970885301 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.3970885301 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.837398322
Short name T1149
Test name
Test status
Simulation time 218351973 ps
CPU time 2.12 seconds
Started Feb 08 06:47:29 PM UTC 25
Finished Feb 08 06:47:33 PM UTC 25
Peak memory 229720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837398322 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.837398322 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_errors.2450215095
Short name T1148
Test name
Test status
Simulation time 283534469 ps
CPU time 2.04 seconds
Started Feb 08 06:47:29 PM UTC 25
Finished Feb 08 06:47:33 PM UTC 25
Peak memory 225196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450215095 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.2450215095 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/12.kmac_tl_intg_err.1791029237
Short name T1152
Test name
Test status
Simulation time 665666333 ps
CPU time 2.45 seconds
Started Feb 08 06:47:29 PM UTC 25
Finished Feb 08 06:47:33 PM UTC 25
Peak memory 225124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791029237 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1791029237 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1122808408
Short name T1162
Test name
Test status
Simulation time 668008969 ps
CPU time 2.39 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:35 PM UTC 25
Peak memory 231316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11
22808408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.11
22808408 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_csr_rw.350239338
Short name T1150
Test name
Test status
Simulation time 47243961 ps
CPU time 1.19 seconds
Started Feb 08 06:47:31 PM UTC 25
Finished Feb 08 06:47:33 PM UTC 25
Peak memory 223928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350239338 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.350239338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_intr_test.2338400549
Short name T1147
Test name
Test status
Simulation time 23017831 ps
CPU time 0.76 seconds
Started Feb 08 06:47:31 PM UTC 25
Finished Feb 08 06:47:33 PM UTC 25
Peak memory 223952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338400549 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2338400549 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2755093997
Short name T1167
Test name
Test status
Simulation time 472929025 ps
CPU time 2.81 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:36 PM UTC 25
Peak memory 225188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755093997 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr_outstanding.2755093997 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors.2726350717
Short name T1151
Test name
Test status
Simulation time 50512407 ps
CPU time 1.39 seconds
Started Feb 08 06:47:30 PM UTC 25
Finished Feb 08 06:47:33 PM UTC 25
Peak memory 225980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726350717 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.2726350717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.453280077
Short name T1154
Test name
Test status
Simulation time 144676133 ps
CPU time 2.25 seconds
Started Feb 08 06:47:30 PM UTC 25
Finished Feb 08 06:47:34 PM UTC 25
Peak memory 229888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453280077 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.453280077 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_errors.2570251020
Short name T1161
Test name
Test status
Simulation time 133715084 ps
CPU time 3.3 seconds
Started Feb 08 06:47:30 PM UTC 25
Finished Feb 08 06:47:35 PM UTC 25
Peak memory 225240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570251020 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.2570251020 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/13.kmac_tl_intg_err.3392169554
Short name T180
Test name
Test status
Simulation time 193325203 ps
CPU time 3.58 seconds
Started Feb 08 06:47:31 PM UTC 25
Finished Feb 08 06:47:35 PM UTC 25
Peak memory 225184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392169554 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3392169554 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.790680794
Short name T1168
Test name
Test status
Simulation time 82414420 ps
CPU time 2.47 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:36 PM UTC 25
Peak memory 231380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79
0680794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.790
680794 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_csr_rw.333915273
Short name T1157
Test name
Test status
Simulation time 228556639 ps
CPU time 1.25 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:35 PM UTC 25
Peak memory 223988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333915273 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.333915273 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_intr_test.797346122
Short name T1155
Test name
Test status
Simulation time 54253208 ps
CPU time 0.81 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:34 PM UTC 25
Peak memory 223860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797346122 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.797346122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_same_csr_outstanding.2936276035
Short name T1160
Test name
Test status
Simulation time 42575919 ps
CPU time 1.62 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:35 PM UTC 25
Peak memory 224060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936276035 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr_outstanding.2936276035 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2108707597
Short name T1156
Test name
Test status
Simulation time 83239041 ps
CPU time 1.09 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:34 PM UTC 25
Peak memory 223932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108707597 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.2108707597 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.2128998255
Short name T1159
Test name
Test status
Simulation time 205172715 ps
CPU time 1.75 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:35 PM UTC 25
Peak memory 223884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128998255 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.2128998255 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_errors.1156769594
Short name T1175
Test name
Test status
Simulation time 126357732 ps
CPU time 3.4 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 225388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156769594 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1156769594 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/14.kmac_tl_intg_err.192932534
Short name T1173
Test name
Test status
Simulation time 284417230 ps
CPU time 3.08 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:36 PM UTC 25
Peak memory 225008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192932534 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.192932534 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.1379334974
Short name T1181
Test name
Test status
Simulation time 82690789 ps
CPU time 2.69 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 231316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13
79334974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.13
79334974 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_csr_rw.2107854228
Short name T1171
Test name
Test status
Simulation time 175491399 ps
CPU time 1.35 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:36 PM UTC 25
Peak memory 223936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107854228 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2107854228 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_intr_test.1314745899
Short name T1165
Test name
Test status
Simulation time 24722902 ps
CPU time 1 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:36 PM UTC 25
Peak memory 223944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314745899 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.1314745899 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3905362840
Short name T1174
Test name
Test status
Simulation time 226930578 ps
CPU time 2.06 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 225128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905362840 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_csr_outstanding.3905362840 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1978326791
Short name T1158
Test name
Test status
Simulation time 33465850 ps
CPU time 1.14 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:35 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978326791 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.1978326791 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4284226663
Short name T1164
Test name
Test status
Simulation time 140693137 ps
CPU time 2.13 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:35 PM UTC 25
Peak memory 229692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284226663 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.4284226663 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_errors.3734341081
Short name T1163
Test name
Test status
Simulation time 191297523 ps
CPU time 1.87 seconds
Started Feb 08 06:47:32 PM UTC 25
Finished Feb 08 06:47:35 PM UTC 25
Peak memory 224052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734341081 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3734341081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/15.kmac_tl_intg_err.2084237320
Short name T1180
Test name
Test status
Simulation time 101250026 ps
CPU time 2.65 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 225096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084237320 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2084237320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.1397475839
Short name T1184
Test name
Test status
Simulation time 309953431 ps
CPU time 2.53 seconds
Started Feb 08 06:47:34 PM UTC 25
Finished Feb 08 06:47:38 PM UTC 25
Peak memory 231448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13
97475839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.13
97475839 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_csr_rw.2441729732
Short name T1166
Test name
Test status
Simulation time 38754874 ps
CPU time 0.87 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:36 PM UTC 25
Peak memory 223880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441729732 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2441729732 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_intr_test.3555754610
Short name T1170
Test name
Test status
Simulation time 66594343 ps
CPU time 1.01 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:36 PM UTC 25
Peak memory 224520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555754610 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3555754610 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2197055123
Short name T1182
Test name
Test status
Simulation time 242783757 ps
CPU time 2.46 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 225124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197055123 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr_outstanding.2197055123 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1581850645
Short name T1169
Test name
Test status
Simulation time 99672843 ps
CPU time 1.11 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:36 PM UTC 25
Peak memory 223880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581850645 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.1581850645 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1430358187
Short name T1176
Test name
Test status
Simulation time 430526437 ps
CPU time 2.1 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 225400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430358187 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.1430358187 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_errors.2868284578
Short name T1125
Test name
Test status
Simulation time 189877381 ps
CPU time 4.33 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 225128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868284578 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2868284578 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/16.kmac_tl_intg_err.1388089618
Short name T1186
Test name
Test status
Simulation time 326815914 ps
CPU time 3.76 seconds
Started Feb 08 06:47:33 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 225056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388089618 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1388089618 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.1678268456
Short name T1187
Test name
Test status
Simulation time 23640330 ps
CPU time 1.69 seconds
Started Feb 08 06:47:36 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 229916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16
78268456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.16
78268456 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_csr_rw.3318017875
Short name T1178
Test name
Test status
Simulation time 83182765 ps
CPU time 1.03 seconds
Started Feb 08 06:47:35 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 223996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318017875 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3318017875 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_intr_test.4265989815
Short name T1177
Test name
Test status
Simulation time 16808513 ps
CPU time 0.88 seconds
Started Feb 08 06:47:35 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 224200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265989815 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.4265989815 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2042799355
Short name T1188
Test name
Test status
Simulation time 25393157 ps
CPU time 1.69 seconds
Started Feb 08 06:47:36 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 223892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042799355 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_csr_outstanding.2042799355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors.762656155
Short name T1179
Test name
Test status
Simulation time 75920024 ps
CPU time 1.23 seconds
Started Feb 08 06:47:34 PM UTC 25
Finished Feb 08 06:47:37 PM UTC 25
Peak memory 223932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762656155 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.762656155 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.698335239
Short name T1189
Test name
Test status
Simulation time 523556083 ps
CPU time 3.09 seconds
Started Feb 08 06:47:35 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 225660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698335239 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.698335239 +enable_masking=
1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_errors.2523396867
Short name T1153
Test name
Test status
Simulation time 114579284 ps
CPU time 3.01 seconds
Started Feb 08 06:47:35 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 225244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523396867 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2523396867 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/17.kmac_tl_intg_err.1406242563
Short name T182
Test name
Test status
Simulation time 92616356 ps
CPU time 2.35 seconds
Started Feb 08 06:47:35 PM UTC 25
Finished Feb 08 06:47:38 PM UTC 25
Peak memory 225224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406242563 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1406242563 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2524227078
Short name T1207
Test name
Test status
Simulation time 650769550 ps
CPU time 2.64 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 231316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25
24227078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.25
24227078 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_csr_rw.616667690
Short name T1118
Test name
Test status
Simulation time 19138904 ps
CPU time 1.07 seconds
Started Feb 08 06:47:36 PM UTC 25
Finished Feb 08 06:47:38 PM UTC 25
Peak memory 223872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616667690 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.616667690 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_same_csr_outstanding.3630273151
Short name T1196
Test name
Test status
Simulation time 190199103 ps
CPU time 1.56 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:40 PM UTC 25
Peak memory 223960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630273151 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_outstanding.3630273151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors.2316527181
Short name T1185
Test name
Test status
Simulation time 286328442 ps
CPU time 1.33 seconds
Started Feb 08 06:47:36 PM UTC 25
Finished Feb 08 06:47:38 PM UTC 25
Peak memory 225976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316527181 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.2316527181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2569079840
Short name T1197
Test name
Test status
Simulation time 123163879 ps
CPU time 2.83 seconds
Started Feb 08 06:47:36 PM UTC 25
Finished Feb 08 06:47:40 PM UTC 25
Peak memory 229756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569079840 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.2569079840 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_errors.2378983011
Short name T1201
Test name
Test status
Simulation time 145973388 ps
CPU time 3.52 seconds
Started Feb 08 06:47:36 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 225304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378983011 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.2378983011 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/18.kmac_tl_intg_err.826105313
Short name T1200
Test name
Test status
Simulation time 100913121 ps
CPU time 3.09 seconds
Started Feb 08 06:47:36 PM UTC 25
Finished Feb 08 06:47:40 PM UTC 25
Peak memory 225160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826105313 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.826105313 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2199457906
Short name T1210
Test name
Test status
Simulation time 66375529 ps
CPU time 2.35 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 231448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21
99457906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.21
99457906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_csr_rw.251993980
Short name T1194
Test name
Test status
Simulation time 62762607 ps
CPU time 0.94 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:40 PM UTC 25
Peak memory 223928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251993980 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.251993980 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_intr_test.650857134
Short name T1195
Test name
Test status
Simulation time 54289978 ps
CPU time 1.1 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:40 PM UTC 25
Peak memory 224468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650857134 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.650857134 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_same_csr_outstanding.553561186
Short name T1199
Test name
Test status
Simulation time 280817443 ps
CPU time 1.65 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:40 PM UTC 25
Peak memory 223888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553561186 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr_outstanding.553561186 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors.2560910264
Short name T1190
Test name
Test status
Simulation time 17574907 ps
CPU time 1 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 223912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560910264 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.2560910264 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1635950902
Short name T1198
Test name
Test status
Simulation time 157993644 ps
CPU time 1.61 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:40 PM UTC 25
Peak memory 223936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635950902 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.1635950902 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_errors.4037249107
Short name T1219
Test name
Test status
Simulation time 485991433 ps
CPU time 3.6 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:42 PM UTC 25
Peak memory 225248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037249107 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.4037249107 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/19.kmac_tl_intg_err.3797189530
Short name T1217
Test name
Test status
Simulation time 155140659 ps
CPU time 2.85 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 225252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797189530 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.3797189530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_aliasing.817104256
Short name T1106
Test name
Test status
Simulation time 1065839906 ps
CPU time 7.8 seconds
Started Feb 08 06:47:16 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 225188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817104256 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.817104256 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_bit_bash.1748633417
Short name T1172
Test name
Test status
Simulation time 5219418059 ps
CPU time 20.23 seconds
Started Feb 08 06:47:15 PM UTC 25
Finished Feb 08 06:47:36 PM UTC 25
Peak memory 225076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748633417 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1748633417 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_hw_reset.1390049037
Short name T1087
Test name
Test status
Simulation time 28701158 ps
CPU time 1.48 seconds
Started Feb 08 06:47:15 PM UTC 25
Finished Feb 08 06:47:17 PM UTC 25
Peak memory 223936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390049037 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1390049037 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1103588953
Short name T138
Test name
Test status
Simulation time 284249488 ps
CPU time 2.95 seconds
Started Feb 08 06:47:16 PM UTC 25
Finished Feb 08 06:47:20 PM UTC 25
Peak memory 231324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11
03588953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.110
3588953 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_csr_rw.3702401380
Short name T1086
Test name
Test status
Simulation time 47787686 ps
CPU time 1.17 seconds
Started Feb 08 06:47:15 PM UTC 25
Finished Feb 08 06:47:17 PM UTC 25
Peak memory 223812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702401380 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3702401380 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_intr_test.4003577052
Short name T163
Test name
Test status
Simulation time 46191427 ps
CPU time 1.07 seconds
Started Feb 08 06:47:15 PM UTC 25
Finished Feb 08 06:47:17 PM UTC 25
Peak memory 224000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003577052 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.4003577052 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_partial_access.598221513
Short name T141
Test name
Test status
Simulation time 45924431 ps
CPU time 1.8 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:16 PM UTC 25
Peak memory 223968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598221513 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial_access.598221513 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_mem_walk.927900362
Short name T1085
Test name
Test status
Simulation time 15107557 ps
CPU time 1.08 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:16 PM UTC 25
Peak memory 223884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927900362 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.927900362 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3369172170
Short name T155
Test name
Test status
Simulation time 69156955 ps
CPU time 1.86 seconds
Started Feb 08 06:47:16 PM UTC 25
Finished Feb 08 06:47:19 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369172170 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.3369172170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1698756399
Short name T88
Test name
Test status
Simulation time 96180457 ps
CPU time 1.6 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:16 PM UTC 25
Peak memory 225928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698756399 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.1698756399 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3106654802
Short name T89
Test name
Test status
Simulation time 53472230 ps
CPU time 1.82 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:16 PM UTC 25
Peak memory 228088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106654802 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.3106654802 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_errors.788179590
Short name T123
Test name
Test status
Simulation time 278763734 ps
CPU time 2.05 seconds
Started Feb 08 06:47:13 PM UTC 25
Finished Feb 08 06:47:17 PM UTC 25
Peak memory 225368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788179590 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.788179590 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/2.kmac_tl_intg_err.2223458641
Short name T117
Test name
Test status
Simulation time 182698632 ps
CPU time 2.55 seconds
Started Feb 08 06:47:14 PM UTC 25
Finished Feb 08 06:47:18 PM UTC 25
Peak memory 225116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223458641 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.2223458641 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/20.kmac_intr_test.3706172758
Short name T1193
Test name
Test status
Simulation time 62453418 ps
CPU time 0.86 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706172758 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3706172758 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/21.kmac_intr_test.2483335162
Short name T1191
Test name
Test status
Simulation time 25541180 ps
CPU time 0.78 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483335162 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2483335162 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/22.kmac_intr_test.2779222748
Short name T1192
Test name
Test status
Simulation time 76552315 ps
CPU time 0.79 seconds
Started Feb 08 06:47:37 PM UTC 25
Finished Feb 08 06:47:39 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779222748 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.2779222748 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/23.kmac_intr_test.1260519002
Short name T1209
Test name
Test status
Simulation time 21597732 ps
CPU time 1.02 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 223876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260519002 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1260519002 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/24.kmac_intr_test.3374991409
Short name T1202
Test name
Test status
Simulation time 16421755 ps
CPU time 0.9 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 224140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374991409 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.3374991409 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/25.kmac_intr_test.2940272796
Short name T1204
Test name
Test status
Simulation time 17053934 ps
CPU time 0.86 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940272796 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2940272796 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/26.kmac_intr_test.4028637688
Short name T1211
Test name
Test status
Simulation time 22612302 ps
CPU time 1.07 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 224292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028637688 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.4028637688 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/27.kmac_intr_test.113581066
Short name T1205
Test name
Test status
Simulation time 37276556 ps
CPU time 0.77 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 223996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113581066 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.113581066 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/28.kmac_intr_test.3331147340
Short name T1203
Test name
Test status
Simulation time 14988464 ps
CPU time 0.81 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 224028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331147340 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3331147340 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/29.kmac_intr_test.2752290124
Short name T1206
Test name
Test status
Simulation time 16518774 ps
CPU time 0.83 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 223952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752290124 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2752290124 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_aliasing.42558461
Short name T1099
Test name
Test status
Simulation time 199904791 ps
CPU time 4.83 seconds
Started Feb 08 06:47:17 PM UTC 25
Finished Feb 08 06:47:24 PM UTC 25
Peak memory 225224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42558461 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.42558461 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_bit_bash.1277196585
Short name T1183
Test name
Test status
Simulation time 2681525732 ps
CPU time 18.93 seconds
Started Feb 08 06:47:17 PM UTC 25
Finished Feb 08 06:47:38 PM UTC 25
Peak memory 225084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277196585 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1277196585 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_hw_reset.2337552484
Short name T1091
Test name
Test status
Simulation time 24193263 ps
CPU time 1.03 seconds
Started Feb 08 06:47:17 PM UTC 25
Finished Feb 08 06:47:20 PM UTC 25
Peak memory 223776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337552484 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2337552484 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.699997645
Short name T156
Test name
Test status
Simulation time 398820338 ps
CPU time 2.68 seconds
Started Feb 08 06:47:18 PM UTC 25
Finished Feb 08 06:47:21 PM UTC 25
Peak memory 231520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69
9997645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.6999
97645 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_csr_rw.966423807
Short name T1093
Test name
Test status
Simulation time 58655907 ps
CPU time 1.21 seconds
Started Feb 08 06:47:17 PM UTC 25
Finished Feb 08 06:47:20 PM UTC 25
Peak memory 223932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966423807 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.966423807 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_intr_test.2982097021
Short name T164
Test name
Test status
Simulation time 16028323 ps
CPU time 0.88 seconds
Started Feb 08 06:47:17 PM UTC 25
Finished Feb 08 06:47:19 PM UTC 25
Peak memory 224000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982097021 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2982097021 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_partial_access.3480512081
Short name T142
Test name
Test status
Simulation time 43922074 ps
CPU time 1.59 seconds
Started Feb 08 06:47:16 PM UTC 25
Finished Feb 08 06:47:19 PM UTC 25
Peak memory 223868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480512081 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial_access.3480512081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_mem_walk.3770009998
Short name T1089
Test name
Test status
Simulation time 24872791 ps
CPU time 0.88 seconds
Started Feb 08 06:47:16 PM UTC 25
Finished Feb 08 06:47:18 PM UTC 25
Peak memory 224168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770009998 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3770009998 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_same_csr_outstanding.973588161
Short name T157
Test name
Test status
Simulation time 116175752 ps
CPU time 3.1 seconds
Started Feb 08 06:47:18 PM UTC 25
Finished Feb 08 06:47:22 PM UTC 25
Peak memory 225184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973588161 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.973588161 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors.544604896
Short name T1090
Test name
Test status
Simulation time 22033331 ps
CPU time 0.99 seconds
Started Feb 08 06:47:16 PM UTC 25
Finished Feb 08 06:47:18 PM UTC 25
Peak memory 223928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544604896 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.544604896 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3772776758
Short name T185
Test name
Test status
Simulation time 27666487 ps
CPU time 1.84 seconds
Started Feb 08 06:47:16 PM UTC 25
Finished Feb 08 06:47:19 PM UTC 25
Peak memory 225984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772776758 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.3772776758 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_errors.3111758908
Short name T126
Test name
Test status
Simulation time 294562303 ps
CPU time 2.31 seconds
Started Feb 08 06:47:16 PM UTC 25
Finished Feb 08 06:47:20 PM UTC 25
Peak memory 225448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111758908 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3111758908 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/3.kmac_tl_intg_err.1261963600
Short name T132
Test name
Test status
Simulation time 149407642 ps
CPU time 2.57 seconds
Started Feb 08 06:47:16 PM UTC 25
Finished Feb 08 06:47:20 PM UTC 25
Peak memory 225176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261963600 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.1261963600 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/30.kmac_intr_test.4050041567
Short name T1208
Test name
Test status
Simulation time 16344737 ps
CPU time 0.82 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 224200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050041567 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.4050041567 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/31.kmac_intr_test.3442607330
Short name T1213
Test name
Test status
Simulation time 75608852 ps
CPU time 0.96 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 224464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442607330 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3442607330 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/32.kmac_intr_test.4079218393
Short name T1215
Test name
Test status
Simulation time 82037325 ps
CPU time 0.92 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 223944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079218393 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.4079218393 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/33.kmac_intr_test.3439185858
Short name T1218
Test name
Test status
Simulation time 39438454 ps
CPU time 0.94 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 223944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439185858 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3439185858 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/34.kmac_intr_test.1586113818
Short name T1216
Test name
Test status
Simulation time 20702850 ps
CPU time 0.9 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586113818 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1586113818 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/35.kmac_intr_test.794651436
Short name T1212
Test name
Test status
Simulation time 36455329 ps
CPU time 0.8 seconds
Started Feb 08 06:47:39 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 223996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794651436 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.794651436 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/36.kmac_intr_test.740966753
Short name T1221
Test name
Test status
Simulation time 46106447 ps
CPU time 0.84 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:42 PM UTC 25
Peak memory 224464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740966753 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.740966753 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/37.kmac_intr_test.2446571365
Short name T1220
Test name
Test status
Simulation time 18289510 ps
CPU time 0.79 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:42 PM UTC 25
Peak memory 223952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446571365 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2446571365 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/38.kmac_intr_test.2824396998
Short name T1224
Test name
Test status
Simulation time 26379639 ps
CPU time 0.96 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:42 PM UTC 25
Peak memory 223944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824396998 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2824396998 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/39.kmac_intr_test.3021049961
Short name T1222
Test name
Test status
Simulation time 11192079 ps
CPU time 0.87 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:42 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021049961 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3021049961 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_aliasing.1129776134
Short name T1134
Test name
Test status
Simulation time 1049368398 ps
CPU time 10.09 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:31 PM UTC 25
Peak memory 225012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129776134 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1129776134 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_bit_bash.1886788694
Short name T1214
Test name
Test status
Simulation time 1537322936 ps
CPU time 20.5 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:41 PM UTC 25
Peak memory 225308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886788694 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1886788694 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_hw_reset.2068323159
Short name T1095
Test name
Test status
Simulation time 49555443 ps
CPU time 1.04 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:21 PM UTC 25
Peak memory 223836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068323159 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.2068323159 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1481394034
Short name T170
Test name
Test status
Simulation time 252046170 ps
CPU time 2.65 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:23 PM UTC 25
Peak memory 231392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14
81394034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.148
1394034 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_csr_rw.2478236766
Short name T1096
Test name
Test status
Simulation time 42228244 ps
CPU time 1.26 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:22 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478236766 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2478236766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_partial_access.2359248972
Short name T143
Test name
Test status
Simulation time 49614201 ps
CPU time 1.38 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:22 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359248972 -assert nopostproc +UVM_TEST
NAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partial_access.2359248972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_mem_walk.3091606403
Short name T1092
Test name
Test status
Simulation time 16300013 ps
CPU time 0.75 seconds
Started Feb 08 06:47:18 PM UTC 25
Finished Feb 08 06:47:20 PM UTC 25
Peak memory 224076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091606403 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3091606403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1033334332
Short name T1097
Test name
Test status
Simulation time 79279974 ps
CPU time 1.45 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:22 PM UTC 25
Peak memory 223996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033334332 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.1033334332 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors.540754200
Short name T92
Test name
Test status
Simulation time 164372920 ps
CPU time 1.14 seconds
Started Feb 08 06:47:18 PM UTC 25
Finished Feb 08 06:47:20 PM UTC 25
Peak memory 225924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540754200 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.540754200 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.833537760
Short name T93
Test name
Test status
Simulation time 271352327 ps
CPU time 2.72 seconds
Started Feb 08 06:47:18 PM UTC 25
Finished Feb 08 06:47:22 PM UTC 25
Peak memory 229760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833537760 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.833537760 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_errors.3013568317
Short name T124
Test name
Test status
Simulation time 53901047 ps
CPU time 1.78 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:22 PM UTC 25
Peak memory 223952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013568317 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3013568317 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/4.kmac_tl_intg_err.1221781314
Short name T175
Test name
Test status
Simulation time 211374451 ps
CPU time 3.91 seconds
Started Feb 08 06:47:19 PM UTC 25
Finished Feb 08 06:47:24 PM UTC 25
Peak memory 225176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221781314 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.1221781314 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/40.kmac_intr_test.2165816017
Short name T1223
Test name
Test status
Simulation time 18962634 ps
CPU time 0.8 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:42 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165816017 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2165816017 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/41.kmac_intr_test.3837226786
Short name T1228
Test name
Test status
Simulation time 10744210 ps
CPU time 0.86 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:43 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837226786 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3837226786 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/42.kmac_intr_test.2851427739
Short name T1227
Test name
Test status
Simulation time 17033436 ps
CPU time 0.76 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:43 PM UTC 25
Peak memory 224208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851427739 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.2851427739 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/43.kmac_intr_test.4228450772
Short name T1225
Test name
Test status
Simulation time 19409907 ps
CPU time 0.77 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:42 PM UTC 25
Peak memory 224200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228450772 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.4228450772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/44.kmac_intr_test.423166151
Short name T1230
Test name
Test status
Simulation time 116708973 ps
CPU time 0.84 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:43 PM UTC 25
Peak memory 224408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423166151 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.423166151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/45.kmac_intr_test.1329004688
Short name T1226
Test name
Test status
Simulation time 41409675 ps
CPU time 0.73 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:42 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329004688 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1329004688 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/46.kmac_intr_test.3465356609
Short name T1229
Test name
Test status
Simulation time 50415596 ps
CPU time 0.75 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:43 PM UTC 25
Peak memory 224344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465356609 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3465356609 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/47.kmac_intr_test.1756980975
Short name T1231
Test name
Test status
Simulation time 14158472 ps
CPU time 0.77 seconds
Started Feb 08 06:47:40 PM UTC 25
Finished Feb 08 06:47:43 PM UTC 25
Peak memory 224080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756980975 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1756980975 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/48.kmac_intr_test.1030900225
Short name T1232
Test name
Test status
Simulation time 13373060 ps
CPU time 0.78 seconds
Started Feb 08 06:47:42 PM UTC 25
Finished Feb 08 06:47:44 PM UTC 25
Peak memory 223940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030900225 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.1030900225 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/49.kmac_intr_test.2652816849
Short name T1233
Test name
Test status
Simulation time 11649849 ps
CPU time 0.76 seconds
Started Feb 08 06:47:42 PM UTC 25
Finished Feb 08 06:47:44 PM UTC 25
Peak memory 223988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652816849 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2652816849 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1537632780
Short name T1105
Test name
Test status
Simulation time 81984920 ps
CPU time 2.96 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 231320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15
37632780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.153
7632780 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_csr_rw.722737698
Short name T1098
Test name
Test status
Simulation time 71389262 ps
CPU time 1.36 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:23 PM UTC 25
Peak memory 223876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722737698 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.722737698 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_intr_test.1849777594
Short name T166
Test name
Test status
Simulation time 24535498 ps
CPU time 1.18 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:23 PM UTC 25
Peak memory 224000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849777594 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1849777594 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_same_csr_outstanding.851008765
Short name T1100
Test name
Test status
Simulation time 83241217 ps
CPU time 1.94 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:24 PM UTC 25
Peak memory 223996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851008765 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr_outstanding.851008765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors.3426004914
Short name T96
Test name
Test status
Simulation time 44981082 ps
CPU time 1.73 seconds
Started Feb 08 06:47:20 PM UTC 25
Finished Feb 08 06:47:24 PM UTC 25
Peak memory 223932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426004914 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.3426004914 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.427500360
Short name T94
Test name
Test status
Simulation time 31958314 ps
CPU time 1.77 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:23 PM UTC 25
Peak memory 227968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427500360 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.427500360 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/5.kmac_tl_errors.1318811031
Short name T128
Test name
Test status
Simulation time 69891276 ps
CPU time 4.16 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:26 PM UTC 25
Peak memory 225312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318811031 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1318811031 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.4271744139
Short name T1109
Test name
Test status
Simulation time 108210972 ps
CPU time 2.19 seconds
Started Feb 08 06:47:22 PM UTC 25
Finished Feb 08 06:47:26 PM UTC 25
Peak memory 229276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42
71744139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.427
1744139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_csr_rw.2462540631
Short name T1101
Test name
Test status
Simulation time 287745508 ps
CPU time 0.97 seconds
Started Feb 08 06:47:22 PM UTC 25
Finished Feb 08 06:47:24 PM UTC 25
Peak memory 223880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462540631 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.2462540631 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_intr_test.3674386597
Short name T167
Test name
Test status
Simulation time 41168102 ps
CPU time 1.19 seconds
Started Feb 08 06:47:22 PM UTC 25
Finished Feb 08 06:47:24 PM UTC 25
Peak memory 224412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674386597 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3674386597 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_same_csr_outstanding.913632940
Short name T1103
Test name
Test status
Simulation time 96163860 ps
CPU time 1.49 seconds
Started Feb 08 06:47:22 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 224056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913632940 -assert nopostproc +UVM_TES
TNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_outstanding.913632940 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors.440000524
Short name T129
Test name
Test status
Simulation time 30549081 ps
CPU time 1.13 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:23 PM UTC 25
Peak memory 223876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440000524 -assert nopostproc +UVM_TESTNA
ME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.440000524 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.4036703644
Short name T1102
Test name
Test status
Simulation time 203691258 ps
CPU time 2.53 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 227764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036703644 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.4036703644 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_errors.1412992080
Short name T127
Test name
Test status
Simulation time 57305783 ps
CPU time 1.97 seconds
Started Feb 08 06:47:21 PM UTC 25
Finished Feb 08 06:47:24 PM UTC 25
Peak memory 224048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412992080 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1412992080 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/6.kmac_tl_intg_err.399305688
Short name T176
Test name
Test status
Simulation time 114114874 ps
CPU time 2.32 seconds
Started Feb 08 06:47:22 PM UTC 25
Finished Feb 08 06:47:26 PM UTC 25
Peak memory 225180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399305688 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.399305688 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3326453693
Short name T1112
Test name
Test status
Simulation time 55661769 ps
CPU time 1.69 seconds
Started Feb 08 06:47:24 PM UTC 25
Finished Feb 08 06:47:27 PM UTC 25
Peak memory 227976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33
26453693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.332
6453693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_csr_rw.3689676461
Short name T1110
Test name
Test status
Simulation time 17398582 ps
CPU time 1.1 seconds
Started Feb 08 06:47:23 PM UTC 25
Finished Feb 08 06:47:26 PM UTC 25
Peak memory 223880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689676461 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3689676461 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_intr_test.1709677477
Short name T168
Test name
Test status
Simulation time 17921009 ps
CPU time 0.74 seconds
Started Feb 08 06:47:23 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 224248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709677477 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1709677477 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3939088394
Short name T160
Test name
Test status
Simulation time 234586232 ps
CPU time 1.78 seconds
Started Feb 08 06:47:24 PM UTC 25
Finished Feb 08 06:47:27 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939088394 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_outstanding.3939088394 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1582619254
Short name T1107
Test name
Test status
Simulation time 97761518 ps
CPU time 1.83 seconds
Started Feb 08 06:47:22 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 223928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582619254 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.1582619254 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1370030796
Short name T95
Test name
Test status
Simulation time 54725081 ps
CPU time 1.79 seconds
Started Feb 08 06:47:22 PM UTC 25
Finished Feb 08 06:47:25 PM UTC 25
Peak memory 228028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370030796 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.1370030796 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_errors.1964408804
Short name T1104
Test name
Test status
Simulation time 94839419 ps
CPU time 2.37 seconds
Started Feb 08 06:47:23 PM UTC 25
Finished Feb 08 06:47:27 PM UTC 25
Peak memory 225308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964408804 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.1964408804 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/7.kmac_tl_intg_err.563123909
Short name T181
Test name
Test status
Simulation time 110103656 ps
CPU time 3.98 seconds
Started Feb 08 06:47:23 PM UTC 25
Finished Feb 08 06:47:29 PM UTC 25
Peak memory 225028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563123909 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.563123909 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.705472083
Short name T1126
Test name
Test status
Simulation time 322077008 ps
CPU time 2.63 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:30 PM UTC 25
Peak memory 231292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70
5472083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.7054
72083 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_csr_rw.952340327
Short name T159
Test name
Test status
Simulation time 91137247 ps
CPU time 1.16 seconds
Started Feb 08 06:47:25 PM UTC 25
Finished Feb 08 06:47:27 PM UTC 25
Peak memory 223992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952340327 -assert nopostproc +UVM_TESTNAME=kmac_base_te
st +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.952340327 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_intr_test.1518125799
Short name T169
Test name
Test status
Simulation time 31769217 ps
CPU time 0.82 seconds
Started Feb 08 06:47:25 PM UTC 25
Finished Feb 08 06:47:27 PM UTC 25
Peak memory 223952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518125799 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1518125799 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1809291658
Short name T1114
Test name
Test status
Simulation time 149555480 ps
CPU time 2.25 seconds
Started Feb 08 06:47:25 PM UTC 25
Finished Feb 08 06:47:28 PM UTC 25
Peak memory 225248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809291658 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_outstanding.1809291658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3650741627
Short name T1111
Test name
Test status
Simulation time 96872606 ps
CPU time 1.21 seconds
Started Feb 08 06:47:25 PM UTC 25
Finished Feb 08 06:47:27 PM UTC 25
Peak memory 223904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650741627 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.3650741627 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.834500116
Short name T161
Test name
Test status
Simulation time 63178889 ps
CPU time 1.97 seconds
Started Feb 08 06:47:25 PM UTC 25
Finished Feb 08 06:47:28 PM UTC 25
Peak memory 225920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834500116 -assert nopostproc
+UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.834500116 +enable_masking=1
+sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_errors.4222060240
Short name T1113
Test name
Test status
Simulation time 349964752 ps
CPU time 2.22 seconds
Started Feb 08 06:47:25 PM UTC 25
Finished Feb 08 06:47:28 PM UTC 25
Peak memory 225320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222060240 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.4222060240 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/8.kmac_tl_intg_err.2767293235
Short name T178
Test name
Test status
Simulation time 837119348 ps
CPU time 4.43 seconds
Started Feb 08 06:47:25 PM UTC 25
Finished Feb 08 06:47:30 PM UTC 25
Peak memory 225164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767293235 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.2767293235 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.1686063023
Short name T1132
Test name
Test status
Simulation time 51843518 ps
CPU time 2.68 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:31 PM UTC 25
Peak memory 231324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16
86063023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.168
6063023 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_csr_rw.1642184296
Short name T1123
Test name
Test status
Simulation time 28898292 ps
CPU time 1.44 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:29 PM UTC 25
Peak memory 223976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642184296 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.1642184296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_intr_test.4078576203
Short name T1117
Test name
Test status
Simulation time 45163572 ps
CPU time 0.84 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:28 PM UTC 25
Peak memory 224000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078576203 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.4078576203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_same_csr_outstanding.4104139666
Short name T1127
Test name
Test status
Simulation time 314541645 ps
CPU time 2.42 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:30 PM UTC 25
Peak memory 225184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104139666 -assert nopostproc +UVM_TE
STNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_outstanding.4104139666 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2501785029
Short name T1116
Test name
Test status
Simulation time 24562444 ps
CPU time 0.99 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:28 PM UTC 25
Peak memory 223932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501785029 -assert nopostproc +UVM_TESTN
AME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.2501785029 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3091509976
Short name T1121
Test name
Test status
Simulation time 110625415 ps
CPU time 1.65 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:29 PM UTC 25
Peak memory 223812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091509976 -assert nopostpro
c +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.3091509976 +enable_masking
=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_errors.835651575
Short name T1129
Test name
Test status
Simulation time 82082293 ps
CPU time 2.81 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:30 PM UTC 25
Peak memory 225300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835651575 -assert nopostproc +UVM_TESTNAME=kmac_base_test
+UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.835651575 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/cover_reg_top/9.kmac_tl_intg_err.2929800280
Short name T1128
Test name
Test status
Simulation time 538438561 ps
CPU time 2.66 seconds
Started Feb 08 06:47:26 PM UTC 25
Finished Feb 08 06:47:30 PM UTC 25
Peak memory 225180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929800280 -assert nopostproc +UVM_TESTNAME=km
ac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.2929800280 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_app.1304708127
Short name T27
Test name
Test status
Simulation time 170258157675 ps
CPU time 328.14 seconds
Started Feb 08 09:19:50 PM UTC 25
Finished Feb 08 09:25:23 PM UTC 25
Peak memory 387048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304708127 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.1304708127 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_burst_write.2992949428
Short name T144
Test name
Test status
Simulation time 15810687104 ps
CPU time 1420.81 seconds
Started Feb 08 09:17:28 PM UTC 25
Finished Feb 08 09:41:26 PM UTC 25
Peak memory 251868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992949428 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2992949428 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_edn_timeout_error.2682078441
Short name T38
Test name
Test status
Simulation time 394801438 ps
CPU time 13.14 seconds
Started Feb 08 09:21:53 PM UTC 25
Finished Feb 08 09:22:07 PM UTC 25
Peak memory 233320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682078441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2682078441 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_entropy_refresh.2689873182
Short name T13
Test name
Test status
Simulation time 18587716777 ps
CPU time 334.37 seconds
Started Feb 08 09:20:58 PM UTC 25
Finished Feb 08 09:26:37 PM UTC 25
Peak memory 386992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689873182 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.2689873182 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_long_msg_and_output.3548405546
Short name T231
Test name
Test status
Simulation time 311274252893 ps
CPU time 3003.13 seconds
Started Feb 08 09:17:11 PM UTC 25
Finished Feb 08 10:07:46 PM UTC 25
Peak memory 3043328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548405546 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.3548405546 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_mubi.1397171281
Short name T10
Test name
Test status
Simulation time 1948475889 ps
CPU time 15.95 seconds
Started Feb 08 09:21:13 PM UTC 25
Finished Feb 08 09:21:30 PM UTC 25
Peak memory 234244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397171281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_m
ubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 0.kmac_mubi.1397171281 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_sideload.1027221860
Short name T21
Test name
Test status
Simulation time 7010094408 ps
CPU time 266.75 seconds
Started Feb 08 09:17:25 PM UTC 25
Finished Feb 08 09:21:56 PM UTC 25
Peak memory 411544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027221860 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.1027221860 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_smoke.2199150742
Short name T1
Test name
Test status
Simulation time 12668809224 ps
CPU time 64.78 seconds
Started Feb 08 09:16:45 PM UTC 25
Finished Feb 08 09:17:52 PM UTC 25
Peak memory 235556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199150742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.kmac_smoke.2199150742 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac.3029759917
Short name T2
Test name
Test status
Simulation time 464955023 ps
CPU time 8.51 seconds
Started Feb 08 09:19:34 PM UTC 25
Finished Feb 08 09:19:43 PM UTC 25
Peak memory 235364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3029759917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 0.kmac_test_vectors_kmac.3029759917 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_kmac_xof.290679260
Short name T3
Test name
Test status
Simulation time 187323227 ps
CPU time 9.24 seconds
Started Feb 08 09:19:44 PM UTC 25
Finished Feb 08 09:19:54 PM UTC 25
Peak memory 229420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=290679260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 0.kmac_test_vectors_kmac_xof.290679260 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_256.2867198964
Short name T229
Test name
Test status
Simulation time 124162044310 ps
CPU time 2878.77 seconds
Started Feb 08 09:17:56 PM UTC 25
Finished Feb 08 10:06:27 PM UTC 25
Peak memory 3018620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867198964 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2867198964 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_384.1935369977
Short name T217
Test name
Test status
Simulation time 74169838251 ps
CPU time 2633.15 seconds
Started Feb 08 09:18:49 PM UTC 25
Finished Feb 08 10:03:13 PM UTC 25
Peak memory 2430872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935369977 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1935369977 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_sha3_512.3137129990
Short name T188
Test name
Test status
Simulation time 134512490907 ps
CPU time 1547.19 seconds
Started Feb 08 09:18:54 PM UTC 25
Finished Feb 08 09:44:59 PM UTC 25
Peak memory 1763296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137129990 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3137129990 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_128.2854266239
Short name T441
Test name
Test status
Simulation time 187503222041 ps
CPU time 8037.66 seconds
Started Feb 08 09:18:57 PM UTC 25
Finished Feb 08 11:34:18 PM UTC 25
Peak memory 7839464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854266239 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2854266239 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/0.kmac_test_vectors_shake_256.3937485381
Short name T425
Test name
Test status
Simulation time 1304034755533 ps
CPU time 7633.93 seconds
Started Feb 08 09:19:21 PM UTC 25
Finished Feb 08 11:27:55 PM UTC 25
Peak memory 6479584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937485381 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3937485381 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_alert_test.1246744700
Short name T110
Test name
Test status
Simulation time 46842997 ps
CPU time 1.27 seconds
Started Feb 08 09:30:39 PM UTC 25
Finished Feb 08 09:30:42 PM UTC 25
Peak memory 225700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246744700 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1246744700 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_app.1352585110
Short name T40
Test name
Test status
Simulation time 38330818328 ps
CPU time 273.01 seconds
Started Feb 08 09:26:20 PM UTC 25
Finished Feb 08 09:30:57 PM UTC 25
Peak memory 403376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352585110 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1352585110 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_app_with_partial_data.3431233479
Short name T14
Test name
Test status
Simulation time 5216048411 ps
CPU time 267.32 seconds
Started Feb 08 09:26:29 PM UTC 25
Finished Feb 08 09:31:01 PM UTC 25
Peak memory 294828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431233479 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.3431233479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_burst_write.3280295072
Short name T151
Test name
Test status
Simulation time 106335317191 ps
CPU time 1513.44 seconds
Started Feb 08 09:24:21 PM UTC 25
Finished Feb 08 09:49:53 PM UTC 25
Peak memory 266124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280295072 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.3280295072 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_edn_timeout_error.1456964979
Short name T63
Test name
Test status
Simulation time 1909210295 ps
CPU time 12.7 seconds
Started Feb 08 09:29:35 PM UTC 25
Finished Feb 08 09:29:49 PM UTC 25
Peak memory 234556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456964979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1456964979 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_mode_error.2784705139
Short name T41
Test name
Test status
Simulation time 194395380 ps
CPU time 12.71 seconds
Started Feb 08 09:29:50 PM UTC 25
Finished Feb 08 09:30:04 PM UTC 25
Peak memory 235108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784705139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2784705139 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_entropy_ready_error.1009494755
Short name T5
Test name
Test status
Simulation time 2479668837 ps
CPU time 15.01 seconds
Started Feb 08 09:29:54 PM UTC 25
Finished Feb 08 09:30:10 PM UTC 25
Peak memory 235468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009494755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
ntropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1009494755 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_error.1761378867
Short name T19
Test name
Test status
Simulation time 15333775827 ps
CPU time 565.32 seconds
Started Feb 08 09:28:21 PM UTC 25
Finished Feb 08 09:37:54 PM UTC 25
Peak memory 540620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761378867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 1.kmac_error.1761378867 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_key_error.189463382
Short name T8
Test name
Test status
Simulation time 3365060143 ps
CPU time 20.64 seconds
Started Feb 08 09:29:12 PM UTC 25
Finished Feb 08 09:29:33 PM UTC 25
Peak memory 229252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189463382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ke
y_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.kmac_key_error.189463382 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_long_msg_and_output.983610696
Short name T271
Test name
Test status
Simulation time 165069950235 ps
CPU time 3543.24 seconds
Started Feb 08 09:23:52 PM UTC 25
Finished Feb 08 10:23:31 PM UTC 25
Peak memory 3915760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983610696 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.983610696 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_mubi.300762934
Short name T28
Test name
Test status
Simulation time 57975771020 ps
CPU time 326.04 seconds
Started Feb 08 09:28:13 PM UTC 25
Finished Feb 08 09:33:44 PM UTC 25
Peak memory 313620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300762934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mu
bi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 1.kmac_mubi.300762934 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_sideload.2083641186
Short name T24
Test name
Test status
Simulation time 6929516242 ps
CPU time 420.55 seconds
Started Feb 08 09:24:11 PM UTC 25
Finished Feb 08 09:31:17 PM UTC 25
Peak memory 372780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083641186 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2083641186 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac.2978705437
Short name T85
Test name
Test status
Simulation time 421834392 ps
CPU time 8.29 seconds
Started Feb 08 09:26:00 PM UTC 25
Finished Feb 08 09:26:09 PM UTC 25
Peak memory 235360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2978705437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 1.kmac_test_vectors_kmac.2978705437 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_kmac_xof.1868987602
Short name T69
Test name
Test status
Simulation time 536189747 ps
CPU time 8.08 seconds
Started Feb 08 09:26:10 PM UTC 25
Finished Feb 08 09:26:19 PM UTC 25
Peak memory 229452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1868987602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.kmac_test_vectors_kmac_xof.1868987602 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_224.752480776
Short name T192
Test name
Test status
Simulation time 72238342487 ps
CPU time 2904.97 seconds
Started Feb 08 09:24:21 PM UTC 25
Finished Feb 08 10:13:18 PM UTC 25
Peak memory 3229528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752480776 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.752480776 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_384.1898052696
Short name T187
Test name
Test status
Simulation time 186480276103 ps
CPU time 2361.42 seconds
Started Feb 08 09:24:33 PM UTC 25
Finished Feb 08 10:04:21 PM UTC 25
Peak memory 2365276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898052696 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1898052696 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_sha3_512.2961899883
Short name T189
Test name
Test status
Simulation time 183647255489 ps
CPU time 1460.88 seconds
Started Feb 08 09:24:43 PM UTC 25
Finished Feb 08 09:49:20 PM UTC 25
Peak memory 1722184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961899883 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.2961899883 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_128.3693709199
Short name T389
Test name
Test status
Simulation time 252662610773 ps
CPU time 6408.02 seconds
Started Feb 08 09:25:24 PM UTC 25
Finished Feb 08 11:13:23 PM UTC 25
Peak memory 2699096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693709199 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.3693709199 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/1.kmac_test_vectors_shake_256.4138070112
Short name T442
Test name
Test status
Simulation time 265258553991 ps
CPU time 7670.03 seconds
Started Feb 08 09:25:24 PM UTC 25
Finished Feb 08 11:34:37 PM UTC 25
Peak memory 6383556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138070112 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.4138070112 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_alert_test.815412915
Short name T303
Test name
Test status
Simulation time 20838976 ps
CPU time 1.2 seconds
Started Feb 08 10:31:52 PM UTC 25
Finished Feb 08 10:31:54 PM UTC 25
Peak memory 227148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815412915 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.815412915 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_app.2848842322
Short name T309
Test name
Test status
Simulation time 10694602465 ps
CPU time 358.73 seconds
Started Feb 08 10:31:17 PM UTC 25
Finished Feb 08 10:37:21 PM UTC 25
Peak memory 315368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848842322 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.2848842322 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_burst_write.4126462060
Short name T308
Test name
Test status
Simulation time 4404557208 ps
CPU time 463.42 seconds
Started Feb 08 10:29:19 PM UTC 25
Finished Feb 08 10:37:08 PM UTC 25
Peak memory 241560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126462060 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.4126462060 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_edn_timeout_error.1426611999
Short name T300
Test name
Test status
Simulation time 129999733 ps
CPU time 15.55 seconds
Started Feb 08 10:31:27 PM UTC 25
Finished Feb 08 10:31:44 PM UTC 25
Peak memory 231528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426611999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1426611999 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_mode_error.3923106653
Short name T302
Test name
Test status
Simulation time 123566912 ps
CPU time 1.82 seconds
Started Feb 08 10:31:45 PM UTC 25
Finished Feb 08 10:31:48 PM UTC 25
Peak memory 227216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923106653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3923106653 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_entropy_refresh.3524114988
Short name T298
Test name
Test status
Simulation time 83272459 ps
CPU time 6.15 seconds
Started Feb 08 10:31:18 PM UTC 25
Finished Feb 08 10:31:25 PM UTC 25
Peak memory 235424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524114988 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3524114988 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_error.2216301974
Short name T323
Test name
Test status
Simulation time 17529275185 ps
CPU time 644.55 seconds
Started Feb 08 10:31:21 PM UTC 25
Finished Feb 08 10:42:14 PM UTC 25
Peak memory 581596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216301974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 10.kmac_error.2216301974 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_key_error.1966876960
Short name T301
Test name
Test status
Simulation time 1571964247 ps
CPU time 19.11 seconds
Started Feb 08 10:31:26 PM UTC 25
Finished Feb 08 10:31:47 PM UTC 25
Peak memory 227356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966876960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.kmac_key_error.1966876960 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_long_msg_and_output.2807695054
Short name T381
Test name
Test status
Simulation time 21940145616 ps
CPU time 2456.88 seconds
Started Feb 08 10:28:50 PM UTC 25
Finished Feb 08 11:10:13 PM UTC 25
Peak memory 1503280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807695054 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.2807695054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_sideload.3792426596
Short name T306
Test name
Test status
Simulation time 9998098851 ps
CPU time 353.56 seconds
Started Feb 08 10:29:09 PM UTC 25
Finished Feb 08 10:35:07 PM UTC 25
Peak memory 495524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792426596 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3792426596 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_smoke.1202620766
Short name T289
Test name
Test status
Simulation time 2965292035 ps
CPU time 78.26 seconds
Started Feb 08 10:28:29 PM UTC 25
Finished Feb 08 10:29:49 PM UTC 25
Peak memory 233684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202620766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 10.kmac_smoke.1202620766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_stress_all.1081578633
Short name T429
Test name
Test status
Simulation time 616675125478 ps
CPU time 3459.17 seconds
Started Feb 08 10:31:50 PM UTC 25
Finished Feb 08 11:30:06 PM UTC 25
Peak memory 1280332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081578633 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1081578633 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_test_vectors_kmac.1311249783
Short name T295
Test name
Test status
Simulation time 273503380 ps
CPU time 9.32 seconds
Started Feb 08 10:30:54 PM UTC 25
Finished Feb 08 10:31:04 PM UTC 25
Peak memory 235620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1311249783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 10.kmac_test_vectors_kmac.1311249783 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_test_vectors_kmac_xof.3954277147
Short name T296
Test name
Test status
Simulation time 205786931 ps
CPU time 6.88 seconds
Started Feb 08 10:31:05 PM UTC 25
Finished Feb 08 10:31:13 PM UTC 25
Peak memory 229584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3954277147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 10.kmac_test_vectors_kmac_xof.3954277147 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_test_vectors_sha3_224.2563983566
Short name T402
Test name
Test status
Simulation time 98868886038 ps
CPU time 2990.84 seconds
Started Feb 08 10:29:26 PM UTC 25
Finished Feb 08 11:19:48 PM UTC 25
Peak memory 3272540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563983566 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.2563983566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_test_vectors_sha3_256.1218659774
Short name T366
Test name
Test status
Simulation time 160475622348 ps
CPU time 2154.9 seconds
Started Feb 08 10:29:50 PM UTC 25
Finished Feb 08 11:06:10 PM UTC 25
Peak memory 1154888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218659774 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.1218659774 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_test_vectors_sha3_384.430251987
Short name T367
Test name
Test status
Simulation time 122954578759 ps
CPU time 2116.95 seconds
Started Feb 08 10:30:35 PM UTC 25
Finished Feb 08 11:06:15 PM UTC 25
Peak memory 2490208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430251987 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.430251987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_test_vectors_sha3_512.1414388898
Short name T343
Test name
Test status
Simulation time 76695991964 ps
CPU time 1316.8 seconds
Started Feb 08 10:30:38 PM UTC 25
Finished Feb 08 10:52:50 PM UTC 25
Peak memory 712608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414388898 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.1414388898 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_test_vectors_shake_128.2408730749
Short name T550
Test name
Test status
Simulation time 66738918921 ps
CPU time 6335.26 seconds
Started Feb 08 10:30:42 PM UTC 25
Finished Feb 09 12:17:27 AM UTC 25
Peak memory 2742096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408730749 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.2408730749 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/10.kmac_test_vectors_shake_256.155300662
Short name T574
Test name
Test status
Simulation time 903940131048 ps
CPU time 6975.46 seconds
Started Feb 08 10:30:45 PM UTC 25
Finished Feb 09 12:28:12 AM UTC 25
Peak memory 6369108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155300662 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.155300662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_alert_test.1848889581
Short name T321
Test name
Test status
Simulation time 24002423 ps
CPU time 1.27 seconds
Started Feb 08 10:41:21 PM UTC 25
Finished Feb 08 10:41:24 PM UTC 25
Peak memory 226232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848889581 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1848889581 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_app.3481905816
Short name T328
Test name
Test status
Simulation time 51411988706 ps
CPU time 306.04 seconds
Started Feb 08 10:38:56 PM UTC 25
Finished Feb 08 10:44:07 PM UTC 25
Peak memory 317596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481905816 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3481905816 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_burst_write.1283523979
Short name T311
Test name
Test status
Simulation time 5707450202 ps
CPU time 200.96 seconds
Started Feb 08 10:35:09 PM UTC 25
Finished Feb 08 10:38:33 PM UTC 25
Peak memory 251864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283523979 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.1283523979 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_edn_timeout_error.1118602338
Short name T318
Test name
Test status
Simulation time 27607741 ps
CPU time 1.77 seconds
Started Feb 08 10:41:09 PM UTC 25
Finished Feb 08 10:41:12 PM UTC 25
Peak memory 227180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118602338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1118602338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_mode_error.1387190234
Short name T319
Test name
Test status
Simulation time 19898749 ps
CPU time 1.3 seconds
Started Feb 08 10:41:13 PM UTC 25
Finished Feb 08 10:41:15 PM UTC 25
Peak memory 224088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387190234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1387190234 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_entropy_refresh.899742154
Short name T326
Test name
Test status
Simulation time 10102725843 ps
CPU time 241.97 seconds
Started Feb 08 10:39:39 PM UTC 25
Finished Feb 08 10:43:45 PM UTC 25
Peak memory 376800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899742154 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.899742154 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_error.1064715719
Short name T332
Test name
Test status
Simulation time 87513534011 ps
CPU time 383.31 seconds
Started Feb 08 10:40:41 PM UTC 25
Finished Feb 08 10:47:09 PM UTC 25
Peak memory 368544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064715719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 11.kmac_error.1064715719 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_key_error.2626737148
Short name T317
Test name
Test status
Simulation time 3924509995 ps
CPU time 21.1 seconds
Started Feb 08 10:40:46 PM UTC 25
Finished Feb 08 10:41:08 PM UTC 25
Peak memory 227232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626737148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.kmac_key_error.2626737148 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_lc_escalation.1568352424
Short name T53
Test name
Test status
Simulation time 148130486 ps
CPU time 2.81 seconds
Started Feb 08 10:41:16 PM UTC 25
Finished Feb 08 10:41:20 PM UTC 25
Peak memory 233520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568352424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1568352424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_long_msg_and_output.4014699166
Short name T455
Test name
Test status
Simulation time 58555327958 ps
CPU time 3905 seconds
Started Feb 08 10:33:33 PM UTC 25
Finished Feb 08 11:39:22 PM UTC 25
Peak memory 1963928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014699166 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.4014699166 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_sideload.314781086
Short name T307
Test name
Test status
Simulation time 1257551639 ps
CPU time 101.61 seconds
Started Feb 08 10:34:58 PM UTC 25
Finished Feb 08 10:36:41 PM UTC 25
Peak memory 264024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314781086 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.314781086 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_smoke.1792886362
Short name T304
Test name
Test status
Simulation time 4360276488 ps
CPU time 95.81 seconds
Started Feb 08 10:31:55 PM UTC 25
Finished Feb 08 10:33:33 PM UTC 25
Peak memory 239516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792886362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 11.kmac_smoke.1792886362 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_stress_all.882145906
Short name T346
Test name
Test status
Simulation time 23761955473 ps
CPU time 775.65 seconds
Started Feb 08 10:41:18 PM UTC 25
Finished Feb 08 10:54:23 PM UTC 25
Peak memory 446780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882145906 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.882145906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_test_vectors_kmac.3146593004
Short name T312
Test name
Test status
Simulation time 466616186 ps
CPU time 9.33 seconds
Started Feb 08 10:38:34 PM UTC 25
Finished Feb 08 10:38:44 PM UTC 25
Peak memory 235472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3146593004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 11.kmac_test_vectors_kmac.3146593004 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_test_vectors_kmac_xof.297148674
Short name T313
Test name
Test status
Simulation time 1974155979 ps
CPU time 8.95 seconds
Started Feb 08 10:38:45 PM UTC 25
Finished Feb 08 10:38:55 PM UTC 25
Peak memory 227408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=297148674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 11.kmac_test_vectors_kmac_xof.297148674 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_test_vectors_sha3_224.817663562
Short name T408
Test name
Test status
Simulation time 66141199750 ps
CPU time 2775.41 seconds
Started Feb 08 10:35:33 PM UTC 25
Finished Feb 08 11:22:17 PM UTC 25
Peak memory 3280796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817663562 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.817663562 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_test_vectors_sha3_256.308423325
Short name T384
Test name
Test status
Simulation time 70799033598 ps
CPU time 2190.79 seconds
Started Feb 08 10:35:40 PM UTC 25
Finished Feb 08 11:12:35 PM UTC 25
Peak memory 1144728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308423325 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.308423325 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_test_vectors_sha3_384.1213646866
Short name T371
Test name
Test status
Simulation time 96534855215 ps
CPU time 1878.86 seconds
Started Feb 08 10:36:42 PM UTC 25
Finished Feb 08 11:08:22 PM UTC 25
Peak memory 2395992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213646866 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.1213646866 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_test_vectors_sha3_512.263733030
Short name T362
Test name
Test status
Simulation time 33405072797 ps
CPU time 1450.48 seconds
Started Feb 08 10:37:09 PM UTC 25
Finished Feb 08 11:01:36 PM UTC 25
Peak memory 1752912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263733030 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.263733030 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_test_vectors_shake_128.2378661877
Short name T535
Test name
Test status
Simulation time 243004397991 ps
CPU time 5671.18 seconds
Started Feb 08 10:37:21 PM UTC 25
Finished Feb 09 12:12:51 AM UTC 25
Peak memory 2766656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378661877 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.2378661877 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/11.kmac_test_vectors_shake_256.1341138772
Short name T562
Test name
Test status
Simulation time 163312648626 ps
CPU time 6406.98 seconds
Started Feb 08 10:37:25 PM UTC 25
Finished Feb 09 12:25:18 AM UTC 25
Peak memory 6444940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341138772 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.1341138772 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_alert_test.3516830174
Short name T338
Test name
Test status
Simulation time 66324912 ps
CPU time 1.35 seconds
Started Feb 08 10:48:24 PM UTC 25
Finished Feb 08 10:48:27 PM UTC 25
Peak memory 223904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516830174 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3516830174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_app.3256463713
Short name T341
Test name
Test status
Simulation time 22074057795 ps
CPU time 261.75 seconds
Started Feb 08 10:46:03 PM UTC 25
Finished Feb 08 10:50:29 PM UTC 25
Peak memory 317360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256463713 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3256463713 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_burst_write.1609296077
Short name T364
Test name
Test status
Simulation time 21767981619 ps
CPU time 1205.7 seconds
Started Feb 08 10:42:15 PM UTC 25
Finished Feb 08 11:02:36 PM UTC 25
Peak memory 262116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609296077 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1609296077 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_edn_timeout_error.1910362688
Short name T335
Test name
Test status
Simulation time 26550366 ps
CPU time 1.6 seconds
Started Feb 08 10:47:16 PM UTC 25
Finished Feb 08 10:47:18 PM UTC 25
Peak memory 227160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910362688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1910362688 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_mode_error.4282398812
Short name T336
Test name
Test status
Simulation time 65710976 ps
CPU time 1.59 seconds
Started Feb 08 10:47:19 PM UTC 25
Finished Feb 08 10:47:21 PM UTC 25
Peak memory 227168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282398812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.4282398812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_entropy_refresh.439874037
Short name T333
Test name
Test status
Simulation time 586427495 ps
CPU time 15.05 seconds
Started Feb 08 10:46:53 PM UTC 25
Finished Feb 08 10:47:10 PM UTC 25
Peak memory 233580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439874037 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.439874037 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_error.2667963766
Short name T344
Test name
Test status
Simulation time 9945951118 ps
CPU time 366.72 seconds
Started Feb 08 10:47:11 PM UTC 25
Finished Feb 08 10:53:22 PM UTC 25
Peak memory 481188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667963766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 12.kmac_error.2667963766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_key_error.3050120261
Short name T334
Test name
Test status
Simulation time 268605016 ps
CPU time 2.87 seconds
Started Feb 08 10:47:11 PM UTC 25
Finished Feb 08 10:47:14 PM UTC 25
Peak memory 227164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050120261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.kmac_key_error.3050120261 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_long_msg_and_output.3375196913
Short name T448
Test name
Test status
Simulation time 150204814568 ps
CPU time 3386.72 seconds
Started Feb 08 10:41:29 PM UTC 25
Finished Feb 08 11:38:32 PM UTC 25
Peak memory 3434440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375196913 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.3375196913 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_sideload.2599195473
Short name T340
Test name
Test status
Simulation time 17654838532 ps
CPU time 507.89 seconds
Started Feb 08 10:41:42 PM UTC 25
Finished Feb 08 10:50:17 PM UTC 25
Peak memory 602076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599195473 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2599195473 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_smoke.3357266994
Short name T325
Test name
Test status
Simulation time 3347821238 ps
CPU time 99.81 seconds
Started Feb 08 10:41:24 PM UTC 25
Finished Feb 08 10:43:06 PM UTC 25
Peak memory 235612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357266994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 12.kmac_smoke.3357266994 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_stress_all.4280778167
Short name T348
Test name
Test status
Simulation time 9867452894 ps
CPU time 438.88 seconds
Started Feb 08 10:47:26 PM UTC 25
Finished Feb 08 10:54:50 PM UTC 25
Peak memory 436188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280778167 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.4280778167 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_test_vectors_kmac.2188963273
Short name T330
Test name
Test status
Simulation time 275448548 ps
CPU time 9.52 seconds
Started Feb 08 10:45:41 PM UTC 25
Finished Feb 08 10:45:52 PM UTC 25
Peak memory 229556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2188963273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 12.kmac_test_vectors_kmac.2188963273 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_test_vectors_kmac_xof.3812738595
Short name T331
Test name
Test status
Simulation time 3907886541 ps
CPU time 8.63 seconds
Started Feb 08 10:45:53 PM UTC 25
Finished Feb 08 10:46:03 PM UTC 25
Peak memory 229520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3812738595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 12.kmac_test_vectors_kmac_xof.3812738595 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_test_vectors_sha3_224.3319494746
Short name T398
Test name
Test status
Simulation time 41379783294 ps
CPU time 2038.74 seconds
Started Feb 08 10:42:20 PM UTC 25
Finished Feb 08 11:16:40 PM UTC 25
Peak memory 1195920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319494746 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.3319494746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_test_vectors_sha3_256.3102331338
Short name T401
Test name
Test status
Simulation time 39639842930 ps
CPU time 2117.04 seconds
Started Feb 08 10:43:08 PM UTC 25
Finished Feb 08 11:18:49 PM UTC 25
Peak memory 1130440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102331338 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3102331338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_test_vectors_sha3_384.1354763084
Short name T382
Test name
Test status
Simulation time 15622518978 ps
CPU time 1652.59 seconds
Started Feb 08 10:43:46 PM UTC 25
Finished Feb 08 11:11:37 PM UTC 25
Peak memory 938016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354763084 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.1354763084 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_test_vectors_sha3_512.565880684
Short name T391
Test name
Test status
Simulation time 139114583317 ps
CPU time 1871.84 seconds
Started Feb 08 10:44:03 PM UTC 25
Finished Feb 08 11:15:37 PM UTC 25
Peak memory 1750936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565880684 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.565880684 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_test_vectors_shake_128.301471011
Short name T586
Test name
Test status
Simulation time 64919826327 ps
CPU time 6771.27 seconds
Started Feb 08 10:44:07 PM UTC 25
Finished Feb 09 12:38:15 AM UTC 25
Peak memory 2686924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301471011 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.301471011 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/12.kmac_test_vectors_shake_256.3504398131
Short name T516
Test name
Test status
Simulation time 54717840278 ps
CPU time 4778.67 seconds
Started Feb 08 10:44:31 PM UTC 25
Finished Feb 09 12:05:00 AM UTC 25
Peak memory 2242440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504398131 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.3504398131 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_alert_test.721714869
Short name T357
Test name
Test status
Simulation time 61406151 ps
CPU time 1.28 seconds
Started Feb 08 10:59:29 PM UTC 25
Finished Feb 08 10:59:32 PM UTC 25
Peak memory 225948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721714869 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.721714869 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_app.3035480476
Short name T353
Test name
Test status
Simulation time 5133650190 ps
CPU time 125.81 seconds
Started Feb 08 10:55:13 PM UTC 25
Finished Feb 08 10:57:22 PM UTC 25
Peak memory 321512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035480476 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.3035480476 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_burst_write.2708722454
Short name T352
Test name
Test status
Simulation time 14791373114 ps
CPU time 370.77 seconds
Started Feb 08 10:50:30 PM UTC 25
Finished Feb 08 10:56:46 PM UTC 25
Peak memory 251952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708722454 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.2708722454 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_edn_timeout_error.3930470433
Short name T355
Test name
Test status
Simulation time 85984717 ps
CPU time 1.94 seconds
Started Feb 08 10:57:42 PM UTC 25
Finished Feb 08 10:57:45 PM UTC 25
Peak memory 227232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930470433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3930470433 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_entropy_mode_error.1268568987
Short name T356
Test name
Test status
Simulation time 42533383 ps
CPU time 1.88 seconds
Started Feb 08 10:57:46 PM UTC 25
Finished Feb 08 10:57:49 PM UTC 25
Peak memory 227168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268568987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1268568987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_error.3537543728
Short name T359
Test name
Test status
Simulation time 6488333486 ps
CPU time 184.54 seconds
Started Feb 08 10:56:46 PM UTC 25
Finished Feb 08 10:59:54 PM UTC 25
Peak memory 284572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537543728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 13.kmac_error.3537543728 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_key_error.2320858040
Short name T354
Test name
Test status
Simulation time 4330104574 ps
CPU time 18.27 seconds
Started Feb 08 10:57:22 PM UTC 25
Finished Feb 08 10:57:42 PM UTC 25
Peak memory 227280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320858040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.kmac_key_error.2320858040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_lc_escalation.2739435136
Short name T65
Test name
Test status
Simulation time 378523495 ps
CPU time 2.42 seconds
Started Feb 08 10:57:51 PM UTC 25
Finished Feb 08 10:57:54 PM UTC 25
Peak memory 233592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739435136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2739435136 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_long_msg_and_output.1901784203
Short name T480
Test name
Test status
Simulation time 27962317409 ps
CPU time 3559.41 seconds
Started Feb 08 10:49:00 PM UTC 25
Finished Feb 08 11:48:59 PM UTC 25
Peak memory 1902500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901784203 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.1901784203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_sideload.4043937137
Short name T351
Test name
Test status
Simulation time 17256523203 ps
CPU time 361.8 seconds
Started Feb 08 10:50:18 PM UTC 25
Finished Feb 08 10:56:25 PM UTC 25
Peak memory 452652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043937137 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.4043937137 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_smoke.2337764674
Short name T339
Test name
Test status
Simulation time 2991614735 ps
CPU time 30.89 seconds
Started Feb 08 10:48:27 PM UTC 25
Finished Feb 08 10:49:00 PM UTC 25
Peak memory 235484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337764674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 13.kmac_smoke.2337764674 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_stress_all.2378288100
Short name T422
Test name
Test status
Simulation time 76236017520 ps
CPU time 1706.84 seconds
Started Feb 08 10:57:55 PM UTC 25
Finished Feb 08 11:26:41 PM UTC 25
Peak memory 809256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378288100 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2378288100 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_test_vectors_kmac.623255948
Short name T349
Test name
Test status
Simulation time 380695678 ps
CPU time 7.99 seconds
Started Feb 08 10:54:51 PM UTC 25
Finished Feb 08 10:55:00 PM UTC 25
Peak memory 229464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=623255948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 13.kmac_test_vectors_kmac.623255948 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_test_vectors_kmac_xof.1684983134
Short name T350
Test name
Test status
Simulation time 311721323 ps
CPU time 9.65 seconds
Started Feb 08 10:55:01 PM UTC 25
Finished Feb 08 10:55:12 PM UTC 25
Peak memory 229480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1684983134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 13.kmac_test_vectors_kmac_xof.1684983134 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_test_vectors_sha3_224.4070164849
Short name T458
Test name
Test status
Simulation time 66931103366 ps
CPU time 2843.88 seconds
Started Feb 08 10:52:34 PM UTC 25
Finished Feb 08 11:40:30 PM UTC 25
Peak memory 3155924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070164849 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.4070164849 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_test_vectors_sha3_256.3306220501
Short name T433
Test name
Test status
Simulation time 244027610225 ps
CPU time 2244.19 seconds
Started Feb 08 10:52:51 PM UTC 25
Finished Feb 08 11:30:40 PM UTC 25
Peak memory 1179672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306220501 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.3306220501 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_test_vectors_sha3_384.2466509046
Short name T418
Test name
Test status
Simulation time 97668604342 ps
CPU time 1835.78 seconds
Started Feb 08 10:53:24 PM UTC 25
Finished Feb 08 11:24:20 PM UTC 25
Peak memory 2424648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466509046 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.2466509046 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_test_vectors_sha3_512.699009647
Short name T403
Test name
Test status
Simulation time 154858805855 ps
CPU time 1602.41 seconds
Started Feb 08 10:53:45 PM UTC 25
Finished Feb 08 11:20:45 PM UTC 25
Peak memory 1709916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699009647 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.699009647 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_test_vectors_shake_128.1257823777
Short name T672
Test name
Test status
Simulation time 178457464976 ps
CPU time 7984.09 seconds
Started Feb 08 10:54:24 PM UTC 25
Finished Feb 09 01:08:53 AM UTC 25
Peak memory 7915460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257823777 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.1257823777 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/13.kmac_test_vectors_shake_256.2695230548
Short name T597
Test name
Test status
Simulation time 254485977829 ps
CPU time 6419.64 seconds
Started Feb 08 10:54:28 PM UTC 25
Finished Feb 09 12:42:30 AM UTC 25
Peak memory 6408056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695230548 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.2695230548 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_alert_test.3379056144
Short name T376
Test name
Test status
Simulation time 45652506 ps
CPU time 1.23 seconds
Started Feb 08 11:09:07 PM UTC 25
Finished Feb 08 11:09:09 PM UTC 25
Peak memory 225884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379056144 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3379056144 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_app.565926904
Short name T370
Test name
Test status
Simulation time 1852945926 ps
CPU time 111.04 seconds
Started Feb 08 11:06:22 PM UTC 25
Finished Feb 08 11:08:15 PM UTC 25
Peak memory 255856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565926904 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.565926904 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_burst_write.972548007
Short name T417
Test name
Test status
Simulation time 48005423947 ps
CPU time 1377.95 seconds
Started Feb 08 11:00:55 PM UTC 25
Finished Feb 08 11:24:08 PM UTC 25
Peak memory 253864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972548007 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.972548007 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_edn_timeout_error.2089063335
Short name T377
Test name
Test status
Simulation time 1403479556 ps
CPU time 55.97 seconds
Started Feb 08 11:08:28 PM UTC 25
Finished Feb 08 11:09:26 PM UTC 25
Peak memory 235172 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089063335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2089063335 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_mode_error.210321323
Short name T374
Test name
Test status
Simulation time 27006216 ps
CPU time 1.6 seconds
Started Feb 08 11:08:45 PM UTC 25
Finished Feb 08 11:08:47 PM UTC 25
Peak memory 227220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210321323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.210321323 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_entropy_refresh.1978348054
Short name T379
Test name
Test status
Simulation time 9530165703 ps
CPU time 208.05 seconds
Started Feb 08 11:06:27 PM UTC 25
Finished Feb 08 11:09:58 PM UTC 25
Peak memory 286628 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978348054 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1978348054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_error.3996022908
Short name T386
Test name
Test status
Simulation time 15124487820 ps
CPU time 260.93 seconds
Started Feb 08 11:08:16 PM UTC 25
Finished Feb 08 11:12:41 PM UTC 25
Peak memory 417888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996022908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 14.kmac_error.3996022908 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_key_error.1378348887
Short name T373
Test name
Test status
Simulation time 1552672072 ps
CPU time 18.69 seconds
Started Feb 08 11:08:23 PM UTC 25
Finished Feb 08 11:08:43 PM UTC 25
Peak memory 227168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378348887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.kmac_key_error.1378348887 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_long_msg_and_output.3644127331
Short name T443
Test name
Test status
Simulation time 17315469781 ps
CPU time 2085.74 seconds
Started Feb 08 10:59:45 PM UTC 25
Finished Feb 08 11:34:55 PM UTC 25
Peak memory 1214416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644127331 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.3644127331 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_sideload.257252450
Short name T380
Test name
Test status
Simulation time 97741873664 ps
CPU time 607.78 seconds
Started Feb 08 10:59:54 PM UTC 25
Finished Feb 08 11:10:10 PM UTC 25
Peak memory 364516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257252450 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.257252450 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_smoke.3820445040
Short name T358
Test name
Test status
Simulation time 308417705 ps
CPU time 10.21 seconds
Started Feb 08 10:59:33 PM UTC 25
Finished Feb 08 10:59:45 PM UTC 25
Peak memory 235420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820445040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 14.kmac_smoke.3820445040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_stress_all.2158272968
Short name T375
Test name
Test status
Simulation time 1127433655 ps
CPU time 12.43 seconds
Started Feb 08 11:08:52 PM UTC 25
Finished Feb 08 11:09:06 PM UTC 25
Peak memory 243952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158272968 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.2158272968 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_test_vectors_kmac.749726514
Short name T368
Test name
Test status
Simulation time 1669075015 ps
CPU time 8.78 seconds
Started Feb 08 11:06:11 PM UTC 25
Finished Feb 08 11:06:21 PM UTC 25
Peak memory 235432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=749726514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 14.kmac_test_vectors_kmac.749726514 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_test_vectors_kmac_xof.332225445
Short name T369
Test name
Test status
Simulation time 370048865 ps
CPU time 8.09 seconds
Started Feb 08 11:06:17 PM UTC 25
Finished Feb 08 11:06:26 PM UTC 25
Peak memory 227424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=332225445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 14.kmac_test_vectors_kmac_xof.332225445 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_test_vectors_sha3_224.2858312125
Short name T484
Test name
Test status
Simulation time 65474210182 ps
CPU time 2924.29 seconds
Started Feb 08 11:01:02 PM UTC 25
Finished Feb 08 11:50:18 PM UTC 25
Peak memory 3229644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858312125 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.2858312125 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_test_vectors_sha3_256.2951601030
Short name T462
Test name
Test status
Simulation time 61388985192 ps
CPU time 2532.17 seconds
Started Feb 08 11:01:37 PM UTC 25
Finished Feb 08 11:44:17 PM UTC 25
Peak memory 3041176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951601030 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.2951601030 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_test_vectors_sha3_384.526628542
Short name T460
Test name
Test status
Simulation time 199041597144 ps
CPU time 2348.93 seconds
Started Feb 08 11:02:05 PM UTC 25
Finished Feb 08 11:41:41 PM UTC 25
Peak memory 2428752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526628542 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.526628542 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_test_vectors_sha3_512.1879978976
Short name T424
Test name
Test status
Simulation time 69385409832 ps
CPU time 1474.31 seconds
Started Feb 08 11:02:37 PM UTC 25
Finished Feb 08 11:27:28 PM UTC 25
Peak memory 1740684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879978976 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.1879978976 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_test_vectors_shake_128.804166437
Short name T742
Test name
Test status
Simulation time 536663235214 ps
CPU time 9206.53 seconds
Started Feb 08 11:03:33 PM UTC 25
Finished Feb 09 01:38:37 AM UTC 25
Peak memory 7845824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804166437 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.804166437 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/14.kmac_test_vectors_shake_256.1892803110
Short name T630
Test name
Test status
Simulation time 1286075968028 ps
CPU time 6333.17 seconds
Started Feb 08 11:05:00 PM UTC 25
Finished Feb 09 12:51:39 AM UTC 25
Peak memory 6510420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892803110 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.1892803110 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_alert_test.3144254050
Short name T396
Test name
Test status
Simulation time 58104720 ps
CPU time 1.31 seconds
Started Feb 08 11:16:20 PM UTC 25
Finished Feb 08 11:16:22 PM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144254050 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3144254050 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_app.1506401428
Short name T390
Test name
Test status
Simulation time 10631196325 ps
CPU time 149.63 seconds
Started Feb 08 11:13:02 PM UTC 25
Finished Feb 08 11:15:35 PM UTC 25
Peak memory 331696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506401428 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1506401428 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_burst_write.1277730398
Short name T409
Test name
Test status
Simulation time 30568462300 ps
CPU time 767.42 seconds
Started Feb 08 11:09:59 PM UTC 25
Finished Feb 08 11:22:56 PM UTC 25
Peak memory 252012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277730398 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1277730398 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_edn_timeout_error.3234006818
Short name T395
Test name
Test status
Simulation time 1098107743 ps
CPU time 27.23 seconds
Started Feb 08 11:15:50 PM UTC 25
Finished Feb 08 11:16:19 PM UTC 25
Peak memory 251692 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234006818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3234006818 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_entropy_mode_error.3101142188
Short name T394
Test name
Test status
Simulation time 65201432 ps
CPU time 1.5 seconds
Started Feb 08 11:16:01 PM UTC 25
Finished Feb 08 11:16:04 PM UTC 25
Peak memory 227168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101142188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.3101142188 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_error.2965597381
Short name T400
Test name
Test status
Simulation time 14318801324 ps
CPU time 138.18 seconds
Started Feb 08 11:15:36 PM UTC 25
Finished Feb 08 11:17:57 PM UTC 25
Peak memory 303068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965597381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.kmac_error.2965597381 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_key_error.3690862969
Short name T392
Test name
Test status
Simulation time 957294113 ps
CPU time 10.19 seconds
Started Feb 08 11:15:38 PM UTC 25
Finished Feb 08 11:15:50 PM UTC 25
Peak memory 227348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690862969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.kmac_key_error.3690862969 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_lc_escalation.1774710025
Short name T83
Test name
Test status
Simulation time 59234141 ps
CPU time 2.18 seconds
Started Feb 08 11:16:04 PM UTC 25
Finished Feb 08 11:16:08 PM UTC 25
Peak memory 233648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774710025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.1774710025 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_long_msg_and_output.1803734276
Short name T518
Test name
Test status
Simulation time 246720313105 ps
CPU time 3344.62 seconds
Started Feb 08 11:09:27 PM UTC 25
Finished Feb 09 12:05:48 AM UTC 25
Peak memory 3452836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803734276 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.1803734276 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_sideload.545762864
Short name T385
Test name
Test status
Simulation time 5223204435 ps
CPU time 184.63 seconds
Started Feb 08 11:09:32 PM UTC 25
Finished Feb 08 11:12:40 PM UTC 25
Peak memory 342124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545762864 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.545762864 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_smoke.2789349760
Short name T378
Test name
Test status
Simulation time 1438349369 ps
CPU time 19.78 seconds
Started Feb 08 11:09:10 PM UTC 25
Finished Feb 08 11:09:31 PM UTC 25
Peak memory 231660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789349760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.kmac_smoke.2789349760 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_stress_all.2113197710
Short name T397
Test name
Test status
Simulation time 3805860361 ps
CPU time 16.97 seconds
Started Feb 08 11:16:09 PM UTC 25
Finished Feb 08 11:16:27 PM UTC 25
Peak memory 245812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113197710 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.2113197710 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_test_vectors_kmac.3979829543
Short name T387
Test name
Test status
Simulation time 179521923 ps
CPU time 7.79 seconds
Started Feb 08 11:12:42 PM UTC 25
Finished Feb 08 11:12:51 PM UTC 25
Peak memory 227412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3979829543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.kmac_test_vectors_kmac.3979829543 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_test_vectors_kmac_xof.3342225537
Short name T388
Test name
Test status
Simulation time 3360697801 ps
CPU time 8.15 seconds
Started Feb 08 11:12:52 PM UTC 25
Finished Feb 08 11:13:02 PM UTC 25
Peak memory 229544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3342225537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 15.kmac_test_vectors_kmac_xof.3342225537 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_test_vectors_sha3_224.1559472682
Short name T479
Test name
Test status
Simulation time 183259839045 ps
CPU time 2287 seconds
Started Feb 08 11:10:11 PM UTC 25
Finished Feb 08 11:48:44 PM UTC 25
Peak memory 1193816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559472682 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.1559472682 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_test_vectors_sha3_256.2488078846
Short name T504
Test name
Test status
Simulation time 63662252368 ps
CPU time 2829.87 seconds
Started Feb 08 11:10:13 PM UTC 25
Finished Feb 08 11:57:55 PM UTC 25
Peak memory 3106712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488078846 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.2488078846 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_test_vectors_sha3_384.31896302
Short name T497
Test name
Test status
Simulation time 75373084976 ps
CPU time 2529.6 seconds
Started Feb 08 11:11:39 PM UTC 25
Finished Feb 08 11:54:17 PM UTC 25
Peak memory 2433092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31896302 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.31896302 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_test_vectors_sha3_512.3462915284
Short name T475
Test name
Test status
Simulation time 402934432756 ps
CPU time 2039.23 seconds
Started Feb 08 11:12:26 PM UTC 25
Finished Feb 08 11:46:49 PM UTC 25
Peak memory 1714064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462915284 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.3462915284 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_test_vectors_shake_128.1789646359
Short name T750
Test name
Test status
Simulation time 748929768882 ps
CPU time 8816.98 seconds
Started Feb 08 11:12:36 PM UTC 25
Finished Feb 09 01:41:06 AM UTC 25
Peak memory 7976900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789646359 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1789646359 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/15.kmac_test_vectors_shake_256.764170935
Short name T668
Test name
Test status
Simulation time 151963324285 ps
CPU time 6671.66 seconds
Started Feb 08 11:12:41 PM UTC 25
Finished Feb 09 01:05:03 AM UTC 25
Peak memory 6320016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764170935 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.764170935 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_alert_test.366229611
Short name T416
Test name
Test status
Simulation time 106757413 ps
CPU time 1.07 seconds
Started Feb 08 11:24:03 PM UTC 25
Finished Feb 08 11:24:05 PM UTC 25
Peak memory 226236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366229611 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.366229611 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_app.2484441543
Short name T420
Test name
Test status
Simulation time 9513105184 ps
CPU time 198.23 seconds
Started Feb 08 11:21:31 PM UTC 25
Finished Feb 08 11:24:53 PM UTC 25
Peak memory 280548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484441543 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2484441543 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_burst_write.518763430
Short name T457
Test name
Test status
Simulation time 28291418226 ps
CPU time 1352.37 seconds
Started Feb 08 11:17:33 PM UTC 25
Finished Feb 08 11:40:21 PM UTC 25
Peak memory 268200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518763430 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.518763430 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_edn_timeout_error.1265762364
Short name T412
Test name
Test status
Simulation time 556710073 ps
CPU time 14.14 seconds
Started Feb 08 11:23:15 PM UTC 25
Finished Feb 08 11:23:30 PM UTC 25
Peak memory 231336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265762364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1265762364 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_mode_error.1881717230
Short name T413
Test name
Test status
Simulation time 460627527 ps
CPU time 25.12 seconds
Started Feb 08 11:23:31 PM UTC 25
Finished Feb 08 11:23:57 PM UTC 25
Peak memory 235104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881717230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.1881717230 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_entropy_refresh.95254774
Short name T410
Test name
Test status
Simulation time 4320485304 ps
CPU time 39.25 seconds
Started Feb 08 11:22:18 PM UTC 25
Finished Feb 08 11:22:59 PM UTC 25
Peak memory 251824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95254774 -assert nopostproc +UVM_TESTNAME=kmac_bas
e_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_m
asked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.95254774 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_error.1382175619
Short name T421
Test name
Test status
Simulation time 5558949984 ps
CPU time 158.08 seconds
Started Feb 08 11:22:56 PM UTC 25
Finished Feb 08 11:25:37 PM UTC 25
Peak memory 311204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382175619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 16.kmac_error.1382175619 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_key_error.3824122849
Short name T411
Test name
Test status
Simulation time 3051358871 ps
CPU time 11.7 seconds
Started Feb 08 11:23:01 PM UTC 25
Finished Feb 08 11:23:13 PM UTC 25
Peak memory 227296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824122849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.kmac_key_error.3824122849 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_lc_escalation.661707781
Short name T414
Test name
Test status
Simulation time 43851399 ps
CPU time 1.95 seconds
Started Feb 08 11:23:58 PM UTC 25
Finished Feb 08 11:24:01 PM UTC 25
Peak memory 233004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661707781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.661707781 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_long_msg_and_output.3122599397
Short name T527
Test name
Test status
Simulation time 111007012925 ps
CPU time 3090.31 seconds
Started Feb 08 11:16:28 PM UTC 25
Finished Feb 09 12:08:31 AM UTC 25
Peak memory 1857448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122599397 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.3122599397 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_sideload.2642803781
Short name T423
Test name
Test status
Simulation time 21159527925 ps
CPU time 641.82 seconds
Started Feb 08 11:16:41 PM UTC 25
Finished Feb 08 11:27:31 PM UTC 25
Peak memory 640996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642803781 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.2642803781 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_smoke.1529301672
Short name T399
Test name
Test status
Simulation time 1576915603 ps
CPU time 67.15 seconds
Started Feb 08 11:16:23 PM UTC 25
Finished Feb 08 11:17:32 PM UTC 25
Peak memory 235416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529301672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 16.kmac_smoke.1529301672 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_stress_all.2445457253
Short name T478
Test name
Test status
Simulation time 187240120468 ps
CPU time 1429.05 seconds
Started Feb 08 11:24:02 PM UTC 25
Finished Feb 08 11:48:08 PM UTC 25
Peak memory 805200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445457253 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2445457253 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_test_vectors_kmac.3443338599
Short name T406
Test name
Test status
Simulation time 171076140 ps
CPU time 7.86 seconds
Started Feb 08 11:20:56 PM UTC 25
Finished Feb 08 11:21:05 PM UTC 25
Peak memory 235476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3443338599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.kmac_test_vectors_kmac.3443338599 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_test_vectors_kmac_xof.3727838978
Short name T407
Test name
Test status
Simulation time 2253305301 ps
CPU time 22.88 seconds
Started Feb 08 11:21:06 PM UTC 25
Finished Feb 08 11:21:30 PM UTC 25
Peak memory 235680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3727838978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 16.kmac_test_vectors_kmac_xof.3727838978 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_test_vectors_sha3_224.3879695811
Short name T494
Test name
Test status
Simulation time 89397608395 ps
CPU time 2098.77 seconds
Started Feb 08 11:17:45 PM UTC 25
Finished Feb 08 11:53:06 PM UTC 25
Peak memory 1214348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879695811 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3879695811 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_test_vectors_sha3_256.1899180968
Short name T499
Test name
Test status
Simulation time 40378636909 ps
CPU time 2191.93 seconds
Started Feb 08 11:17:58 PM UTC 25
Finished Feb 08 11:54:54 PM UTC 25
Peak memory 1161032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899180968 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1899180968 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_test_vectors_sha3_384.1965671985
Short name T482
Test name
Test status
Simulation time 17363850257 ps
CPU time 1851.81 seconds
Started Feb 08 11:18:50 PM UTC 25
Finished Feb 08 11:50:04 PM UTC 25
Peak memory 931872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965671985 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1965671985 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_test_vectors_sha3_512.3111944934
Short name T453
Test name
Test status
Simulation time 11583196410 ps
CPU time 1136.42 seconds
Started Feb 08 11:19:49 PM UTC 25
Finished Feb 08 11:38:59 PM UTC 25
Peak memory 718688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111944934 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.3111944934 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_test_vectors_shake_128.1125437558
Short name T623
Test name
Test status
Simulation time 238100148436 ps
CPU time 5363.65 seconds
Started Feb 08 11:20:46 PM UTC 25
Finished Feb 09 12:51:07 AM UTC 25
Peak memory 2674508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125437558 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.1125437558 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/16.kmac_test_vectors_shake_256.290514248
Short name T741
Test name
Test status
Simulation time 1915727652487 ps
CPU time 8170.39 seconds
Started Feb 08 11:20:52 PM UTC 25
Finished Feb 09 01:38:29 AM UTC 25
Peak memory 6426452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290514248 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.290514248 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_alert_test.3254375892
Short name T435
Test name
Test status
Simulation time 18863794 ps
CPU time 1.26 seconds
Started Feb 08 11:30:57 PM UTC 25
Finished Feb 08 11:30:59 PM UTC 25
Peak memory 225944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254375892 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3254375892 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_app.1060949516
Short name T439
Test name
Test status
Simulation time 33530682365 ps
CPU time 258.62 seconds
Started Feb 08 11:28:17 PM UTC 25
Finished Feb 08 11:32:40 PM UTC 25
Peak memory 395180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060949516 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.1060949516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_burst_write.3584894059
Short name T436
Test name
Test status
Simulation time 34327393440 ps
CPU time 388.44 seconds
Started Feb 08 11:24:31 PM UTC 25
Finished Feb 08 11:31:05 PM UTC 25
Peak memory 245680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584894059 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.3584894059 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_edn_timeout_error.1355100030
Short name T434
Test name
Test status
Simulation time 344468825 ps
CPU time 38.55 seconds
Started Feb 08 11:30:15 PM UTC 25
Finished Feb 08 11:30:55 PM UTC 25
Peak memory 235304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355100030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1355100030 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_mode_error.2311613618
Short name T432
Test name
Test status
Simulation time 101702333 ps
CPU time 1.73 seconds
Started Feb 08 11:30:19 PM UTC 25
Finished Feb 08 11:30:22 PM UTC 25
Peak memory 227168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311613618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.2311613618 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_entropy_refresh.3326815482
Short name T76
Test name
Test status
Simulation time 19026391454 ps
CPU time 469.2 seconds
Started Feb 08 11:29:50 PM UTC 25
Finished Feb 08 11:37:45 PM UTC 25
Peak memory 546720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326815482 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.3326815482 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_error.1385928487
Short name T440
Test name
Test status
Simulation time 29821918094 ps
CPU time 225.41 seconds
Started Feb 08 11:30:04 PM UTC 25
Finished Feb 08 11:33:53 PM UTC 25
Peak memory 360356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385928487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 17.kmac_error.1385928487 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_key_error.2392486294
Short name T431
Test name
Test status
Simulation time 2016019775 ps
CPU time 9.87 seconds
Started Feb 08 11:30:07 PM UTC 25
Finished Feb 08 11:30:18 PM UTC 25
Peak memory 229212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392486294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.kmac_key_error.2392486294 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_lc_escalation.2845337391
Short name T66
Test name
Test status
Simulation time 550621622 ps
CPU time 32.82 seconds
Started Feb 08 11:30:23 PM UTC 25
Finished Feb 08 11:30:58 PM UTC 25
Peak memory 249840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845337391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2845337391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_long_msg_and_output.3662533061
Short name T602
Test name
Test status
Simulation time 490582196114 ps
CPU time 4729.1 seconds
Started Feb 08 11:24:09 PM UTC 25
Finished Feb 09 12:43:48 AM UTC 25
Peak memory 4593816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662533061 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.3662533061 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_sideload.305325762
Short name T428
Test name
Test status
Simulation time 3633756587 ps
CPU time 323.74 seconds
Started Feb 08 11:24:20 PM UTC 25
Finished Feb 08 11:29:49 PM UTC 25
Peak memory 339936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305325762 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.305325762 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_smoke.1614765073
Short name T419
Test name
Test status
Simulation time 441371145 ps
CPU time 23.01 seconds
Started Feb 08 11:24:06 PM UTC 25
Finished Feb 08 11:24:31 PM UTC 25
Peak memory 231660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614765073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 17.kmac_smoke.1614765073 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_stress_all.1216512409
Short name T520
Test name
Test status
Simulation time 265390813428 ps
CPU time 2154.68 seconds
Started Feb 08 11:30:41 PM UTC 25
Finished Feb 09 12:06:59 AM UTC 25
Peak memory 1684032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216512409 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.1216512409 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_test_vectors_kmac.411931505
Short name T426
Test name
Test status
Simulation time 445812962 ps
CPU time 7.81 seconds
Started Feb 08 11:27:56 PM UTC 25
Finished Feb 08 11:28:05 PM UTC 25
Peak memory 235536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=411931505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 17.kmac_test_vectors_kmac.411931505 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_test_vectors_kmac_xof.3126500505
Short name T427
Test name
Test status
Simulation time 1010909447 ps
CPU time 8.93 seconds
Started Feb 08 11:28:06 PM UTC 25
Finished Feb 08 11:28:16 PM UTC 25
Peak memory 229480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3126500505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 17.kmac_test_vectors_kmac_xof.3126500505 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_test_vectors_sha3_224.3149240629
Short name T536
Test name
Test status
Simulation time 129748944655 ps
CPU time 2958.59 seconds
Started Feb 08 11:24:37 PM UTC 25
Finished Feb 09 12:14:29 AM UTC 25
Peak memory 3200844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149240629 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.3149240629 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_test_vectors_sha3_256.6246525
Short name T526
Test name
Test status
Simulation time 163732456505 ps
CPU time 2586.72 seconds
Started Feb 08 11:24:54 PM UTC 25
Finished Feb 09 12:08:29 AM UTC 25
Peak memory 3090328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6246525 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kma
c_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.6246525 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_test_vectors_sha3_384.1794114508
Short name T505
Test name
Test status
Simulation time 75651084905 ps
CPU time 2035.5 seconds
Started Feb 08 11:25:38 PM UTC 25
Finished Feb 08 11:59:55 PM UTC 25
Peak memory 2383760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794114508 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1794114508 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_test_vectors_sha3_512.1724575741
Short name T483
Test name
Test status
Simulation time 138638840290 ps
CPU time 1390.57 seconds
Started Feb 08 11:26:41 PM UTC 25
Finished Feb 08 11:50:07 PM UTC 25
Peak memory 1705864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724575741 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.1724575741 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_test_vectors_shake_128.710811873
Short name T670
Test name
Test status
Simulation time 241802545033 ps
CPU time 5911.34 seconds
Started Feb 08 11:27:29 PM UTC 25
Finished Feb 09 01:07:04 AM UTC 25
Peak memory 2680712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710811873 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.710811873 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/17.kmac_test_vectors_shake_256.2467025043
Short name T708
Test name
Test status
Simulation time 321535632043 ps
CPU time 6953.61 seconds
Started Feb 08 11:27:32 PM UTC 25
Finished Feb 09 01:24:41 AM UTC 25
Peak memory 6444948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467025043 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.2467025043 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_alert_test.2832862276
Short name T454
Test name
Test status
Simulation time 85941404 ps
CPU time 1.27 seconds
Started Feb 08 11:38:58 PM UTC 25
Finished Feb 08 11:39:01 PM UTC 25
Peak memory 225944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832862276 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2832862276 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_app.4162234814
Short name T447
Test name
Test status
Simulation time 18582540394 ps
CPU time 112.59 seconds
Started Feb 08 11:36:11 PM UTC 25
Finished Feb 08 11:38:06 PM UTC 25
Peak memory 292784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162234814 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.4162234814 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_burst_write.2914325758
Short name T452
Test name
Test status
Simulation time 29405005342 ps
CPU time 398.98 seconds
Started Feb 08 11:32:09 PM UTC 25
Finished Feb 08 11:38:54 PM UTC 25
Peak memory 251800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914325758 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.2914325758 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_edn_timeout_error.3320630553
Short name T450
Test name
Test status
Simulation time 16871781 ps
CPU time 1.29 seconds
Started Feb 08 11:38:48 PM UTC 25
Finished Feb 08 11:38:50 PM UTC 25
Peak memory 224752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320630553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3320630553 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_mode_error.2452013168
Short name T451
Test name
Test status
Simulation time 79205837 ps
CPU time 1.31 seconds
Started Feb 08 11:38:51 PM UTC 25
Finished Feb 08 11:38:54 PM UTC 25
Peak memory 224028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452013168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2452013168 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_entropy_refresh.3301493834
Short name T461
Test name
Test status
Simulation time 11437026968 ps
CPU time 297.3 seconds
Started Feb 08 11:37:47 PM UTC 25
Finished Feb 08 11:42:48 PM UTC 25
Peak memory 329632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301493834 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3301493834 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_error.2025720587
Short name T468
Test name
Test status
Simulation time 9765702209 ps
CPU time 470.9 seconds
Started Feb 08 11:38:07 PM UTC 25
Finished Feb 08 11:46:04 PM UTC 25
Peak memory 403424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025720587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 18.kmac_error.2025720587 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_key_error.3442627504
Short name T449
Test name
Test status
Simulation time 1928352704 ps
CPU time 12.35 seconds
Started Feb 08 11:38:33 PM UTC 25
Finished Feb 08 11:38:47 PM UTC 25
Peak memory 229272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442627504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.kmac_key_error.3442627504 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_lc_escalation.1576567288
Short name T54
Test name
Test status
Simulation time 109902910 ps
CPU time 1.88 seconds
Started Feb 08 11:38:54 PM UTC 25
Finished Feb 08 11:38:57 PM UTC 25
Peak memory 231012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576567288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1576567288 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_long_msg_and_output.895205827
Short name T628
Test name
Test status
Simulation time 352696789642 ps
CPU time 4779.85 seconds
Started Feb 08 11:31:00 PM UTC 25
Finished Feb 09 12:51:33 AM UTC 25
Peak memory 4138980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895205827 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.895205827 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_sideload.2866253316
Short name T444
Test name
Test status
Simulation time 102769734627 ps
CPU time 279.23 seconds
Started Feb 08 11:31:06 PM UTC 25
Finished Feb 08 11:35:49 PM UTC 25
Peak memory 419800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866253316 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2866253316 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_smoke.197925586
Short name T437
Test name
Test status
Simulation time 4911562734 ps
CPU time 68.05 seconds
Started Feb 08 11:30:59 PM UTC 25
Finished Feb 08 11:32:09 PM UTC 25
Peak memory 235420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197925586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 18.kmac_smoke.197925586 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_test_vectors_kmac.2672610308
Short name T445
Test name
Test status
Simulation time 379935477 ps
CPU time 9.22 seconds
Started Feb 08 11:35:50 PM UTC 25
Finished Feb 08 11:36:00 PM UTC 25
Peak memory 229612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2672610308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 18.kmac_test_vectors_kmac.2672610308 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_test_vectors_kmac_xof.4249290655
Short name T446
Test name
Test status
Simulation time 333258754 ps
CPU time 8.17 seconds
Started Feb 08 11:36:01 PM UTC 25
Finished Feb 08 11:36:11 PM UTC 25
Peak memory 229428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=4249290655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 18.kmac_test_vectors_kmac_xof.4249290655 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_test_vectors_sha3_224.698099719
Short name T549
Test name
Test status
Simulation time 67239755654 ps
CPU time 2679.61 seconds
Started Feb 08 11:32:16 PM UTC 25
Finished Feb 09 12:17:26 AM UTC 25
Peak memory 3217296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698099719 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.698099719 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_test_vectors_sha3_256.1758220134
Short name T530
Test name
Test status
Simulation time 135929771955 ps
CPU time 2154.93 seconds
Started Feb 08 11:32:41 PM UTC 25
Finished Feb 09 12:09:00 AM UTC 25
Peak memory 1136480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758220134 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.1758220134 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_test_vectors_sha3_384.2254044821
Short name T519
Test name
Test status
Simulation time 142152352378 ps
CPU time 1915.27 seconds
Started Feb 08 11:33:54 PM UTC 25
Finished Feb 09 12:06:10 AM UTC 25
Peak memory 2447192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254044821 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.2254044821 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_test_vectors_sha3_512.3144673825
Short name T509
Test name
Test status
Simulation time 282524961801 ps
CPU time 1661.3 seconds
Started Feb 08 11:34:19 PM UTC 25
Finished Feb 09 12:02:19 AM UTC 25
Peak memory 1699680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144673825 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.3144673825 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_test_vectors_shake_128.3075929595
Short name T846
Test name
Test status
Simulation time 2029228004624 ps
CPU time 9499.46 seconds
Started Feb 08 11:34:39 PM UTC 25
Finished Feb 09 02:14:38 AM UTC 25
Peak memory 7767988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075929595 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.3075929595 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/18.kmac_test_vectors_shake_256.1618109907
Short name T710
Test name
Test status
Simulation time 630857547721 ps
CPU time 6616.89 seconds
Started Feb 08 11:34:56 PM UTC 25
Finished Feb 09 01:26:24 AM UTC 25
Peak memory 6471520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618109907 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.1618109907 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_alert_test.2559949975
Short name T473
Test name
Test status
Simulation time 50329592 ps
CPU time 1.26 seconds
Started Feb 08 11:46:33 PM UTC 25
Finished Feb 08 11:46:36 PM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559949975 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.2559949975 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_app.2346404
Short name T466
Test name
Test status
Simulation time 955305754 ps
CPU time 22.94 seconds
Started Feb 08 11:44:41 PM UTC 25
Finished Feb 08 11:45:05 PM UTC 25
Peak memory 234736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346404 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2346404 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_burst_write.1586906358
Short name T467
Test name
Test status
Simulation time 3098929754 ps
CPU time 356.37 seconds
Started Feb 08 11:40:00 PM UTC 25
Finished Feb 08 11:46:01 PM UTC 25
Peak memory 239592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586906358 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1586906358 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_edn_timeout_error.2071044211
Short name T469
Test name
Test status
Simulation time 60882872 ps
CPU time 1.77 seconds
Started Feb 08 11:46:05 PM UTC 25
Finished Feb 08 11:46:07 PM UTC 25
Peak memory 227180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071044211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2071044211 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_mode_error.3207885433
Short name T470
Test name
Test status
Simulation time 49681849 ps
CPU time 1.42 seconds
Started Feb 08 11:46:09 PM UTC 25
Finished Feb 08 11:46:11 PM UTC 25
Peak memory 224448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207885433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3207885433 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_entropy_refresh.3634356243
Short name T492
Test name
Test status
Simulation time 90901330032 ps
CPU time 435.75 seconds
Started Feb 08 11:45:05 PM UTC 25
Finished Feb 08 11:52:27 PM UTC 25
Peak memory 514008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634356243 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3634356243 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_error.4080027352
Short name T481
Test name
Test status
Simulation time 6435597687 ps
CPU time 238.97 seconds
Started Feb 08 11:45:06 PM UTC 25
Finished Feb 08 11:49:09 PM UTC 25
Peak memory 382940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080027352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 19.kmac_error.4080027352 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_key_error.1041262068
Short name T471
Test name
Test status
Simulation time 520814323 ps
CPU time 7.68 seconds
Started Feb 08 11:46:02 PM UTC 25
Finished Feb 08 11:46:11 PM UTC 25
Peak memory 227272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041262068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.kmac_key_error.1041262068 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_lc_escalation.1807208847
Short name T474
Test name
Test status
Simulation time 13821397505 ps
CPU time 32 seconds
Started Feb 08 11:46:12 PM UTC 25
Finished Feb 08 11:46:45 PM UTC 25
Peak memory 262168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807208847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1807208847 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_long_msg_and_output.3657174123
Short name T459
Test name
Test status
Simulation time 2379415610 ps
CPU time 102.74 seconds
Started Feb 08 11:39:02 PM UTC 25
Finished Feb 08 11:40:46 PM UTC 25
Peak memory 344008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657174123 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.3657174123 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_sideload.2258344689
Short name T472
Test name
Test status
Simulation time 21340084056 ps
CPU time 422.77 seconds
Started Feb 08 11:39:24 PM UTC 25
Finished Feb 08 11:46:32 PM UTC 25
Peak memory 389160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258344689 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2258344689 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_smoke.741635029
Short name T456
Test name
Test status
Simulation time 1751783413 ps
CPU time 57.39 seconds
Started Feb 08 11:38:59 PM UTC 25
Finished Feb 08 11:39:59 PM UTC 25
Peak memory 233508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741635029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 19.kmac_smoke.741635029 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_stress_all.909558935
Short name T498
Test name
Test status
Simulation time 9192795168 ps
CPU time 512.32 seconds
Started Feb 08 11:46:12 PM UTC 25
Finished Feb 08 11:54:50 PM UTC 25
Peak memory 438176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909558935 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.909558935 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_test_vectors_kmac.1924651968
Short name T463
Test name
Test status
Simulation time 277397538 ps
CPU time 9.41 seconds
Started Feb 08 11:44:19 PM UTC 25
Finished Feb 08 11:44:30 PM UTC 25
Peak memory 235372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1924651968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.kmac_test_vectors_kmac.1924651968 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_test_vectors_kmac_xof.3789682491
Short name T464
Test name
Test status
Simulation time 95711164 ps
CPU time 7.88 seconds
Started Feb 08 11:44:31 PM UTC 25
Finished Feb 08 11:44:40 PM UTC 25
Peak memory 229472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3789682491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 19.kmac_test_vectors_kmac_xof.3789682491 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_test_vectors_sha3_224.3871832411
Short name T598
Test name
Test status
Simulation time 198915918598 ps
CPU time 3727.1 seconds
Started Feb 08 11:40:00 PM UTC 25
Finished Feb 09 12:42:50 AM UTC 25
Peak memory 3192660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871832411 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3871832411 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_test_vectors_sha3_256.3365557453
Short name T546
Test name
Test status
Simulation time 20790279055 ps
CPU time 2170.72 seconds
Started Feb 08 11:40:21 PM UTC 25
Finished Feb 09 12:16:56 AM UTC 25
Peak memory 1136604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365557453 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.3365557453 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_test_vectors_sha3_384.685702856
Short name T554
Test name
Test status
Simulation time 72796760294 ps
CPU time 2365.1 seconds
Started Feb 08 11:40:30 PM UTC 25
Finished Feb 09 12:20:21 AM UTC 25
Peak memory 2375520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685702856 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.685702856 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_test_vectors_sha3_512.3901633150
Short name T521
Test name
Test status
Simulation time 50292333134 ps
CPU time 1560.67 seconds
Started Feb 08 11:40:47 PM UTC 25
Finished Feb 09 12:07:06 AM UTC 25
Peak memory 1742736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901633150 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.3901633150 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_test_vectors_shake_128.3876547494
Short name T837
Test name
Test status
Simulation time 829625498799 ps
CPU time 8955.32 seconds
Started Feb 08 11:41:43 PM UTC 25
Finished Feb 09 02:12:32 AM UTC 25
Peak memory 7901004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876547494 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3876547494 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/19.kmac_test_vectors_shake_256.1883848252
Short name T763
Test name
Test status
Simulation time 336990924466 ps
CPU time 7223.3 seconds
Started Feb 08 11:42:49 PM UTC 25
Finished Feb 09 01:44:28 AM UTC 25
Peak memory 6344656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883848252 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.1883848252 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/19.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_alert_test.1958444077
Short name T111
Test name
Test status
Simulation time 74058707 ps
CPU time 1.2 seconds
Started Feb 08 09:37:55 PM UTC 25
Finished Feb 08 09:37:57 PM UTC 25
Peak memory 225940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958444077 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1958444077 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_app.2423316726
Short name T147
Test name
Test status
Simulation time 29438516913 ps
CPU time 424.8 seconds
Started Feb 08 09:35:07 PM UTC 25
Finished Feb 08 09:42:18 PM UTC 25
Peak memory 507876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423316726 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2423316726 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_app_with_partial_data.1978698124
Short name T42
Test name
Test status
Simulation time 11989418329 ps
CPU time 337.71 seconds
Started Feb 08 09:35:15 PM UTC 25
Finished Feb 08 09:40:58 PM UTC 25
Peak memory 305060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978698124 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1978698124 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_burst_write.3440568000
Short name T149
Test name
Test status
Simulation time 86420186405 ps
CPU time 999.06 seconds
Started Feb 08 09:31:05 PM UTC 25
Finished Feb 08 09:47:55 PM UTC 25
Peak memory 262052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440568000 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3440568000 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_mode_error.2476455119
Short name T77
Test name
Test status
Simulation time 16550010 ps
CPU time 1.34 seconds
Started Feb 08 09:37:30 PM UTC 25
Finished Feb 08 09:37:32 PM UTC 25
Peak memory 224808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476455119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2476455119 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_ready_error.4085256422
Short name T6
Test name
Test status
Simulation time 11489432197 ps
CPU time 41.02 seconds
Started Feb 08 09:37:33 PM UTC 25
Finished Feb 08 09:38:15 PM UTC 25
Peak memory 235616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085256422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
ntropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.4085256422 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_entropy_refresh.3493502798
Short name T70
Test name
Test status
Simulation time 46344424440 ps
CPU time 104 seconds
Started Feb 08 09:35:16 PM UTC 25
Finished Feb 08 09:37:02 PM UTC 25
Peak memory 284592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493502798 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3493502798 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_error.574303695
Short name T23
Test name
Test status
Simulation time 22525190542 ps
CPU time 52.53 seconds
Started Feb 08 09:37:04 PM UTC 25
Finished Feb 08 09:37:58 PM UTC 25
Peak memory 278428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574303695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_er
ror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 2.kmac_error.574303695 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_key_error.485122221
Short name T15
Test name
Test status
Simulation time 3520758231 ps
CPU time 14.8 seconds
Started Feb 08 09:37:10 PM UTC 25
Finished Feb 08 09:37:26 PM UTC 25
Peak memory 227332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485122221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ke
y_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.kmac_key_error.485122221 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_lc_escalation.3276928468
Short name T31
Test name
Test status
Simulation time 117145673 ps
CPU time 1.99 seconds
Started Feb 08 09:37:44 PM UTC 25
Finished Feb 08 09:37:47 PM UTC 25
Peak memory 231016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276928468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3276928468 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_long_msg_and_output.2144977645
Short name T315
Test name
Test status
Simulation time 958377068216 ps
CPU time 4137.53 seconds
Started Feb 08 09:30:58 PM UTC 25
Finished Feb 08 10:40:40 PM UTC 25
Peak memory 3635292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144977645 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.2144977645 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_mubi.2684907787
Short name T58
Test name
Test status
Simulation time 14591435395 ps
CPU time 322.62 seconds
Started Feb 08 09:35:46 PM UTC 25
Finished Feb 08 09:41:14 PM UTC 25
Peak memory 401768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684907787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_m
ubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 2.kmac_mubi.2684907787 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_sec_cm.2225620251
Short name T35
Test name
Test status
Simulation time 8655546006 ps
CPU time 104.31 seconds
Started Feb 08 09:37:54 PM UTC 25
Finished Feb 08 09:39:41 PM UTC 25
Peak memory 281784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225620251 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2225620251 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_sideload.644968421
Short name T22
Test name
Test status
Simulation time 7769657818 ps
CPU time 279.78 seconds
Started Feb 08 09:31:02 PM UTC 25
Finished Feb 08 09:35:46 PM UTC 25
Peak memory 452576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644968421 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.644968421 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_smoke.862405669
Short name T46
Test name
Test status
Simulation time 2799432881 ps
CPU time 20.84 seconds
Started Feb 08 09:30:43 PM UTC 25
Finished Feb 08 09:31:05 PM UTC 25
Peak memory 235400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862405669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 2.kmac_smoke.862405669 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all.268671212
Short name T235
Test name
Test status
Simulation time 44058885480 ps
CPU time 1811 seconds
Started Feb 08 09:37:44 PM UTC 25
Finished Feb 08 10:08:15 PM UTC 25
Peak memory 825708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268671212 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.268671212 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_stress_all_with_rand_reset.4289524127
Short name T50
Test name
Test status
Simulation time 572977183896 ps
CPU time 6335.47 seconds
Started Feb 08 09:37:48 PM UTC 25
Finished Feb 08 11:24:36 PM UTC 25
Peak memory 1258048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289524127 -asse
rt nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.4289524127 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac.1184025660
Short name T196
Test name
Test status
Simulation time 977586160 ps
CPU time 10.03 seconds
Started Feb 08 09:34:45 PM UTC 25
Finished Feb 08 09:34:57 PM UTC 25
Peak memory 235388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1184025660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.kmac_test_vectors_kmac.1184025660 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_kmac_xof.742299355
Short name T197
Test name
Test status
Simulation time 118928687 ps
CPU time 8.16 seconds
Started Feb 08 09:34:57 PM UTC 25
Finished Feb 08 09:35:07 PM UTC 25
Peak memory 229460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=742299355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.kmac_test_vectors_kmac_xof.742299355 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_224.2748800461
Short name T253
Test name
Test status
Simulation time 247305968662 ps
CPU time 2732.59 seconds
Started Feb 08 09:31:06 PM UTC 25
Finished Feb 08 10:17:08 PM UTC 25
Peak memory 3186572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748800461 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2748800461 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_256.1159364457
Short name T245
Test name
Test status
Simulation time 89865177594 ps
CPU time 2465.6 seconds
Started Feb 08 09:31:18 PM UTC 25
Finished Feb 08 10:12:53 PM UTC 25
Peak memory 1189784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159364457 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1159364457 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_384.1101466393
Short name T254
Test name
Test status
Simulation time 142788549502 ps
CPU time 2723.72 seconds
Started Feb 08 09:31:29 PM UTC 25
Finished Feb 08 10:17:24 PM UTC 25
Peak memory 2410448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101466393 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1101466393 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_sha3_512.1013116571
Short name T220
Test name
Test status
Simulation time 102329438909 ps
CPU time 1906.5 seconds
Started Feb 08 09:31:54 PM UTC 25
Finished Feb 08 10:04:03 PM UTC 25
Peak memory 1767452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013116571 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1013116571 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_128.1138779056
Short name T555
Test name
Test status
Simulation time 517118488432 ps
CPU time 9954.57 seconds
Started Feb 08 09:32:54 PM UTC 25
Finished Feb 09 12:20:36 AM UTC 25
Peak memory 7745536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138779056 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1138779056 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/2.kmac_test_vectors_shake_256.298141990
Short name T517
Test name
Test status
Simulation time 919652156196 ps
CPU time 8996.81 seconds
Started Feb 08 09:33:45 PM UTC 25
Finished Feb 09 12:05:21 AM UTC 25
Peak memory 6524740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298141990 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.298141990 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_alert_test.3650858485
Short name T491
Test name
Test status
Simulation time 26015954 ps
CPU time 1.22 seconds
Started Feb 08 11:52:09 PM UTC 25
Finished Feb 08 11:52:11 PM UTC 25
Peak memory 225884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650858485 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3650858485 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_app.709978185
Short name T501
Test name
Test status
Simulation time 25770639050 ps
CPU time 395.08 seconds
Started Feb 08 11:50:20 PM UTC 25
Finished Feb 08 11:57:00 PM UTC 25
Peak memory 477104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709978185 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.709978185 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_burst_write.2039795411
Short name T513
Test name
Test status
Simulation time 30318203132 ps
CPU time 956.4 seconds
Started Feb 08 11:47:43 PM UTC 25
Finished Feb 09 12:03:51 AM UTC 25
Peak memory 247720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039795411 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2039795411 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_entropy_refresh.2047657906
Short name T493
Test name
Test status
Simulation time 17250677120 ps
CPU time 143.25 seconds
Started Feb 08 11:50:29 PM UTC 25
Finished Feb 08 11:52:55 PM UTC 25
Peak memory 303048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047657906 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.2047657906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_error.3119301424
Short name T496
Test name
Test status
Simulation time 3701660451 ps
CPU time 165.54 seconds
Started Feb 08 11:51:14 PM UTC 25
Finished Feb 08 11:54:03 PM UTC 25
Peak memory 344028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119301424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 20.kmac_error.3119301424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_key_error.2422183123
Short name T489
Test name
Test status
Simulation time 1813215571 ps
CPU time 7.05 seconds
Started Feb 08 11:51:52 PM UTC 25
Finished Feb 08 11:52:00 PM UTC 25
Peak memory 227168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422183123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 20.kmac_key_error.2422183123 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_lc_escalation.1819116940
Short name T490
Test name
Test status
Simulation time 880845833 ps
CPU time 5.65 seconds
Started Feb 08 11:52:01 PM UTC 25
Finished Feb 08 11:52:07 PM UTC 25
Peak memory 245212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819116940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1819116940 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_long_msg_and_output.3830523848
Short name T543
Test name
Test status
Simulation time 213219612417 ps
CPU time 1758.67 seconds
Started Feb 08 11:46:46 PM UTC 25
Finished Feb 09 12:16:24 AM UTC 25
Peak memory 1089436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830523848 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_and_output.3830523848 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_sideload.1644969489
Short name T487
Test name
Test status
Simulation time 41563954758 ps
CPU time 259.03 seconds
Started Feb 08 11:46:50 PM UTC 25
Finished Feb 08 11:51:13 PM UTC 25
Peak memory 438180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644969489 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1644969489 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_smoke.2540745068
Short name T477
Test name
Test status
Simulation time 3276676792 ps
CPU time 81.99 seconds
Started Feb 08 11:46:37 PM UTC 25
Finished Feb 08 11:48:01 PM UTC 25
Peak memory 235608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540745068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 20.kmac_smoke.2540745068 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_stress_all.1092199859
Short name T552
Test name
Test status
Simulation time 37315397408 ps
CPU time 1544.93 seconds
Started Feb 08 11:52:09 PM UTC 25
Finished Feb 09 12:18:12 AM UTC 25
Peak memory 725344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092199859 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.1092199859 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_test_vectors_kmac.2749475762
Short name T485
Test name
Test status
Simulation time 663343253 ps
CPU time 10.06 seconds
Started Feb 08 11:50:08 PM UTC 25
Finished Feb 08 11:50:19 PM UTC 25
Peak memory 235532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2749475762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 20.kmac_test_vectors_kmac.2749475762 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_test_vectors_kmac_xof.163214014
Short name T486
Test name
Test status
Simulation time 952485265 ps
CPU time 8.32 seconds
Started Feb 08 11:50:19 PM UTC 25
Finished Feb 08 11:50:28 PM UTC 25
Peak memory 229424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=163214014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 20.kmac_test_vectors_kmac_xof.163214014 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_test_vectors_sha3_224.3211164324
Short name T579
Test name
Test status
Simulation time 73132224345 ps
CPU time 2670 seconds
Started Feb 08 11:48:02 PM UTC 25
Finished Feb 09 12:33:00 AM UTC 25
Peak memory 3321748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211164324 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3211164324 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_test_vectors_sha3_256.2186398219
Short name T578
Test name
Test status
Simulation time 75641481004 ps
CPU time 2606.3 seconds
Started Feb 08 11:48:09 PM UTC 25
Finished Feb 09 12:32:04 AM UTC 25
Peak memory 3086164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186398219 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.2186398219 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_test_vectors_sha3_384.1761038151
Short name T548
Test name
Test status
Simulation time 30226712208 ps
CPU time 1693.61 seconds
Started Feb 08 11:48:44 PM UTC 25
Finished Feb 09 12:17:17 AM UTC 25
Peak memory 948056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761038151 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.1761038151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_test_vectors_sha3_512.3668126936
Short name T537
Test name
Test status
Simulation time 138861411668 ps
CPU time 1586.07 seconds
Started Feb 08 11:49:00 PM UTC 25
Finished Feb 09 12:15:45 AM UTC 25
Peak memory 1734496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668126936 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3668126936 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_test_vectors_shake_128.3502578835
Short name T715
Test name
Test status
Simulation time 667595052743 ps
CPU time 5919.74 seconds
Started Feb 08 11:49:10 PM UTC 25
Finished Feb 09 01:28:54 AM UTC 25
Peak memory 2699144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502578835 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.3502578835 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/20.kmac_test_vectors_shake_256.1949966073
Short name T748
Test name
Test status
Simulation time 163260779182 ps
CPU time 6587.41 seconds
Started Feb 08 11:50:05 PM UTC 25
Finished Feb 09 01:41:01 AM UTC 25
Peak memory 6432588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949966073 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.1949966073 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_alert_test.1472925479
Short name T510
Test name
Test status
Simulation time 40885628 ps
CPU time 1.27 seconds
Started Feb 09 12:02:20 AM UTC 25
Finished Feb 09 12:02:22 AM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472925479 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1472925479 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_app.2224061511
Short name T506
Test name
Test status
Simulation time 7140374078 ps
CPU time 233.41 seconds
Started Feb 08 11:57:23 PM UTC 25
Finished Feb 09 12:01:20 AM UTC 25
Peak memory 358288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224061511 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2224061511 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_burst_write.990061399
Short name T105
Test name
Test status
Simulation time 119910970484 ps
CPU time 1835.51 seconds
Started Feb 08 11:53:07 PM UTC 25
Finished Feb 09 12:24:04 AM UTC 25
Peak memory 274404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990061399 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.990061399 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_entropy_refresh.2662634698
Short name T515
Test name
Test status
Simulation time 19661155453 ps
CPU time 410.01 seconds
Started Feb 08 11:57:56 PM UTC 25
Finished Feb 09 12:04:52 AM UTC 25
Peak memory 333788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662634698 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.2662634698 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_error.1952836690
Short name T514
Test name
Test status
Simulation time 41647822462 ps
CPU time 277.42 seconds
Started Feb 08 11:59:57 PM UTC 25
Finished Feb 09 12:04:38 AM UTC 25
Peak memory 348072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952836690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 21.kmac_error.1952836690 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_key_error.2667749498
Short name T507
Test name
Test status
Simulation time 1185466289 ps
CPU time 15.92 seconds
Started Feb 09 12:01:21 AM UTC 25
Finished Feb 09 12:01:38 AM UTC 25
Peak memory 229216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667749498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 21.kmac_key_error.2667749498 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_lc_escalation.293967905
Short name T508
Test name
Test status
Simulation time 50200716 ps
CPU time 2.34 seconds
Started Feb 09 12:01:39 AM UTC 25
Finished Feb 09 12:01:43 AM UTC 25
Peak memory 233704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293967905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.293967905 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_long_msg_and_output.3353858566
Short name T592
Test name
Test status
Simulation time 205274527037 ps
CPU time 2804.75 seconds
Started Feb 08 11:52:28 PM UTC 25
Finished Feb 09 12:39:42 AM UTC 25
Peak memory 3221464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353858566 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_and_output.3353858566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_sideload.1592308308
Short name T500
Test name
Test status
Simulation time 6037413430 ps
CPU time 221.72 seconds
Started Feb 08 11:52:56 PM UTC 25
Finished Feb 08 11:56:41 PM UTC 25
Peak memory 317400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592308308 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.1592308308 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_smoke.1672378435
Short name T495
Test name
Test status
Simulation time 1660846028 ps
CPU time 84.99 seconds
Started Feb 08 11:52:12 PM UTC 25
Finished Feb 08 11:53:39 PM UTC 25
Peak memory 235392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672378435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 21.kmac_smoke.1672378435 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_stress_all.1422622513
Short name T590
Test name
Test status
Simulation time 211195739551 ps
CPU time 2244.64 seconds
Started Feb 09 12:01:43 AM UTC 25
Finished Feb 09 12:39:32 AM UTC 25
Peak memory 1823008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422622513 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.1422622513 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_test_vectors_kmac.98637450
Short name T502
Test name
Test status
Simulation time 977266369 ps
CPU time 9.29 seconds
Started Feb 08 11:57:02 PM UTC 25
Finished Feb 08 11:57:12 PM UTC 25
Peak memory 235428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=98637450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.kmac_test_vectors_kmac.98637450 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_test_vectors_kmac_xof.3992606741
Short name T503
Test name
Test status
Simulation time 443729371 ps
CPU time 7.82 seconds
Started Feb 08 11:57:13 PM UTC 25
Finished Feb 08 11:57:22 PM UTC 25
Peak memory 229528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3992606741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 21.kmac_test_vectors_kmac_xof.3992606741 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_test_vectors_sha3_224.3007794235
Short name T565
Test name
Test status
Simulation time 46430692108 ps
CPU time 1926.3 seconds
Started Feb 08 11:53:40 PM UTC 25
Finished Feb 09 12:26:07 AM UTC 25
Peak memory 1214348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007794235 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.3007794235 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_test_vectors_sha3_256.4149751838
Short name T109
Test name
Test status
Simulation time 19805785702 ps
CPU time 1832.4 seconds
Started Feb 08 11:54:04 PM UTC 25
Finished Feb 09 12:24:56 AM UTC 25
Peak memory 1138496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149751838 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.4149751838 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_test_vectors_sha3_384.3698891484
Short name T104
Test name
Test status
Simulation time 17165422397 ps
CPU time 1745.67 seconds
Started Feb 08 11:54:18 PM UTC 25
Finished Feb 09 12:23:43 AM UTC 25
Peak memory 927584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698891484 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3698891484 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_test_vectors_sha3_512.1935628347
Short name T108
Test name
Test status
Simulation time 176413916656 ps
CPU time 1780.57 seconds
Started Feb 08 11:54:51 PM UTC 25
Finished Feb 09 12:24:52 AM UTC 25
Peak memory 1726496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935628347 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.1935628347 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_test_vectors_shake_128.151297996
Short name T885
Test name
Test status
Simulation time 937300259779 ps
CPU time 9168.37 seconds
Started Feb 08 11:54:55 PM UTC 25
Finished Feb 09 02:29:18 AM UTC 25
Peak memory 7759860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151297996 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.151297996 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/21.kmac_test_vectors_shake_256.2581814765
Short name T816
Test name
Test status
Simulation time 421128882959 ps
CPU time 7391.6 seconds
Started Feb 08 11:56:43 PM UTC 25
Finished Feb 09 02:01:11 AM UTC 25
Peak memory 6418444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581814765 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.2581814765 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_alert_test.1544322687
Short name T529
Test name
Test status
Simulation time 41749311 ps
CPU time 1.29 seconds
Started Feb 09 12:08:34 AM UTC 25
Finished Feb 09 12:08:36 AM UTC 25
Peak memory 227152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544322687 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1544322687 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_app.777046252
Short name T534
Test name
Test status
Simulation time 20550600427 ps
CPU time 257.49 seconds
Started Feb 09 12:07:09 AM UTC 25
Finished Feb 09 12:11:30 AM UTC 25
Peak memory 385132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777046252 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.777046252 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_burst_write.1956925920
Short name T540
Test name
Test status
Simulation time 6361867969 ps
CPU time 732.47 seconds
Started Feb 09 12:03:52 AM UTC 25
Finished Feb 09 12:16:14 AM UTC 25
Peak memory 245676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956925920 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1956925920 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_entropy_refresh.1061162021
Short name T524
Test name
Test status
Simulation time 5938902479 ps
CPU time 51.69 seconds
Started Feb 09 12:07:15 AM UTC 25
Finished Feb 09 12:08:08 AM UTC 25
Peak memory 257936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061162021 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1061162021 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_key_error.3475194507
Short name T531
Test name
Test status
Simulation time 15875744728 ps
CPU time 32.78 seconds
Started Feb 09 12:08:28 AM UTC 25
Finished Feb 09 12:09:03 AM UTC 25
Peak memory 227280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475194507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 22.kmac_key_error.3475194507 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_lc_escalation.2536264031
Short name T528
Test name
Test status
Simulation time 170168997 ps
CPU time 1.96 seconds
Started Feb 09 12:08:30 AM UTC 25
Finished Feb 09 12:08:33 AM UTC 25
Peak memory 231012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536264031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2536264031 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_long_msg_and_output.3707343164
Short name T706
Test name
Test status
Simulation time 88096888838 ps
CPU time 4798.88 seconds
Started Feb 09 12:03:11 AM UTC 25
Finished Feb 09 01:24:04 AM UTC 25
Peak memory 4118440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707343164 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_and_output.3707343164 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_sideload.2425486966
Short name T525
Test name
Test status
Simulation time 2862214880 ps
CPU time 293.49 seconds
Started Feb 09 12:03:29 AM UTC 25
Finished Feb 09 12:08:27 AM UTC 25
Peak memory 309344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425486966 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2425486966 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_smoke.489716842
Short name T512
Test name
Test status
Simulation time 28326869092 ps
CPU time 63.49 seconds
Started Feb 09 12:02:23 AM UTC 25
Finished Feb 09 12:03:28 AM UTC 25
Peak memory 233708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489716842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 22.kmac_smoke.489716842 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_stress_all.2566470484
Short name T560
Test name
Test status
Simulation time 47137084592 ps
CPU time 800.41 seconds
Started Feb 09 12:08:32 AM UTC 25
Finished Feb 09 12:22:02 AM UTC 25
Peak memory 629064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566470484 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.2566470484 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_test_vectors_kmac.2377409700
Short name T522
Test name
Test status
Simulation time 175780881 ps
CPU time 7.18 seconds
Started Feb 09 12:07:00 AM UTC 25
Finished Feb 09 12:07:08 AM UTC 25
Peak memory 235424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2377409700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.kmac_test_vectors_kmac.2377409700 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_test_vectors_kmac_xof.3546510399
Short name T523
Test name
Test status
Simulation time 551061276 ps
CPU time 7.41 seconds
Started Feb 09 12:07:06 AM UTC 25
Finished Feb 09 12:07:14 AM UTC 25
Peak memory 235364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3546510399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 22.kmac_test_vectors_kmac_xof.3546510399 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_test_vectors_sha3_224.2445404322
Short name T585
Test name
Test status
Simulation time 79452289726 ps
CPU time 1976.52 seconds
Started Feb 09 12:04:40 AM UTC 25
Finished Feb 09 12:37:57 AM UTC 25
Peak memory 1189784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445404322 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.2445404322 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_test_vectors_sha3_256.1249788855
Short name T637
Test name
Test status
Simulation time 226477453722 ps
CPU time 3005.2 seconds
Started Feb 09 12:04:53 AM UTC 25
Finished Feb 09 12:55:30 AM UTC 25
Peak memory 3112796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249788855 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.1249788855 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_test_vectors_sha3_384.143680181
Short name T577
Test name
Test status
Simulation time 67119914687 ps
CPU time 1522.13 seconds
Started Feb 09 12:05:01 AM UTC 25
Finished Feb 09 12:30:40 AM UTC 25
Peak memory 931736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143680181 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.143680181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_test_vectors_sha3_512.924305079
Short name T569
Test name
Test status
Simulation time 10718211302 ps
CPU time 1279.09 seconds
Started Feb 09 12:05:22 AM UTC 25
Finished Feb 09 12:26:56 AM UTC 25
Peak memory 722820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924305079 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.924305079 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_test_vectors_shake_128.1595560650
Short name T896
Test name
Test status
Simulation time 237861107905 ps
CPU time 8717.66 seconds
Started Feb 09 12:05:48 AM UTC 25
Finished Feb 09 02:32:37 AM UTC 25
Peak memory 7725124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595560650 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1595560650 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/22.kmac_test_vectors_shake_256.1988256535
Short name T721
Test name
Test status
Simulation time 52656369056 ps
CPU time 5080.29 seconds
Started Feb 09 12:06:11 AM UTC 25
Finished Feb 09 01:31:47 AM UTC 25
Peak memory 2238348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988256535 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1988256535 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_alert_test.2519498578
Short name T547
Test name
Test status
Simulation time 22868883 ps
CPU time 1.26 seconds
Started Feb 09 12:16:54 AM UTC 25
Finished Feb 09 12:16:56 AM UTC 25
Peak memory 224024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519498578 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2519498578 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_app.3681990735
Short name T553
Test name
Test status
Simulation time 2154381482 ps
CPU time 163.59 seconds
Started Feb 09 12:16:14 AM UTC 25
Finished Feb 09 12:19:01 AM UTC 25
Peak memory 272420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681990735 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.3681990735 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_burst_write.3649213420
Short name T576
Test name
Test status
Simulation time 9571461709 ps
CPU time 1185.09 seconds
Started Feb 09 12:10:01 AM UTC 25
Finished Feb 09 12:30:01 AM UTC 25
Peak memory 249780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649213420 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.3649213420 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_entropy_refresh.2649610221
Short name T102
Test name
Test status
Simulation time 6293375381 ps
CPU time 399.34 seconds
Started Feb 09 12:16:24 AM UTC 25
Finished Feb 09 12:23:09 AM UTC 25
Peak memory 327776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649610221 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.2649610221 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_error.2625197713
Short name T556
Test name
Test status
Simulation time 10059537377 ps
CPU time 255.46 seconds
Started Feb 09 12:16:26 AM UTC 25
Finished Feb 09 12:20:45 AM UTC 25
Peak memory 432092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625197713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 23.kmac_error.2625197713 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_key_error.3832222468
Short name T545
Test name
Test status
Simulation time 2808646094 ps
CPU time 18 seconds
Started Feb 09 12:16:33 AM UTC 25
Finished Feb 09 12:16:52 AM UTC 25
Peak memory 227200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832222468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 23.kmac_key_error.3832222468 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_lc_escalation.1321980783
Short name T51
Test name
Test status
Simulation time 48496722 ps
CPU time 1.84 seconds
Started Feb 09 12:16:50 AM UTC 25
Finished Feb 09 12:16:53 AM UTC 25
Peak memory 230960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321980783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1321980783 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_long_msg_and_output.1081815669
Short name T648
Test name
Test status
Simulation time 105466622388 ps
CPU time 2887.49 seconds
Started Feb 09 12:09:01 AM UTC 25
Finished Feb 09 12:57:40 AM UTC 25
Peak memory 1638476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081815669 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_and_output.1081815669 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_sideload.3534282557
Short name T539
Test name
Test status
Simulation time 7575066578 ps
CPU time 412.75 seconds
Started Feb 09 12:09:04 AM UTC 25
Finished Feb 09 12:16:03 AM UTC 25
Peak memory 346064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534282557 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3534282557 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_smoke.1784148011
Short name T532
Test name
Test status
Simulation time 3372532499 ps
CPU time 81.67 seconds
Started Feb 09 12:08:37 AM UTC 25
Finished Feb 09 12:10:01 AM UTC 25
Peak memory 235612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784148011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 23.kmac_smoke.1784148011 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_stress_all.3177206522
Short name T568
Test name
Test status
Simulation time 12619386634 ps
CPU time 574.51 seconds
Started Feb 09 12:16:53 AM UTC 25
Finished Feb 09 12:26:35 AM UTC 25
Peak memory 741740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177206522 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3177206522 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_test_vectors_kmac.1315416235
Short name T541
Test name
Test status
Simulation time 296945960 ps
CPU time 9.38 seconds
Started Feb 09 12:16:03 AM UTC 25
Finished Feb 09 12:16:14 AM UTC 25
Peak memory 229476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1315416235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.kmac_test_vectors_kmac.1315416235 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_test_vectors_kmac_xof.11700232
Short name T542
Test name
Test status
Simulation time 411170045 ps
CPU time 7.64 seconds
Started Feb 09 12:16:14 AM UTC 25
Finished Feb 09 12:16:23 AM UTC 25
Peak memory 227376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=11700232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 23.kmac_test_vectors_kmac_xof.11700232 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_test_vectors_sha3_224.1054173845
Short name T649
Test name
Test status
Simulation time 73085113023 ps
CPU time 2788.94 seconds
Started Feb 09 12:10:45 AM UTC 25
Finished Feb 09 12:57:45 AM UTC 25
Peak memory 3168152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054173845 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.1054173845 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_test_vectors_sha3_256.3234708939
Short name T600
Test name
Test status
Simulation time 20144064419 ps
CPU time 1900.98 seconds
Started Feb 09 12:11:31 AM UTC 25
Finished Feb 09 12:43:33 AM UTC 25
Peak memory 1154904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234708939 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.3234708939 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_test_vectors_sha3_384.3412329834
Short name T596
Test name
Test status
Simulation time 68795531727 ps
CPU time 1709.55 seconds
Started Feb 09 12:12:52 AM UTC 25
Finished Feb 09 12:41:41 AM UTC 25
Peak memory 943960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412329834 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.3412329834 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_test_vectors_sha3_512.4044605403
Short name T587
Test name
Test status
Simulation time 45535927064 ps
CPU time 1426.29 seconds
Started Feb 09 12:14:30 AM UTC 25
Finished Feb 09 12:38:32 AM UTC 25
Peak memory 1769556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044605403 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.4044605403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_test_vectors_shake_128.3776969681
Short name T805
Test name
Test status
Simulation time 62697039033 ps
CPU time 6025.41 seconds
Started Feb 09 12:15:46 AM UTC 25
Finished Feb 09 01:57:18 AM UTC 25
Peak memory 2738128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776969681 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3776969681 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/23.kmac_test_vectors_shake_256.3815860717
Short name T726
Test name
Test status
Simulation time 110643706700 ps
CPU time 4608.38 seconds
Started Feb 09 12:15:46 AM UTC 25
Finished Feb 09 01:33:24 AM UTC 25
Peak memory 2246444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815860717 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3815860717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_alert_test.4191869584
Short name T103
Test name
Test status
Simulation time 14483452 ps
CPU time 1.24 seconds
Started Feb 09 12:23:10 AM UTC 25
Finished Feb 09 12:23:13 AM UTC 25
Peak memory 226232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191869584 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.4191869584 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_burst_write.3744199726
Short name T106
Test name
Test status
Simulation time 6134546613 ps
CPU time 417.55 seconds
Started Feb 09 12:17:27 AM UTC 25
Finished Feb 09 12:24:31 AM UTC 25
Peak memory 239540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744199726 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3744199726 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_entropy_refresh.1150303735
Short name T564
Test name
Test status
Simulation time 11285140440 ps
CPU time 296.04 seconds
Started Feb 09 12:21:06 AM UTC 25
Finished Feb 09 12:26:07 AM UTC 25
Peak memory 419804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150303735 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1150303735 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_error.2463567275
Short name T563
Test name
Test status
Simulation time 11837463203 ps
CPU time 211.12 seconds
Started Feb 09 12:22:03 AM UTC 25
Finished Feb 09 12:25:37 AM UTC 25
Peak memory 321632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463567275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.kmac_error.2463567275 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_lc_escalation.1168366052
Short name T101
Test name
Test status
Simulation time 276517015 ps
CPU time 9.41 seconds
Started Feb 09 12:22:17 AM UTC 25
Finished Feb 09 12:22:28 AM UTC 25
Peak memory 245844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168366052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1168366052 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_long_msg_and_output.3584556804
Short name T634
Test name
Test status
Simulation time 102156938044 ps
CPU time 2180.84 seconds
Started Feb 09 12:16:57 AM UTC 25
Finished Feb 09 12:53:43 AM UTC 25
Peak memory 2117584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584556804 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_and_output.3584556804 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_sideload.1261902768
Short name T107
Test name
Test status
Simulation time 12779249575 ps
CPU time 435.93 seconds
Started Feb 09 12:17:18 AM UTC 25
Finished Feb 09 12:24:40 AM UTC 25
Peak memory 358364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261902768 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1261902768 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_smoke.4289684468
Short name T551
Test name
Test status
Simulation time 3131138491 ps
CPU time 51.98 seconds
Started Feb 09 12:16:57 AM UTC 25
Finished Feb 09 12:17:51 AM UTC 25
Peak memory 235596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289684468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.kmac_smoke.4289684468 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_stress_all.1313720117
Short name T629
Test name
Test status
Simulation time 91873395087 ps
CPU time 1728.33 seconds
Started Feb 09 12:22:28 AM UTC 25
Finished Feb 09 12:51:35 AM UTC 25
Peak memory 956368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313720117 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1313720117 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_test_vectors_kmac.1862027729
Short name T557
Test name
Test status
Simulation time 805005227 ps
CPU time 7.79 seconds
Started Feb 09 12:20:46 AM UTC 25
Finished Feb 09 12:20:55 AM UTC 25
Peak memory 235364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1862027729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 24.kmac_test_vectors_kmac.1862027729 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_test_vectors_kmac_xof.3608964133
Short name T559
Test name
Test status
Simulation time 292237194 ps
CPU time 8.65 seconds
Started Feb 09 12:20:56 AM UTC 25
Finished Feb 09 12:21:06 AM UTC 25
Peak memory 227560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3608964133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 24.kmac_test_vectors_kmac_xof.3608964133 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_test_vectors_sha3_224.583662326
Short name T633
Test name
Test status
Simulation time 47527079028 ps
CPU time 2113.53 seconds
Started Feb 09 12:17:28 AM UTC 25
Finished Feb 09 12:53:05 AM UTC 25
Peak memory 1183584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583662326 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.583662326 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_test_vectors_sha3_256.1249489112
Short name T671
Test name
Test status
Simulation time 96772284384 ps
CPU time 2925.75 seconds
Started Feb 09 12:17:52 AM UTC 25
Finished Feb 09 01:07:08 AM UTC 25
Peak memory 3106824 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249489112 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.1249489112 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_test_vectors_sha3_384.798067875
Short name T626
Test name
Test status
Simulation time 97146842000 ps
CPU time 1969.18 seconds
Started Feb 09 12:18:13 AM UTC 25
Finished Feb 09 12:51:25 AM UTC 25
Peak memory 966544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798067875 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.798067875 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_test_vectors_sha3_512.2594019210
Short name T618
Test name
Test status
Simulation time 34158889673 ps
CPU time 1792.39 seconds
Started Feb 09 12:19:02 AM UTC 25
Finished Feb 09 12:49:16 AM UTC 25
Peak memory 1718240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594019210 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2594019210 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_test_vectors_shake_128.4215036498
Short name T777
Test name
Test status
Simulation time 239139638533 ps
CPU time 5185.25 seconds
Started Feb 09 12:20:22 AM UTC 25
Finished Feb 09 01:47:40 AM UTC 25
Peak memory 2699156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215036498 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.4215036498 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/24.kmac_test_vectors_shake_256.2612551352
Short name T875
Test name
Test status
Simulation time 803086252789 ps
CPU time 7369.19 seconds
Started Feb 09 12:20:37 AM UTC 25
Finished Feb 09 02:24:43 AM UTC 25
Peak memory 6373388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612551352 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.2612551352 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_alert_test.1035576551
Short name T572
Test name
Test status
Simulation time 103553311 ps
CPU time 1.31 seconds
Started Feb 09 12:27:44 AM UTC 25
Finished Feb 09 12:27:46 AM UTC 25
Peak memory 225704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035576551 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1035576551 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_app.3691668331
Short name T571
Test name
Test status
Simulation time 5573123860 ps
CPU time 82.77 seconds
Started Feb 09 12:26:18 AM UTC 25
Finished Feb 09 12:27:42 AM UTC 25
Peak memory 294872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691668331 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3691668331 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_burst_write.2003033405
Short name T601
Test name
Test status
Simulation time 18758354291 ps
CPU time 1132.48 seconds
Started Feb 09 12:24:32 AM UTC 25
Finished Feb 09 12:43:38 AM UTC 25
Peak memory 260016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003033405 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2003033405 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_entropy_refresh.1859706109
Short name T581
Test name
Test status
Simulation time 24949811640 ps
CPU time 447.22 seconds
Started Feb 09 12:26:18 AM UTC 25
Finished Feb 09 12:33:51 AM UTC 25
Peak memory 518112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859706109 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.1859706109 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_error.729700190
Short name T582
Test name
Test status
Simulation time 11723795907 ps
CPU time 536.4 seconds
Started Feb 09 12:26:36 AM UTC 25
Finished Feb 09 12:35:39 AM UTC 25
Peak memory 546772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729700190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_er
ror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 25.kmac_error.729700190 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_key_error.712236150
Short name T570
Test name
Test status
Simulation time 2129067289 ps
CPU time 14.06 seconds
Started Feb 09 12:26:57 AM UTC 25
Finished Feb 09 12:27:12 AM UTC 25
Peak memory 227300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712236150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ke
y_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 25.kmac_key_error.712236150 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_long_msg_and_output.1234708038
Short name T642
Test name
Test status
Simulation time 91702557429 ps
CPU time 1958.51 seconds
Started Feb 09 12:23:45 AM UTC 25
Finished Feb 09 12:56:45 AM UTC 25
Peak memory 2207856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234708038 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_and_output.1234708038 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_sideload.1652982593
Short name T580
Test name
Test status
Simulation time 61039410888 ps
CPU time 562.88 seconds
Started Feb 09 12:24:05 AM UTC 25
Finished Feb 09 12:33:35 AM UTC 25
Peak memory 614364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652982593 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.1652982593 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_smoke.1118341154
Short name T561
Test name
Test status
Simulation time 14509537509 ps
CPU time 110.58 seconds
Started Feb 09 12:23:14 AM UTC 25
Finished Feb 09 12:25:07 AM UTC 25
Peak memory 235536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118341154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 25.kmac_smoke.1118341154 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_stress_all.3714675304
Short name T614
Test name
Test status
Simulation time 137440655779 ps
CPU time 1161.87 seconds
Started Feb 09 12:27:17 AM UTC 25
Finished Feb 09 12:46:53 AM UTC 25
Peak memory 350656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714675304 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3714675304 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_test_vectors_kmac.100525242
Short name T566
Test name
Test status
Simulation time 223969615 ps
CPU time 8.04 seconds
Started Feb 09 12:26:08 AM UTC 25
Finished Feb 09 12:26:17 AM UTC 25
Peak memory 229432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=100525242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 25.kmac_test_vectors_kmac.100525242 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_test_vectors_kmac_xof.2376426203
Short name T567
Test name
Test status
Simulation time 165360348 ps
CPU time 8.07 seconds
Started Feb 09 12:26:08 AM UTC 25
Finished Feb 09 12:26:17 AM UTC 25
Peak memory 227536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2376426203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 25.kmac_test_vectors_kmac_xof.2376426203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_test_vectors_sha3_224.1147111148
Short name T663
Test name
Test status
Simulation time 83626308238 ps
CPU time 2220.52 seconds
Started Feb 09 12:24:41 AM UTC 25
Finished Feb 09 01:02:06 AM UTC 25
Peak memory 1206168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147111148 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.1147111148 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_test_vectors_sha3_256.1161944934
Short name T652
Test name
Test status
Simulation time 21396748566 ps
CPU time 1975.61 seconds
Started Feb 09 12:24:52 AM UTC 25
Finished Feb 09 12:58:10 AM UTC 25
Peak memory 1154968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161944934 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.1161944934 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_test_vectors_sha3_384.1378392951
Short name T638
Test name
Test status
Simulation time 189836023758 ps
CPU time 1816.27 seconds
Started Feb 09 12:24:57 AM UTC 25
Finished Feb 09 12:55:32 AM UTC 25
Peak memory 2404176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378392951 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.1378392951 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_test_vectors_sha3_512.1548816174
Short name T606
Test name
Test status
Simulation time 10515505098 ps
CPU time 1169.97 seconds
Started Feb 09 12:25:08 AM UTC 25
Finished Feb 09 12:44:51 AM UTC 25
Peak memory 704408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548816174 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.1548816174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_test_vectors_shake_128.1502731447
Short name T933
Test name
Test status
Simulation time 890677866220 ps
CPU time 8426.84 seconds
Started Feb 09 12:25:19 AM UTC 25
Finished Feb 09 02:47:13 AM UTC 25
Peak memory 7741436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502731447 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.1502731447 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/25.kmac_test_vectors_shake_256.1303348305
Short name T842
Test name
Test status
Simulation time 802643117234 ps
CPU time 6451.18 seconds
Started Feb 09 12:25:38 AM UTC 25
Finished Feb 09 02:14:18 AM UTC 25
Peak memory 6471564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303348305 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.1303348305 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_alert_test.103829787
Short name T591
Test name
Test status
Simulation time 59185862 ps
CPU time 1.31 seconds
Started Feb 09 12:39:34 AM UTC 25
Finished Feb 09 12:39:36 AM UTC 25
Peak memory 225648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103829787 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.103829787 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_app.3629746276
Short name T604
Test name
Test status
Simulation time 14073097924 ps
CPU time 463.81 seconds
Started Feb 09 12:36:01 AM UTC 25
Finished Feb 09 12:43:51 AM UTC 25
Peak memory 479272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629746276 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3629746276 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_burst_write.2745890856
Short name T615
Test name
Test status
Simulation time 20047562846 ps
CPU time 1101.92 seconds
Started Feb 09 12:28:30 AM UTC 25
Finished Feb 09 12:47:06 AM UTC 25
Peak memory 260072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745890856 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2745890856 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_entropy_refresh.281469497
Short name T599
Test name
Test status
Simulation time 78193737868 ps
CPU time 300.82 seconds
Started Feb 09 12:37:58 AM UTC 25
Finished Feb 09 12:43:03 AM UTC 25
Peak memory 337912 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281469497 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.281469497 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_error.2032357836
Short name T612
Test name
Test status
Simulation time 18475777246 ps
CPU time 470.02 seconds
Started Feb 09 12:38:17 AM UTC 25
Finished Feb 09 12:46:13 AM UTC 25
Peak memory 397224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032357836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 26.kmac_error.2032357836 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_key_error.1119222375
Short name T588
Test name
Test status
Simulation time 2092042953 ps
CPU time 7.8 seconds
Started Feb 09 12:38:33 AM UTC 25
Finished Feb 09 12:38:42 AM UTC 25
Peak memory 227168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119222375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 26.kmac_key_error.1119222375 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_lc_escalation.192729089
Short name T589
Test name
Test status
Simulation time 44689758 ps
CPU time 2.25 seconds
Started Feb 09 12:38:43 AM UTC 25
Finished Feb 09 12:38:46 AM UTC 25
Peak memory 233584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192729089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.192729089 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_long_msg_and_output.989334592
Short name T674
Test name
Test status
Simulation time 42010289363 ps
CPU time 2634.61 seconds
Started Feb 09 12:28:02 AM UTC 25
Finished Feb 09 01:12:26 AM UTC 25
Peak memory 1458148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989334592 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_and_output.989334592 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_sideload.2581691230
Short name T575
Test name
Test status
Simulation time 2179989118 ps
CPU time 15.53 seconds
Started Feb 09 12:28:13 AM UTC 25
Finished Feb 09 12:28:30 AM UTC 25
Peak memory 251872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581691230 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2581691230 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_smoke.2310856628
Short name T573
Test name
Test status
Simulation time 1885942593 ps
CPU time 12.7 seconds
Started Feb 09 12:27:47 AM UTC 25
Finished Feb 09 12:28:01 AM UTC 25
Peak memory 235420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310856628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 26.kmac_smoke.2310856628 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_stress_all.43313032
Short name T593
Test name
Test status
Simulation time 5494492539 ps
CPU time 99.42 seconds
Started Feb 09 12:38:47 AM UTC 25
Finished Feb 09 12:40:29 AM UTC 25
Peak memory 257956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43313032 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.43313032 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_test_vectors_kmac.1627257047
Short name T583
Test name
Test status
Simulation time 221718202 ps
CPU time 7.87 seconds
Started Feb 09 12:35:41 AM UTC 25
Finished Feb 09 12:35:50 AM UTC 25
Peak memory 235404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1627257047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.kmac_test_vectors_kmac.1627257047 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_test_vectors_kmac_xof.1386553556
Short name T584
Test name
Test status
Simulation time 996766119 ps
CPU time 8.42 seconds
Started Feb 09 12:35:51 AM UTC 25
Finished Feb 09 12:36:00 AM UTC 25
Peak memory 229584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1386553556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 26.kmac_test_vectors_kmac_xof.1386553556 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_test_vectors_sha3_224.3262404958
Short name T691
Test name
Test status
Simulation time 98645452326 ps
CPU time 2836.21 seconds
Started Feb 09 12:30:03 AM UTC 25
Finished Feb 09 01:17:49 AM UTC 25
Peak memory 3155800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262404958 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.3262404958 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_test_vectors_sha3_256.1916973837
Short name T681
Test name
Test status
Simulation time 81551919267 ps
CPU time 2608.79 seconds
Started Feb 09 12:30:41 AM UTC 25
Finished Feb 09 01:14:42 AM UTC 25
Peak memory 1179616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916973837 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.1916973837 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_test_vectors_sha3_384.3341814042
Short name T655
Test name
Test status
Simulation time 31016550277 ps
CPU time 1641.41 seconds
Started Feb 09 12:32:05 AM UTC 25
Finished Feb 09 12:59:46 AM UTC 25
Peak memory 927576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341814042 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.3341814042 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_test_vectors_sha3_512.3785200325
Short name T641
Test name
Test status
Simulation time 34969319055 ps
CPU time 1405.48 seconds
Started Feb 09 12:33:02 AM UTC 25
Finished Feb 09 12:56:43 AM UTC 25
Peak memory 1738592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785200325 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3785200325 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_test_vectors_shake_128.2416597104
Short name T844
Test name
Test status
Simulation time 254636262584 ps
CPU time 5990.62 seconds
Started Feb 09 12:33:36 AM UTC 25
Finished Feb 09 02:14:31 AM UTC 25
Peak memory 2748252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416597104 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2416597104 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/26.kmac_test_vectors_shake_256.1886933800
Short name T786
Test name
Test status
Simulation time 53154920007 ps
CPU time 4601.25 seconds
Started Feb 09 12:33:52 AM UTC 25
Finished Feb 09 01:51:23 AM UTC 25
Peak memory 2221908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886933800 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.1886933800 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_alert_test.2692641593
Short name T610
Test name
Test status
Simulation time 13861004 ps
CPU time 1.26 seconds
Started Feb 09 12:46:01 AM UTC 25
Finished Feb 09 12:46:03 AM UTC 25
Peak memory 226232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692641593 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2692641593 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_app.722890302
Short name T609
Test name
Test status
Simulation time 2830476432 ps
CPU time 126.72 seconds
Started Feb 09 12:43:51 AM UTC 25
Finished Feb 09 12:46:00 AM UTC 25
Peak memory 266204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722890302 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.722890302 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_burst_write.667598735
Short name T611
Test name
Test status
Simulation time 25118263684 ps
CPU time 317.95 seconds
Started Feb 09 12:40:50 AM UTC 25
Finished Feb 09 12:46:13 AM UTC 25
Peak memory 251816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667598735 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.667598735 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_entropy_refresh.3330268761
Short name T81
Test name
Test status
Simulation time 7392811068 ps
CPU time 353.68 seconds
Started Feb 09 12:43:52 AM UTC 25
Finished Feb 09 12:49:50 AM UTC 25
Peak memory 346064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330268761 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.3330268761 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_error.3085181359
Short name T621
Test name
Test status
Simulation time 34032515448 ps
CPU time 382.39 seconds
Started Feb 09 12:44:00 AM UTC 25
Finished Feb 09 12:50:28 AM UTC 25
Peak memory 505816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085181359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 27.kmac_error.3085181359 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_key_error.2585377739
Short name T607
Test name
Test status
Simulation time 3136452076 ps
CPU time 10.96 seconds
Started Feb 09 12:44:52 AM UTC 25
Finished Feb 09 12:45:05 AM UTC 25
Peak memory 229328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585377739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 27.kmac_key_error.2585377739 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_lc_escalation.2927604878
Short name T52
Test name
Test status
Simulation time 148503990 ps
CPU time 2.16 seconds
Started Feb 09 12:45:06 AM UTC 25
Finished Feb 09 12:45:09 AM UTC 25
Peak memory 233508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927604878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.2927604878 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_long_msg_and_output.1674093869
Short name T697
Test name
Test status
Simulation time 85754683896 ps
CPU time 2454.5 seconds
Started Feb 09 12:39:43 AM UTC 25
Finished Feb 09 01:21:04 AM UTC 25
Peak memory 1435564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674093869 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and_output.1674093869 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_sideload.2162300782
Short name T608
Test name
Test status
Simulation time 4308510250 ps
CPU time 324.91 seconds
Started Feb 09 12:40:30 AM UTC 25
Finished Feb 09 12:46:00 AM UTC 25
Peak memory 358364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162300782 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2162300782 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_smoke.559553169
Short name T594
Test name
Test status
Simulation time 3784510239 ps
CPU time 70.59 seconds
Started Feb 09 12:39:37 AM UTC 25
Finished Feb 09 12:40:49 AM UTC 25
Peak memory 235400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559553169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 27.kmac_smoke.559553169 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_stress_all.3461202903
Short name T673
Test name
Test status
Simulation time 61330675322 ps
CPU time 1607.33 seconds
Started Feb 09 12:45:10 AM UTC 25
Finished Feb 09 01:12:16 AM UTC 25
Peak memory 595924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461202903 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3461202903 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_test_vectors_kmac.2529787059
Short name T603
Test name
Test status
Simulation time 193646312 ps
CPU time 8.6 seconds
Started Feb 09 12:43:39 AM UTC 25
Finished Feb 09 12:43:49 AM UTC 25
Peak memory 235564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2529787059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 27.kmac_test_vectors_kmac.2529787059 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_test_vectors_kmac_xof.3456804487
Short name T605
Test name
Test status
Simulation time 267693076 ps
CPU time 9.23 seconds
Started Feb 09 12:43:49 AM UTC 25
Finished Feb 09 12:43:59 AM UTC 25
Peak memory 229416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3456804487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 27.kmac_test_vectors_kmac_xof.3456804487 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_test_vectors_sha3_224.3530447720
Short name T729
Test name
Test status
Simulation time 66502395963 ps
CPU time 3211.01 seconds
Started Feb 09 12:41:13 AM UTC 25
Finished Feb 09 01:35:21 AM UTC 25
Peak memory 3288980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530447720 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.3530447720 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_test_vectors_sha3_256.3928041812
Short name T685
Test name
Test status
Simulation time 20465474407 ps
CPU time 2030.48 seconds
Started Feb 09 12:41:42 AM UTC 25
Finished Feb 09 01:15:55 AM UTC 25
Peak memory 1142744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928041812 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.3928041812 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_test_vectors_sha3_384.688191991
Short name T686
Test name
Test status
Simulation time 54499619187 ps
CPU time 1994.16 seconds
Started Feb 09 12:42:32 AM UTC 25
Finished Feb 09 01:16:08 AM UTC 25
Peak memory 2322328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688191991 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.688191991 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_test_vectors_sha3_512.2018124181
Short name T669
Test name
Test status
Simulation time 11777304930 ps
CPU time 1425.33 seconds
Started Feb 09 12:42:52 AM UTC 25
Finished Feb 09 01:06:55 AM UTC 25
Peak memory 716768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018124181 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.2018124181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_test_vectors_shake_128.2733938668
Short name T1029
Test name
Test status
Simulation time 264750297155 ps
CPU time 9894.46 seconds
Started Feb 09 12:43:04 AM UTC 25
Finished Feb 09 03:29:44 AM UTC 25
Peak memory 7864380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733938668 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.2733938668 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/27.kmac_test_vectors_shake_256.1011194891
Short name T940
Test name
Test status
Simulation time 452582763709 ps
CPU time 7638.28 seconds
Started Feb 09 12:43:34 AM UTC 25
Finished Feb 09 02:52:12 AM UTC 25
Peak memory 6502412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011194891 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.1011194891 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/27.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_alert_test.2405899065
Short name T627
Test name
Test status
Simulation time 17636020 ps
CPU time 1.34 seconds
Started Feb 09 12:51:26 AM UTC 25
Finished Feb 09 12:51:29 AM UTC 25
Peak memory 225704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405899065 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.2405899065 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_app.2317150108
Short name T631
Test name
Test status
Simulation time 2871139685 ps
CPU time 93.46 seconds
Started Feb 09 12:50:11 AM UTC 25
Finished Feb 09 12:51:46 AM UTC 25
Peak memory 288684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317150108 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.2317150108 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_burst_write.1186052754
Short name T635
Test name
Test status
Simulation time 22699131435 ps
CPU time 466.15 seconds
Started Feb 09 12:46:14 AM UTC 25
Finished Feb 09 12:54:07 AM UTC 25
Peak memory 247704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186052754 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1186052754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_entropy_refresh.2166088768
Short name T622
Test name
Test status
Simulation time 1875948011 ps
CPU time 11.39 seconds
Started Feb 09 12:50:29 AM UTC 25
Finished Feb 09 12:50:42 AM UTC 25
Peak memory 235368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166088768 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.2166088768 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_error.2903500119
Short name T657
Test name
Test status
Simulation time 56518357414 ps
CPU time 548.96 seconds
Started Feb 09 12:50:43 AM UTC 25
Finished Feb 09 01:00:00 AM UTC 25
Peak memory 565156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903500119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 28.kmac_error.2903500119 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_key_error.3741818163
Short name T624
Test name
Test status
Simulation time 283657656 ps
CPU time 2.48 seconds
Started Feb 09 12:51:08 AM UTC 25
Finished Feb 09 12:51:13 AM UTC 25
Peak memory 227168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741818163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 28.kmac_key_error.3741818163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_lc_escalation.310029099
Short name T625
Test name
Test status
Simulation time 59815465 ps
CPU time 1.97 seconds
Started Feb 09 12:51:14 AM UTC 25
Finished Feb 09 12:51:17 AM UTC 25
Peak memory 231012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310029099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.310029099 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_long_msg_and_output.1653520003
Short name T678
Test name
Test status
Simulation time 243760198729 ps
CPU time 1675.44 seconds
Started Feb 09 12:46:04 AM UTC 25
Finished Feb 09 01:14:19 AM UTC 25
Peak memory 1935408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653520003 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_and_output.1653520003 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_sideload.2300917444
Short name T617
Test name
Test status
Simulation time 1964878916 ps
CPU time 156.67 seconds
Started Feb 09 12:46:14 AM UTC 25
Finished Feb 09 12:48:54 AM UTC 25
Peak memory 280548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300917444 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2300917444 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_smoke.3880808319
Short name T613
Test name
Test status
Simulation time 653177737 ps
CPU time 18.37 seconds
Started Feb 09 12:46:01 AM UTC 25
Finished Feb 09 12:46:21 AM UTC 25
Peak memory 235360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880808319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 28.kmac_smoke.3880808319 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_stress_all.1074712572
Short name T636
Test name
Test status
Simulation time 25200648605 ps
CPU time 244.62 seconds
Started Feb 09 12:51:18 AM UTC 25
Finished Feb 09 12:55:26 AM UTC 25
Peak memory 364436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074712572 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1074712572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_test_vectors_kmac.2445662373
Short name T619
Test name
Test status
Simulation time 196619619 ps
CPU time 7.34 seconds
Started Feb 09 12:49:51 AM UTC 25
Finished Feb 09 12:50:00 AM UTC 25
Peak memory 229556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2445662373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 28.kmac_test_vectors_kmac.2445662373 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_test_vectors_kmac_xof.3140095361
Short name T620
Test name
Test status
Simulation time 117654602 ps
CPU time 7.54 seconds
Started Feb 09 12:50:00 AM UTC 25
Finished Feb 09 12:50:09 AM UTC 25
Peak memory 229456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3140095361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 28.kmac_test_vectors_kmac_xof.3140095361 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_test_vectors_sha3_224.1167445201
Short name T711
Test name
Test status
Simulation time 24431543836 ps
CPU time 2454.36 seconds
Started Feb 09 12:46:22 AM UTC 25
Finished Feb 09 01:27:44 AM UTC 25
Peak memory 1220440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167445201 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.1167445201 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_test_vectors_sha3_256.695834380
Short name T719
Test name
Test status
Simulation time 175818121082 ps
CPU time 2614.48 seconds
Started Feb 09 12:46:54 AM UTC 25
Finished Feb 09 01:30:55 AM UTC 25
Peak memory 3114968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695834380 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.695834380 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_test_vectors_sha3_384.3866790684
Short name T692
Test name
Test status
Simulation time 15018779945 ps
CPU time 1844.42 seconds
Started Feb 09 12:47:07 AM UTC 25
Finished Feb 09 01:18:14 AM UTC 25
Peak memory 919392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866790684 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.3866790684 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_test_vectors_sha3_512.2703168368
Short name T695
Test name
Test status
Simulation time 123077374985 ps
CPU time 1831.29 seconds
Started Feb 09 12:48:35 AM UTC 25
Finished Feb 09 01:19:28 AM UTC 25
Peak memory 1738776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703168368 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.2703168368 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_test_vectors_shake_128.1509139426
Short name T1035
Test name
Test status
Simulation time 953620365359 ps
CPU time 9817.86 seconds
Started Feb 09 12:48:55 AM UTC 25
Finished Feb 09 03:34:15 AM UTC 25
Peak memory 7786476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509139426 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.1509139426 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/28.kmac_test_vectors_shake_256.2241912706
Short name T916
Test name
Test status
Simulation time 157004714702 ps
CPU time 6733.37 seconds
Started Feb 09 12:49:17 AM UTC 25
Finished Feb 09 02:42:42 AM UTC 25
Peak memory 6463496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241912706 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.2241912706 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_alert_test.2200689366
Short name T645
Test name
Test status
Simulation time 25586790 ps
CPU time 1.34 seconds
Started Feb 09 12:57:00 AM UTC 25
Finished Feb 09 12:57:02 AM UTC 25
Peak memory 225464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200689366 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2200689366 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_app.2816541244
Short name T647
Test name
Test status
Simulation time 1944058629 ps
CPU time 93.07 seconds
Started Feb 09 12:55:43 AM UTC 25
Finished Feb 09 12:57:19 AM UTC 25
Peak memory 253992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816541244 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.2816541244 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_burst_write.1833938946
Short name T644
Test name
Test status
Simulation time 9392787996 ps
CPU time 310.19 seconds
Started Feb 09 12:51:40 AM UTC 25
Finished Feb 09 12:56:55 AM UTC 25
Peak memory 239532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833938946 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.1833938946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_entropy_refresh.2827990854
Short name T667
Test name
Test status
Simulation time 240317473078 ps
CPU time 506.05 seconds
Started Feb 09 12:55:44 AM UTC 25
Finished Feb 09 01:04:17 AM UTC 25
Peak memory 483236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827990854 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2827990854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_error.48526054
Short name T646
Test name
Test status
Simulation time 1131381499 ps
CPU time 29.36 seconds
Started Feb 09 12:56:44 AM UTC 25
Finished Feb 09 12:57:15 AM UTC 25
Peak memory 247652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48526054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_err
or_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 29.kmac_error.48526054 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_key_error.3754358810
Short name T643
Test name
Test status
Simulation time 1619759234 ps
CPU time 7.95 seconds
Started Feb 09 12:56:45 AM UTC 25
Finished Feb 09 12:56:54 AM UTC 25
Peak memory 227228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754358810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 29.kmac_key_error.3754358810 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_lc_escalation.4189063717
Short name T57
Test name
Test status
Simulation time 153094373 ps
CPU time 2.2 seconds
Started Feb 09 12:56:56 AM UTC 25
Finished Feb 09 12:56:59 AM UTC 25
Peak memory 233512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189063717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.4189063717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_long_msg_and_output.2253825609
Short name T737
Test name
Test status
Simulation time 317880657402 ps
CPU time 2734.79 seconds
Started Feb 09 12:51:34 AM UTC 25
Finished Feb 09 01:37:39 AM UTC 25
Peak memory 3182548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253825609 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_and_output.2253825609 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_sideload.1448578844
Short name T650
Test name
Test status
Simulation time 13971080082 ps
CPU time 365.22 seconds
Started Feb 09 12:51:36 AM UTC 25
Finished Feb 09 12:57:46 AM UTC 25
Peak memory 532568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448578844 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.1448578844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_smoke.494176551
Short name T632
Test name
Test status
Simulation time 6231831682 ps
CPU time 74.25 seconds
Started Feb 09 12:51:29 AM UTC 25
Finished Feb 09 12:52:46 AM UTC 25
Peak memory 235484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494176551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 29.kmac_smoke.494176551 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_stress_all.2061128077
Short name T653
Test name
Test status
Simulation time 1126304256 ps
CPU time 102.09 seconds
Started Feb 09 12:56:56 AM UTC 25
Finished Feb 09 12:58:40 AM UTC 25
Peak memory 268312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061128077 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.2061128077 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_test_vectors_kmac.2071016814
Short name T639
Test name
Test status
Simulation time 1278680888 ps
CPU time 9.54 seconds
Started Feb 09 12:55:31 AM UTC 25
Finished Feb 09 12:55:42 AM UTC 25
Peak memory 235400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2071016814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 29.kmac_test_vectors_kmac.2071016814 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_test_vectors_kmac_xof.2466355972
Short name T640
Test name
Test status
Simulation time 1010694750 ps
CPU time 8.82 seconds
Started Feb 09 12:55:32 AM UTC 25
Finished Feb 09 12:55:42 AM UTC 25
Peak memory 227352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2466355972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 29.kmac_test_vectors_kmac_xof.2466355972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_test_vectors_sha3_224.2841710554
Short name T778
Test name
Test status
Simulation time 274515475781 ps
CPU time 3346.73 seconds
Started Feb 09 12:51:47 AM UTC 25
Finished Feb 09 01:48:12 AM UTC 25
Peak memory 3254112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841710554 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2841710554 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_test_vectors_sha3_256.1069405689
Short name T733
Test name
Test status
Simulation time 367729295662 ps
CPU time 2602.17 seconds
Started Feb 09 12:52:47 AM UTC 25
Finished Feb 09 01:36:36 AM UTC 25
Peak memory 3108704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069405689 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.1069405689 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_test_vectors_sha3_384.724712307
Short name T705
Test name
Test status
Simulation time 75469089993 ps
CPU time 1827.85 seconds
Started Feb 09 12:53:06 AM UTC 25
Finished Feb 09 01:23:55 AM UTC 25
Peak memory 941972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724712307 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.724712307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_test_vectors_sha3_512.533500293
Short name T683
Test name
Test status
Simulation time 12034334566 ps
CPU time 1258.34 seconds
Started Feb 09 12:53:44 AM UTC 25
Finished Feb 09 01:14:57 AM UTC 25
Peak memory 712544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533500293 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.533500293 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_test_vectors_shake_128.706074711
Short name T976
Test name
Test status
Simulation time 246313429071 ps
CPU time 7916.39 seconds
Started Feb 09 12:54:07 AM UTC 25
Finished Feb 09 03:07:25 AM UTC 25
Peak memory 7767900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706074711 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.706074711 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/29.kmac_test_vectors_shake_256.557286599
Short name T898
Test name
Test status
Simulation time 148490747280 ps
CPU time 5976.72 seconds
Started Feb 09 12:55:28 AM UTC 25
Finished Feb 09 02:36:06 AM UTC 25
Peak memory 6352908 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557286599 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.557286599 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_alert_test.3084314598
Short name T199
Test name
Test status
Simulation time 25485919 ps
CPU time 1.27 seconds
Started Feb 08 09:44:14 PM UTC 25
Finished Feb 08 09:44:17 PM UTC 25
Peak memory 225700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084314598 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.3084314598 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_app.3951693693
Short name T191
Test name
Test status
Simulation time 22542823384 ps
CPU time 185.98 seconds
Started Feb 08 09:42:18 PM UTC 25
Finished Feb 08 09:45:27 PM UTC 25
Peak memory 292980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951693693 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.3951693693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_app_with_partial_data.2514249998
Short name T148
Test name
Test status
Simulation time 125386842 ps
CPU time 3.07 seconds
Started Feb 08 09:42:19 PM UTC 25
Finished Feb 08 09:42:23 PM UTC 25
Peak memory 227436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514249998 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2514249998 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_burst_write.1249243859
Short name T152
Test name
Test status
Simulation time 92694854244 ps
CPU time 1177.64 seconds
Started Feb 08 09:38:54 PM UTC 25
Finished Feb 08 09:58:47 PM UTC 25
Peak memory 262052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249243859 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1249243859 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_edn_timeout_error.4258774539
Short name T73
Test name
Test status
Simulation time 34847944 ps
CPU time 1.42 seconds
Started Feb 08 09:43:22 PM UTC 25
Finished Feb 08 09:43:24 PM UTC 25
Peak memory 227156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258774539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.4258774539 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_mode_error.240294146
Short name T198
Test name
Test status
Simulation time 553537937 ps
CPU time 24.06 seconds
Started Feb 08 09:43:25 PM UTC 25
Finished Feb 08 09:43:50 PM UTC 25
Peak memory 235068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240294146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.240294146 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_ready_error.1231154530
Short name T174
Test name
Test status
Simulation time 11980781088 ps
CPU time 46.54 seconds
Started Feb 08 09:43:25 PM UTC 25
Finished Feb 08 09:44:13 PM UTC 25
Peak memory 235436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231154530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
ntropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1231154530 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_entropy_refresh.478535631
Short name T25
Test name
Test status
Simulation time 18295143215 ps
CPU time 216.73 seconds
Started Feb 08 09:42:24 PM UTC 25
Finished Feb 08 09:46:04 PM UTC 25
Peak memory 290980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478535631 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.478535631 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_error.290250260
Short name T162
Test name
Test status
Simulation time 619125177 ps
CPU time 30.9 seconds
Started Feb 08 09:43:06 PM UTC 25
Finished Feb 08 09:43:39 PM UTC 25
Peak memory 251800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290250260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_er
ror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 3.kmac_error.290250260 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_key_error.1365006022
Short name T113
Test name
Test status
Simulation time 1898576688 ps
CPU time 7.02 seconds
Started Feb 08 09:43:12 PM UTC 25
Finished Feb 08 09:43:21 PM UTC 25
Peak memory 229268 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365006022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.kmac_key_error.1365006022 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_lc_escalation.1793194262
Short name T32
Test name
Test status
Simulation time 263717786 ps
CPU time 1.96 seconds
Started Feb 08 09:43:26 PM UTC 25
Finished Feb 08 09:43:29 PM UTC 25
Peak memory 231024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793194262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.1793194262 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_long_msg_and_output.1746961092
Short name T286
Test name
Test status
Simulation time 256837551996 ps
CPU time 3035.46 seconds
Started Feb 08 09:37:58 PM UTC 25
Finished Feb 08 10:29:08 PM UTC 25
Peak memory 3092360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746961092 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.1746961092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_mubi.3755391788
Short name T59
Test name
Test status
Simulation time 1452008668 ps
CPU time 28.08 seconds
Started Feb 08 09:42:36 PM UTC 25
Finished Feb 08 09:43:06 PM UTC 25
Peak memory 236008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755391788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_m
ubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 3.kmac_mubi.3755391788 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_sec_cm.3929886174
Short name T86
Test name
Test status
Simulation time 30862196726 ps
CPU time 171.04 seconds
Started Feb 08 09:43:51 PM UTC 25
Finished Feb 08 09:46:45 PM UTC 25
Peak memory 310384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929886174 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3929886174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_sideload.3549932650
Short name T26
Test name
Test status
Simulation time 23207477047 ps
CPU time 304.1 seconds
Started Feb 08 09:38:16 PM UTC 25
Finished Feb 08 09:43:25 PM UTC 25
Peak memory 436196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549932650 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3549932650 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac.819999437
Short name T145
Test name
Test status
Simulation time 356342318 ps
CPU time 7.96 seconds
Started Feb 08 09:41:57 PM UTC 25
Finished Feb 08 09:42:06 PM UTC 25
Peak memory 227536 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=819999437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 3.kmac_test_vectors_kmac.819999437 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_kmac_xof.2481383870
Short name T146
Test name
Test status
Simulation time 954924100 ps
CPU time 8.94 seconds
Started Feb 08 09:42:07 PM UTC 25
Finished Feb 08 09:42:17 PM UTC 25
Peak memory 229424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2481383870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 3.kmac_test_vectors_kmac_xof.2481383870 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_224.1904994422
Short name T266
Test name
Test status
Simulation time 21553138323 ps
CPU time 2418.34 seconds
Started Feb 08 09:39:42 PM UTC 25
Finished Feb 08 10:20:28 PM UTC 25
Peak memory 1220632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904994422 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1904994422 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_256.4103603580
Short name T299
Test name
Test status
Simulation time 192894844052 ps
CPU time 3014.99 seconds
Started Feb 08 09:40:39 PM UTC 25
Finished Feb 08 10:31:27 PM UTC 25
Peak memory 3094492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103603580 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.4103603580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_384.1815959537
Short name T262
Test name
Test status
Simulation time 142646221550 ps
CPU time 2290.59 seconds
Started Feb 08 09:40:59 PM UTC 25
Finished Feb 08 10:19:34 PM UTC 25
Peak memory 2441012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815959537 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1815959537 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_sha3_512.730283998
Short name T219
Test name
Test status
Simulation time 11204891525 ps
CPU time 1341.61 seconds
Started Feb 08 09:41:15 PM UTC 25
Finished Feb 08 10:03:52 PM UTC 25
Peak memory 722960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730283998 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.730283998 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_128.3517351456
Short name T405
Test name
Test status
Simulation time 100715116638 ps
CPU time 5914.24 seconds
Started Feb 08 09:41:17 PM UTC 25
Finished Feb 08 11:20:55 PM UTC 25
Peak memory 2701276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517351456 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3517351456 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/3.kmac_test_vectors_shake_256.4134637058
Short name T438
Test name
Test status
Simulation time 601517752047 ps
CPU time 6579.82 seconds
Started Feb 08 09:41:27 PM UTC 25
Finished Feb 08 11:32:15 PM UTC 25
Peak memory 6428564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134637058 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.4134637058 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_alert_test.2760406122
Short name T664
Test name
Test status
Simulation time 33804678 ps
CPU time 1.06 seconds
Started Feb 09 01:02:07 AM UTC 25
Finished Feb 09 01:02:09 AM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760406122 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2760406122 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_app.2334872467
Short name T659
Test name
Test status
Simulation time 735729082 ps
CPU time 10.41 seconds
Started Feb 09 01:00:01 AM UTC 25
Finished Feb 09 01:00:21 AM UTC 25
Peak memory 229432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334872467 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2334872467 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_burst_write.3275557215
Short name T684
Test name
Test status
Simulation time 9579848534 ps
CPU time 1065.98 seconds
Started Feb 09 12:57:41 AM UTC 25
Finished Feb 09 01:15:39 AM UTC 25
Peak memory 249780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275557215 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.3275557215 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_entropy_refresh.2221349615
Short name T660
Test name
Test status
Simulation time 1875176573 ps
CPU time 72.2 seconds
Started Feb 09 01:00:11 AM UTC 25
Finished Feb 09 01:01:25 AM UTC 25
Peak memory 245736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221349615 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2221349615 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_error.2892278207
Short name T666
Test name
Test status
Simulation time 19921413701 ps
CPU time 218.56 seconds
Started Feb 09 01:00:22 AM UTC 25
Finished Feb 09 01:04:04 AM UTC 25
Peak memory 358488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892278207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 30.kmac_error.2892278207 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_key_error.3307713476
Short name T661
Test name
Test status
Simulation time 6246676138 ps
CPU time 23.15 seconds
Started Feb 09 01:01:27 AM UTC 25
Finished Feb 09 01:01:51 AM UTC 25
Peak memory 229276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307713476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 30.kmac_key_error.3307713476 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_lc_escalation.944218865
Short name T662
Test name
Test status
Simulation time 102197772 ps
CPU time 2.6 seconds
Started Feb 09 01:01:52 AM UTC 25
Finished Feb 09 01:01:55 AM UTC 25
Peak memory 231404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944218865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.944218865 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_long_msg_and_output.3894614977
Short name T766
Test name
Test status
Simulation time 103741783234 ps
CPU time 2856.57 seconds
Started Feb 09 12:57:16 AM UTC 25
Finished Feb 09 01:45:22 AM UTC 25
Peak memory 1828740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894614977 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_and_output.3894614977 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_sideload.2530201759
Short name T651
Test name
Test status
Simulation time 1220403873 ps
CPU time 38.89 seconds
Started Feb 09 12:57:19 AM UTC 25
Finished Feb 09 12:58:00 AM UTC 25
Peak memory 237548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530201759 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.2530201759 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_smoke.4135384009
Short name T654
Test name
Test status
Simulation time 13774198664 ps
CPU time 97.87 seconds
Started Feb 09 12:57:03 AM UTC 25
Finished Feb 09 12:58:43 AM UTC 25
Peak memory 235424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135384009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 30.kmac_smoke.4135384009 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_stress_all.3657248560
Short name T755
Test name
Test status
Simulation time 69611434265 ps
CPU time 2351.81 seconds
Started Feb 09 01:01:56 AM UTC 25
Finished Feb 09 01:41:35 AM UTC 25
Peak memory 1225000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657248560 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.3657248560 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_test_vectors_kmac.1549601754
Short name T656
Test name
Test status
Simulation time 628555775 ps
CPU time 8.86 seconds
Started Feb 09 12:59:47 AM UTC 25
Finished Feb 09 12:59:57 AM UTC 25
Peak memory 229396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1549601754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 30.kmac_test_vectors_kmac.1549601754 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_test_vectors_kmac_xof.2344156187
Short name T658
Test name
Test status
Simulation time 228821509 ps
CPU time 6.28 seconds
Started Feb 09 12:59:59 AM UTC 25
Finished Feb 09 01:00:06 AM UTC 25
Peak memory 235360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2344156187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 30.kmac_test_vectors_kmac_xof.2344156187 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_test_vectors_sha3_224.2598929085
Short name T784
Test name
Test status
Simulation time 1619829655036 ps
CPU time 3066.46 seconds
Started Feb 09 12:57:46 AM UTC 25
Finished Feb 09 01:49:24 AM UTC 25
Peak memory 3252064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598929085 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.2598929085 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_test_vectors_sha3_256.1472936694
Short name T727
Test name
Test status
Simulation time 79771166952 ps
CPU time 2175.77 seconds
Started Feb 09 12:57:47 AM UTC 25
Finished Feb 09 01:34:27 AM UTC 25
Peak memory 1148816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472936694 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.1472936694 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_test_vectors_sha3_384.1023581203
Short name T735
Test name
Test status
Simulation time 623988126812 ps
CPU time 2343.16 seconds
Started Feb 09 12:58:01 AM UTC 25
Finished Feb 09 01:37:29 AM UTC 25
Peak memory 2441044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023581203 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.1023581203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_test_vectors_sha3_512.3010099481
Short name T690
Test name
Test status
Simulation time 39446118413 ps
CPU time 1121.19 seconds
Started Feb 09 12:58:10 AM UTC 25
Finished Feb 09 01:17:03 AM UTC 25
Peak memory 718872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010099481 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.3010099481 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_test_vectors_shake_128.3575552406
Short name T970
Test name
Test status
Simulation time 335593435285 ps
CPU time 7602.67 seconds
Started Feb 09 12:58:41 AM UTC 25
Finished Feb 09 03:06:41 AM UTC 25
Peak memory 7882584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575552406 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.3575552406 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/30.kmac_test_vectors_shake_256.3580154424
Short name T848
Test name
Test status
Simulation time 222106758842 ps
CPU time 4574.91 seconds
Started Feb 09 12:58:44 AM UTC 25
Finished Feb 09 02:15:47 AM UTC 25
Peak memory 2201684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580154424 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3580154424 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_alert_test.4191035465
Short name T682
Test name
Test status
Simulation time 29602602 ps
CPU time 1.45 seconds
Started Feb 09 01:14:46 AM UTC 25
Finished Feb 09 01:14:49 AM UTC 25
Peak memory 224264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191035465 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.4191035465 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_app.1941924788
Short name T679
Test name
Test status
Simulation time 2518821637 ps
CPU time 98.04 seconds
Started Feb 09 01:12:49 AM UTC 25
Finished Feb 09 01:14:29 AM UTC 25
Peak memory 257996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941924788 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1941924788 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_burst_write.3305661467
Short name T709
Test name
Test status
Simulation time 22656191750 ps
CPU time 1227.1 seconds
Started Feb 09 01:04:17 AM UTC 25
Finished Feb 09 01:24:58 AM UTC 25
Peak memory 253872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305661467 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.3305661467 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_entropy_refresh.3958298789
Short name T688
Test name
Test status
Simulation time 47202247987 ps
CPU time 165.65 seconds
Started Feb 09 01:13:32 AM UTC 25
Finished Feb 09 01:16:21 AM UTC 25
Peak memory 274492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958298789 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3958298789 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_error.2926438440
Short name T703
Test name
Test status
Simulation time 13615009264 ps
CPU time 521.66 seconds
Started Feb 09 01:14:20 AM UTC 25
Finished Feb 09 01:23:08 AM UTC 25
Peak memory 600028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926438440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 31.kmac_error.2926438440 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_key_error.4052993382
Short name T680
Test name
Test status
Simulation time 639959065 ps
CPU time 8.84 seconds
Started Feb 09 01:14:30 AM UTC 25
Finished Feb 09 01:14:40 AM UTC 25
Peak memory 229344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052993382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 31.kmac_key_error.4052993382 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_lc_escalation.1348613525
Short name T84
Test name
Test status
Simulation time 46623794 ps
CPU time 2.93 seconds
Started Feb 09 01:14:41 AM UTC 25
Finished Feb 09 01:14:45 AM UTC 25
Peak memory 233684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348613525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.1348613525 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_long_msg_and_output.3988731946
Short name T765
Test name
Test status
Simulation time 59762576512 ps
CPU time 2500.82 seconds
Started Feb 09 01:03:10 AM UTC 25
Finished Feb 09 01:45:16 AM UTC 25
Peak memory 2920424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988731946 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_and_output.3988731946 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_sideload.2969035058
Short name T677
Test name
Test status
Simulation time 75769656103 ps
CPU time 558.21 seconds
Started Feb 09 01:04:05 AM UTC 25
Finished Feb 09 01:13:31 AM UTC 25
Peak memory 583596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969035058 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2969035058 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_smoke.3925399091
Short name T665
Test name
Test status
Simulation time 2020323537 ps
CPU time 56.91 seconds
Started Feb 09 01:02:10 AM UTC 25
Finished Feb 09 01:03:09 AM UTC 25
Peak memory 235360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925399091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 31.kmac_smoke.3925399091 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_stress_all.2333245146
Short name T734
Test name
Test status
Simulation time 34785340780 ps
CPU time 1299.89 seconds
Started Feb 09 01:14:43 AM UTC 25
Finished Feb 09 01:36:38 AM UTC 25
Peak memory 1611744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333245146 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2333245146 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_test_vectors_kmac.2899782805
Short name T675
Test name
Test status
Simulation time 287848582 ps
CPU time 9.17 seconds
Started Feb 09 01:12:27 AM UTC 25
Finished Feb 09 01:12:38 AM UTC 25
Peak memory 229556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2899782805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 31.kmac_test_vectors_kmac.2899782805 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_test_vectors_kmac_xof.2584570195
Short name T676
Test name
Test status
Simulation time 132767334 ps
CPU time 7.75 seconds
Started Feb 09 01:12:39 AM UTC 25
Finished Feb 09 01:12:48 AM UTC 25
Peak memory 227368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2584570195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 31.kmac_test_vectors_kmac_xof.2584570195 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_test_vectors_sha3_224.1138487586
Short name T798
Test name
Test status
Simulation time 112412585231 ps
CPU time 2944.42 seconds
Started Feb 09 01:05:05 AM UTC 25
Finished Feb 09 01:54:41 AM UTC 25
Peak memory 3153948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138487586 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.1138487586 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_test_vectors_sha3_256.2699522111
Short name T804
Test name
Test status
Simulation time 366031522124 ps
CPU time 2944.64 seconds
Started Feb 09 01:06:56 AM UTC 25
Finished Feb 09 01:56:33 AM UTC 25
Peak memory 3055704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699522111 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.2699522111 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_test_vectors_sha3_384.2280260883
Short name T746
Test name
Test status
Simulation time 195218141123 ps
CPU time 2003.42 seconds
Started Feb 09 01:07:05 AM UTC 25
Finished Feb 09 01:40:49 AM UTC 25
Peak memory 2381708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280260883 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.2280260883 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_test_vectors_sha3_512.1355404760
Short name T728
Test name
Test status
Simulation time 213448102072 ps
CPU time 1638.05 seconds
Started Feb 09 01:07:10 AM UTC 25
Finished Feb 09 01:34:46 AM UTC 25
Peak memory 1742712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355404760 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1355404760 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_test_vectors_shake_128.813731542
Short name T981
Test name
Test status
Simulation time 240415463086 ps
CPU time 7082.14 seconds
Started Feb 09 01:08:55 AM UTC 25
Finished Feb 09 03:08:17 AM UTC 25
Peak memory 2703188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813731542 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.813731542 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/31.kmac_test_vectors_shake_256.3209502591
Short name T1011
Test name
Test status
Simulation time 806522168571 ps
CPU time 7527.64 seconds
Started Feb 09 01:12:17 AM UTC 25
Finished Feb 09 03:19:05 AM UTC 25
Peak memory 6424592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209502591 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3209502591 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_alert_test.2477036896
Short name T701
Test name
Test status
Simulation time 119777646 ps
CPU time 1.27 seconds
Started Feb 09 01:21:38 AM UTC 25
Finished Feb 09 01:21:41 AM UTC 25
Peak memory 225584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477036896 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2477036896 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_app.820133821
Short name T696
Test name
Test status
Simulation time 13566009562 ps
CPU time 115.15 seconds
Started Feb 09 01:18:36 AM UTC 25
Finished Feb 09 01:20:34 AM UTC 25
Peak memory 294836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820133821 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.820133821 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_burst_write.2722521682
Short name T722
Test name
Test status
Simulation time 21017732185 ps
CPU time 948.3 seconds
Started Feb 09 01:15:56 AM UTC 25
Finished Feb 09 01:31:56 AM UTC 25
Peak memory 260016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722521682 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.2722521682 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_entropy_refresh.3900957029
Short name T698
Test name
Test status
Simulation time 3667645368 ps
CPU time 105.15 seconds
Started Feb 09 01:19:29 AM UTC 25
Finished Feb 09 01:21:17 AM UTC 25
Peak memory 255904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900957029 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.3900957029 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_error.2441380069
Short name T707
Test name
Test status
Simulation time 123924684165 ps
CPU time 237.8 seconds
Started Feb 09 01:20:35 AM UTC 25
Finished Feb 09 01:24:37 AM UTC 25
Peak memory 370592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441380069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 32.kmac_error.2441380069 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_key_error.2687811735
Short name T699
Test name
Test status
Simulation time 2555434875 ps
CPU time 15.64 seconds
Started Feb 09 01:21:04 AM UTC 25
Finished Feb 09 01:21:21 AM UTC 25
Peak memory 227232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687811735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 32.kmac_key_error.2687811735 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_lc_escalation.2549720985
Short name T700
Test name
Test status
Simulation time 455216013 ps
CPU time 18.43 seconds
Started Feb 09 01:21:18 AM UTC 25
Finished Feb 09 01:21:37 AM UTC 25
Peak memory 247856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549720985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2549720985 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_long_msg_and_output.2572738579
Short name T817
Test name
Test status
Simulation time 139780292794 ps
CPU time 2768.5 seconds
Started Feb 09 01:14:58 AM UTC 25
Finished Feb 09 02:01:34 AM UTC 25
Peak memory 3405784 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572738579 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and_output.2572738579 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_sideload.2103407379
Short name T689
Test name
Test status
Simulation time 4214606389 ps
CPU time 39.36 seconds
Started Feb 09 01:15:40 AM UTC 25
Finished Feb 09 01:16:21 AM UTC 25
Peak memory 255956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103407379 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.2103407379 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_smoke.3137672391
Short name T687
Test name
Test status
Simulation time 3616628916 ps
CPU time 80.2 seconds
Started Feb 09 01:14:49 AM UTC 25
Finished Feb 09 01:16:12 AM UTC 25
Peak memory 235480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137672391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 32.kmac_smoke.3137672391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_stress_all.110791159
Short name T702
Test name
Test status
Simulation time 6342131521 ps
CPU time 52.88 seconds
Started Feb 09 01:21:22 AM UTC 25
Finished Feb 09 01:22:16 AM UTC 25
Peak memory 257952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110791159 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.110791159 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_test_vectors_kmac.943376861
Short name T693
Test name
Test status
Simulation time 248407569 ps
CPU time 9 seconds
Started Feb 09 01:18:15 AM UTC 25
Finished Feb 09 01:18:25 AM UTC 25
Peak memory 229432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=943376861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 32.kmac_test_vectors_kmac.943376861 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_test_vectors_kmac_xof.3918444987
Short name T694
Test name
Test status
Simulation time 445059545 ps
CPU time 8.48 seconds
Started Feb 09 01:18:26 AM UTC 25
Finished Feb 09 01:18:36 AM UTC 25
Peak memory 229420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3918444987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 32.kmac_test_vectors_kmac_xof.3918444987 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_test_vectors_sha3_224.211615212
Short name T789
Test name
Test status
Simulation time 21064846992 ps
CPU time 2119.96 seconds
Started Feb 09 01:16:09 AM UTC 25
Finished Feb 09 01:51:52 AM UTC 25
Peak memory 1202072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211615212 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.211615212 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_test_vectors_sha3_256.2127286091
Short name T820
Test name
Test status
Simulation time 259971790550 ps
CPU time 2871.28 seconds
Started Feb 09 01:16:13 AM UTC 25
Finished Feb 09 02:04:36 AM UTC 25
Peak memory 3100512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127286091 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.2127286091 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_test_vectors_sha3_384.3630209854
Short name T780
Test name
Test status
Simulation time 16573662276 ps
CPU time 1914.93 seconds
Started Feb 09 01:16:22 AM UTC 25
Finished Feb 09 01:48:40 AM UTC 25
Peak memory 931676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630209854 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.3630209854 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_test_vectors_sha3_512.3794052446
Short name T760
Test name
Test status
Simulation time 34700983611 ps
CPU time 1510.89 seconds
Started Feb 09 01:16:22 AM UTC 25
Finished Feb 09 01:41:50 AM UTC 25
Peak memory 1750996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794052446 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.3794052446 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_test_vectors_shake_128.3270540737
Short name T1050
Test name
Test status
Simulation time 944335681910 ps
CPU time 8877.73 seconds
Started Feb 09 01:17:04 AM UTC 25
Finished Feb 09 03:46:36 AM UTC 25
Peak memory 7843904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270540737 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3270540737 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/32.kmac_test_vectors_shake_256.3116423756
Short name T1000
Test name
Test status
Simulation time 187241625298 ps
CPU time 6925.54 seconds
Started Feb 09 01:17:50 AM UTC 25
Finished Feb 09 03:14:29 AM UTC 25
Peak memory 6309772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116423756 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.3116423756 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_alert_test.2803136992
Short name T720
Test name
Test status
Simulation time 17790572 ps
CPU time 1.29 seconds
Started Feb 09 01:30:56 AM UTC 25
Finished Feb 09 01:30:58 AM UTC 25
Peak memory 225524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803136992 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2803136992 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_app.958897916
Short name T716
Test name
Test status
Simulation time 9169845665 ps
CPU time 111.98 seconds
Started Feb 09 01:27:59 AM UTC 25
Finished Feb 09 01:29:53 AM UTC 25
Peak memory 255916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958897916 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.958897916 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_burst_write.420672665
Short name T723
Test name
Test status
Simulation time 10727573445 ps
CPU time 543.8 seconds
Started Feb 09 01:23:14 AM UTC 25
Finished Feb 09 01:32:25 AM UTC 25
Peak memory 249828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420672665 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.420672665 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_entropy_refresh.3432104684
Short name T80
Test name
Test status
Simulation time 9979112205 ps
CPU time 278.41 seconds
Started Feb 09 01:28:07 AM UTC 25
Finished Feb 09 01:32:49 AM UTC 25
Peak memory 413660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432104684 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3432104684 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_error.3717891705
Short name T740
Test name
Test status
Simulation time 64281842036 ps
CPU time 524.12 seconds
Started Feb 09 01:28:56 AM UTC 25
Finished Feb 09 01:37:46 AM UTC 25
Peak memory 620512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717891705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 33.kmac_error.3717891705 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_key_error.4164854868
Short name T717
Test name
Test status
Simulation time 2011107723 ps
CPU time 9.47 seconds
Started Feb 09 01:29:54 AM UTC 25
Finished Feb 09 01:30:05 AM UTC 25
Peak memory 229212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164854868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 33.kmac_key_error.4164854868 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_lc_escalation.192419415
Short name T718
Test name
Test status
Simulation time 4314062572 ps
CPU time 30.72 seconds
Started Feb 09 01:30:05 AM UTC 25
Finished Feb 09 01:30:37 AM UTC 25
Peak memory 256236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192419415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.192419415 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_long_msg_and_output.1034924172
Short name T771
Test name
Test status
Simulation time 76285292099 ps
CPU time 1474.34 seconds
Started Feb 09 01:22:17 AM UTC 25
Finished Feb 09 01:47:09 AM UTC 25
Peak memory 1765292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034924172 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_and_output.1034924172 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_sideload.970540070
Short name T713
Test name
Test status
Simulation time 3411190287 ps
CPU time 284.66 seconds
Started Feb 09 01:23:09 AM UTC 25
Finished Feb 09 01:27:57 AM UTC 25
Peak memory 331700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970540070 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.970540070 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_smoke.3333673204
Short name T704
Test name
Test status
Simulation time 5148330264 ps
CPU time 89.94 seconds
Started Feb 09 01:21:41 AM UTC 25
Finished Feb 09 01:23:13 AM UTC 25
Peak memory 235480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333673204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 33.kmac_smoke.3333673204 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_stress_all.23114071
Short name T754
Test name
Test status
Simulation time 50911491962 ps
CPU time 644.58 seconds
Started Feb 09 01:30:39 AM UTC 25
Finished Feb 09 01:41:32 AM UTC 25
Peak memory 419748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23114071 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.23114071 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_test_vectors_kmac.1835940321
Short name T712
Test name
Test status
Simulation time 193337716 ps
CPU time 8.61 seconds
Started Feb 09 01:27:45 AM UTC 25
Finished Feb 09 01:27:55 AM UTC 25
Peak memory 235404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1835940321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.kmac_test_vectors_kmac.1835940321 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_test_vectors_kmac_xof.3263150454
Short name T714
Test name
Test status
Simulation time 441684624 ps
CPU time 8.57 seconds
Started Feb 09 01:27:57 AM UTC 25
Finished Feb 09 01:28:06 AM UTC 25
Peak memory 235336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3263150454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 33.kmac_test_vectors_kmac_xof.3263150454 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_test_vectors_sha3_224.3714220816
Short name T799
Test name
Test status
Simulation time 81641032671 ps
CPU time 1844.9 seconds
Started Feb 09 01:23:56 AM UTC 25
Finished Feb 09 01:55:01 AM UTC 25
Peak memory 1216476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714220816 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.3714220816 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_test_vectors_sha3_256.2256581107
Short name T826
Test name
Test status
Simulation time 108714260935 ps
CPU time 2464.58 seconds
Started Feb 09 01:24:05 AM UTC 25
Finished Feb 09 02:05:36 AM UTC 25
Peak memory 3010360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256581107 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2256581107 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_test_vectors_sha3_384.3517413669
Short name T819
Test name
Test status
Simulation time 71640790553 ps
CPU time 2286.77 seconds
Started Feb 09 01:24:38 AM UTC 25
Finished Feb 09 02:03:09 AM UTC 25
Peak memory 2389980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517413669 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3517413669 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_test_vectors_sha3_512.1195902852
Short name T764
Test name
Test status
Simulation time 32885428785 ps
CPU time 1204.38 seconds
Started Feb 09 01:24:42 AM UTC 25
Finished Feb 09 01:45:00 AM UTC 25
Peak memory 722776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195902852 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.1195902852 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_test_vectors_shake_128.2502858151
Short name T990
Test name
Test status
Simulation time 61143405766 ps
CPU time 6264.98 seconds
Started Feb 09 01:24:59 AM UTC 25
Finished Feb 09 03:10:33 AM UTC 25
Peak memory 2690904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502858151 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.2502858151 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/33.kmac_test_vectors_shake_256.375475361
Short name T920
Test name
Test status
Simulation time 52915797289 ps
CPU time 4591.47 seconds
Started Feb 09 01:26:25 AM UTC 25
Finished Feb 09 02:43:46 AM UTC 25
Peak memory 2287456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375475361 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.375475361 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_alert_test.2825868033
Short name T739
Test name
Test status
Simulation time 91246421 ps
CPU time 1.37 seconds
Started Feb 09 01:37:40 AM UTC 25
Finished Feb 09 01:37:42 AM UTC 25
Peak memory 224624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825868033 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.2825868033 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_app.1131915096
Short name T744
Test name
Test status
Simulation time 19434353934 ps
CPU time 244.73 seconds
Started Feb 09 01:35:44 AM UTC 25
Finished Feb 09 01:39:53 AM UTC 25
Peak memory 403424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131915096 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.1131915096 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_burst_write.1586142270
Short name T725
Test name
Test status
Simulation time 214889339 ps
CPU time 26 seconds
Started Feb 09 01:32:26 AM UTC 25
Finished Feb 09 01:32:53 AM UTC 25
Peak memory 233500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586142270 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1586142270 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_entropy_refresh.3590588516
Short name T747
Test name
Test status
Simulation time 21723678952 ps
CPU time 256.72 seconds
Started Feb 09 01:36:38 AM UTC 25
Finished Feb 09 01:40:58 AM UTC 25
Peak memory 315356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590588516 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.3590588516 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_error.876020245
Short name T773
Test name
Test status
Simulation time 71718749429 ps
CPU time 639.12 seconds
Started Feb 09 01:36:39 AM UTC 25
Finished Feb 09 01:47:27 AM UTC 25
Peak memory 628700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876020245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_er
ror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 34.kmac_error.876020245 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_key_error.2111934092
Short name T736
Test name
Test status
Simulation time 1060609612 ps
CPU time 2.95 seconds
Started Feb 09 01:37:30 AM UTC 25
Finished Feb 09 01:37:35 AM UTC 25
Peak memory 227352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111934092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 34.kmac_key_error.2111934092 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_lc_escalation.859186120
Short name T738
Test name
Test status
Simulation time 56414707 ps
CPU time 2.17 seconds
Started Feb 09 01:37:36 AM UTC 25
Finished Feb 09 01:37:39 AM UTC 25
Peak memory 231464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859186120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.859186120 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_long_msg_and_output.1205857157
Short name T745
Test name
Test status
Simulation time 15261807931 ps
CPU time 521 seconds
Started Feb 09 01:31:49 AM UTC 25
Finished Feb 09 01:40:37 AM UTC 25
Peak memory 450464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205857157 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_and_output.1205857157 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_sideload.2362372644
Short name T751
Test name
Test status
Simulation time 10491449970 ps
CPU time 543.09 seconds
Started Feb 09 01:31:57 AM UTC 25
Finished Feb 09 01:41:07 AM UTC 25
Peak memory 382936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362372644 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2362372644 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_smoke.605219714
Short name T724
Test name
Test status
Simulation time 6368821432 ps
CPU time 105.6 seconds
Started Feb 09 01:30:59 AM UTC 25
Finished Feb 09 01:32:47 AM UTC 25
Peak memory 235616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605219714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 34.kmac_smoke.605219714 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_stress_all.2331700109
Short name T761
Test name
Test status
Simulation time 6981392494 ps
CPU time 250.55 seconds
Started Feb 09 01:37:40 AM UTC 25
Finished Feb 09 01:41:54 AM UTC 25
Peak memory 383328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331700109 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.2331700109 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_test_vectors_kmac.2116572445
Short name T731
Test name
Test status
Simulation time 714849537 ps
CPU time 9.47 seconds
Started Feb 09 01:35:22 AM UTC 25
Finished Feb 09 01:35:33 AM UTC 25
Peak memory 235368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2116572445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 34.kmac_test_vectors_kmac.2116572445 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_test_vectors_kmac_xof.1834931637
Short name T732
Test name
Test status
Simulation time 196957111 ps
CPU time 8.52 seconds
Started Feb 09 01:35:33 AM UTC 25
Finished Feb 09 01:35:43 AM UTC 25
Peak memory 229480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1834931637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 34.kmac_test_vectors_kmac_xof.1834931637 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_test_vectors_sha3_224.4214639402
Short name T835
Test name
Test status
Simulation time 20478187212 ps
CPU time 2316.97 seconds
Started Feb 09 01:32:48 AM UTC 25
Finished Feb 09 02:11:52 AM UTC 25
Peak memory 1216352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214639402 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.4214639402 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_test_vectors_sha3_256.1104642290
Short name T841
Test name
Test status
Simulation time 39406099850 ps
CPU time 2447.86 seconds
Started Feb 09 01:32:50 AM UTC 25
Finished Feb 09 02:14:08 AM UTC 25
Peak memory 1173344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104642290 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.1104642290 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_test_vectors_sha3_384.1789517407
Short name T815
Test name
Test status
Simulation time 67887904627 ps
CPU time 1644.32 seconds
Started Feb 09 01:32:55 AM UTC 25
Finished Feb 09 02:00:37 AM UTC 25
Peak memory 931676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789517407 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.1789517407 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_test_vectors_sha3_512.3240991052
Short name T821
Test name
Test status
Simulation time 551723702733 ps
CPU time 1873 seconds
Started Feb 09 01:33:25 AM UTC 25
Finished Feb 09 02:04:59 AM UTC 25
Peak memory 1757060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240991052 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.3240991052 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_test_vectors_shake_128.2930502600
Short name T1064
Test name
Test status
Simulation time 1362751867010 ps
CPU time 9689.08 seconds
Started Feb 09 01:34:29 AM UTC 25
Finished Feb 09 04:17:41 AM UTC 25
Peak memory 7897148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930502600 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.2930502600 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/34.kmac_test_vectors_shake_256.3137542636
Short name T1041
Test name
Test status
Simulation time 915751459041 ps
CPU time 7272.25 seconds
Started Feb 09 01:34:48 AM UTC 25
Finished Feb 09 03:37:13 AM UTC 25
Peak memory 6424448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137542636 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.3137542636 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_alert_test.67044549
Short name T758
Test name
Test status
Simulation time 11960832 ps
CPU time 1.19 seconds
Started Feb 09 01:41:42 AM UTC 25
Finished Feb 09 01:41:44 AM UTC 25
Peak memory 226232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67044549 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.67044549 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_app.3887753235
Short name T779
Test name
Test status
Simulation time 15078513700 ps
CPU time 436.74 seconds
Started Feb 09 01:41:08 AM UTC 25
Finished Feb 09 01:48:31 AM UTC 25
Peak memory 511972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887753235 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3887753235 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_burst_write.3909319173
Short name T770
Test name
Test status
Simulation time 7773733787 ps
CPU time 471.82 seconds
Started Feb 09 01:38:38 AM UTC 25
Finished Feb 09 01:46:37 AM UTC 25
Peak memory 239592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909319173 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3909319173 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_entropy_refresh.189853893
Short name T767
Test name
Test status
Simulation time 36567808320 ps
CPU time 245.04 seconds
Started Feb 09 01:41:14 AM UTC 25
Finished Feb 09 01:45:23 AM UTC 25
Peak memory 370792 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189853893 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.189853893 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_error.1910991265
Short name T756
Test name
Test status
Simulation time 998557582 ps
CPU time 22.86 seconds
Started Feb 09 01:41:17 AM UTC 25
Finished Feb 09 01:41:41 AM UTC 25
Peak memory 251776 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910991265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 35.kmac_error.1910991265 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_key_error.2348521881
Short name T759
Test name
Test status
Simulation time 2120534965 ps
CPU time 14.76 seconds
Started Feb 09 01:41:33 AM UTC 25
Finished Feb 09 01:41:49 AM UTC 25
Peak memory 227160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348521881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 35.kmac_key_error.2348521881 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_lc_escalation.2054362590
Short name T68
Test name
Test status
Simulation time 360956029 ps
CPU time 1.98 seconds
Started Feb 09 01:41:36 AM UTC 25
Finished Feb 09 01:41:39 AM UTC 25
Peak memory 233000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054362590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2054362590 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_long_msg_and_output.4290919463
Short name T749
Test name
Test status
Simulation time 6105012401 ps
CPU time 192.76 seconds
Started Feb 09 01:37:47 AM UTC 25
Finished Feb 09 01:41:03 AM UTC 25
Peak memory 399396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290919463 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_and_output.4290919463 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_sideload.1406921200
Short name T757
Test name
Test status
Simulation time 12106211544 ps
CPU time 190.36 seconds
Started Feb 09 01:38:30 AM UTC 25
Finished Feb 09 01:41:43 AM UTC 25
Peak memory 401448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406921200 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1406921200 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_smoke.1758104263
Short name T743
Test name
Test status
Simulation time 28305706332 ps
CPU time 94.74 seconds
Started Feb 09 01:37:43 AM UTC 25
Finished Feb 09 01:39:20 AM UTC 25
Peak memory 235400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758104263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 35.kmac_smoke.1758104263 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_stress_all.3107676459
Short name T810
Test name
Test status
Simulation time 14311813260 ps
CPU time 1040.56 seconds
Started Feb 09 01:41:40 AM UTC 25
Finished Feb 09 01:59:12 AM UTC 25
Peak memory 345988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107676459 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3107676459 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_test_vectors_kmac.444948066
Short name T752
Test name
Test status
Simulation time 280047770 ps
CPU time 7.84 seconds
Started Feb 09 01:41:05 AM UTC 25
Finished Feb 09 01:41:14 AM UTC 25
Peak memory 229480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=444948066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 35.kmac_test_vectors_kmac.444948066 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_test_vectors_kmac_xof.1558669477
Short name T753
Test name
Test status
Simulation time 144691550 ps
CPU time 7.67 seconds
Started Feb 09 01:41:07 AM UTC 25
Finished Feb 09 01:41:16 AM UTC 25
Peak memory 229416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1558669477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 35.kmac_test_vectors_kmac_xof.1558669477 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_test_vectors_sha3_224.4127481595
Short name T881
Test name
Test status
Simulation time 166411507245 ps
CPU time 2931.34 seconds
Started Feb 09 01:39:21 AM UTC 25
Finished Feb 09 02:28:44 AM UTC 25
Peak memory 3207120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127481595 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.4127481595 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_test_vectors_sha3_256.2556260792
Short name T839
Test name
Test status
Simulation time 35310394415 ps
CPU time 1998.41 seconds
Started Feb 09 01:39:54 AM UTC 25
Finished Feb 09 02:13:35 AM UTC 25
Peak memory 1161240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556260792 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.2556260792 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_test_vectors_sha3_384.1483884391
Short name T857
Test name
Test status
Simulation time 89041077061 ps
CPU time 2307.69 seconds
Started Feb 09 01:40:38 AM UTC 25
Finished Feb 09 02:19:31 AM UTC 25
Peak memory 2410328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483884391 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.1483884391 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_test_vectors_sha3_512.1350371844
Short name T832
Test name
Test status
Simulation time 43498243717 ps
CPU time 1537.98 seconds
Started Feb 09 01:40:51 AM UTC 25
Finished Feb 09 02:06:46 AM UTC 25
Peak memory 1711960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350371844 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.1350371844 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_test_vectors_shake_128.2742504081
Short name T1058
Test name
Test status
Simulation time 1029101853357 ps
CPU time 8621.6 seconds
Started Feb 09 01:40:59 AM UTC 25
Finished Feb 09 04:06:12 AM UTC 25
Peak memory 7714644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742504081 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.2742504081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/35.kmac_test_vectors_shake_256.3244125136
Short name T1039
Test name
Test status
Simulation time 1868143660697 ps
CPU time 6758.93 seconds
Started Feb 09 01:41:02 AM UTC 25
Finished Feb 09 03:34:51 AM UTC 25
Peak memory 6274892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244125136 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.3244125136 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_alert_test.3274593050
Short name T776
Test name
Test status
Simulation time 17790763 ps
CPU time 1.29 seconds
Started Feb 09 01:47:35 AM UTC 25
Finished Feb 09 01:47:37 AM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274593050 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3274593050 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_app.3611289759
Short name T772
Test name
Test status
Simulation time 2697613846 ps
CPU time 93.15 seconds
Started Feb 09 01:45:45 AM UTC 25
Finished Feb 09 01:47:20 AM UTC 25
Peak memory 254032 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611289759 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3611289759 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_burst_write.2298188611
Short name T783
Test name
Test status
Simulation time 17565065405 ps
CPU time 441.34 seconds
Started Feb 09 01:41:51 AM UTC 25
Finished Feb 09 01:49:18 AM UTC 25
Peak memory 241584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298188611 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2298188611 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_entropy_refresh.3918571064
Short name T793
Test name
Test status
Simulation time 48904588488 ps
CPU time 392.04 seconds
Started Feb 09 01:46:38 AM UTC 25
Finished Feb 09 01:53:15 AM UTC 25
Peak memory 475096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918571064 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3918571064 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_error.3856607123
Short name T802
Test name
Test status
Simulation time 32722161497 ps
CPU time 532.71 seconds
Started Feb 09 01:47:10 AM UTC 25
Finished Feb 09 01:56:10 AM UTC 25
Peak memory 614360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856607123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 36.kmac_error.3856607123 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_key_error.3362751451
Short name T775
Test name
Test status
Simulation time 2285116312 ps
CPU time 11.13 seconds
Started Feb 09 01:47:21 AM UTC 25
Finished Feb 09 01:47:33 AM UTC 25
Peak memory 227232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362751451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 36.kmac_key_error.3362751451 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_lc_escalation.2184369975
Short name T774
Test name
Test status
Simulation time 137719785 ps
CPU time 2.69 seconds
Started Feb 09 01:47:27 AM UTC 25
Finished Feb 09 01:47:31 AM UTC 25
Peak memory 233452 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184369975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.2184369975 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_long_msg_and_output.3216385102
Short name T803
Test name
Test status
Simulation time 29864163232 ps
CPU time 860.78 seconds
Started Feb 09 01:41:45 AM UTC 25
Finished Feb 09 01:56:16 AM UTC 25
Peak memory 653408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216385102 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_and_output.3216385102 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_sideload.755035416
Short name T785
Test name
Test status
Simulation time 18176809745 ps
CPU time 547.42 seconds
Started Feb 09 01:41:50 AM UTC 25
Finished Feb 09 01:51:04 AM UTC 25
Peak memory 641128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755035416 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.755035416 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_smoke.4178444037
Short name T762
Test name
Test status
Simulation time 5312589261 ps
CPU time 93.41 seconds
Started Feb 09 01:41:45 AM UTC 25
Finished Feb 09 01:43:20 AM UTC 25
Peak memory 235396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178444037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 36.kmac_smoke.4178444037 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_stress_all.2225587697
Short name T797
Test name
Test status
Simulation time 12010112512 ps
CPU time 420.22 seconds
Started Feb 09 01:47:33 AM UTC 25
Finished Feb 09 01:54:38 AM UTC 25
Peak memory 686404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225587697 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.2225587697 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_test_vectors_kmac.380446723
Short name T768
Test name
Test status
Simulation time 261907226 ps
CPU time 9.19 seconds
Started Feb 09 01:45:24 AM UTC 25
Finished Feb 09 01:45:34 AM UTC 25
Peak memory 229420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=380446723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 36.kmac_test_vectors_kmac.380446723 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_test_vectors_kmac_xof.928932957
Short name T769
Test name
Test status
Simulation time 733328764 ps
CPU time 8.03 seconds
Started Feb 09 01:45:35 AM UTC 25
Finished Feb 09 01:45:44 AM UTC 25
Peak memory 229448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=928932957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 36.kmac_test_vectors_kmac_xof.928932957 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_test_vectors_sha3_224.3384749975
Short name T894
Test name
Test status
Simulation time 66276581409 ps
CPU time 2964.87 seconds
Started Feb 09 01:41:56 AM UTC 25
Finished Feb 09 02:31:53 AM UTC 25
Peak memory 3295072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384749975 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.3384749975 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_test_vectors_sha3_256.3009283255
Short name T873
Test name
Test status
Simulation time 63750777117 ps
CPU time 2426.74 seconds
Started Feb 09 01:43:22 AM UTC 25
Finished Feb 09 02:24:14 AM UTC 25
Peak memory 3047256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009283255 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.3009283255 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_test_vectors_sha3_384.2198879257
Short name T854
Test name
Test status
Simulation time 48681359091 ps
CPU time 1954.74 seconds
Started Feb 09 01:44:29 AM UTC 25
Finished Feb 09 02:17:25 AM UTC 25
Peak memory 2404192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198879257 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.2198879257 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_test_vectors_sha3_512.3871914653
Short name T829
Test name
Test status
Simulation time 13198594164 ps
CPU time 1250.6 seconds
Started Feb 09 01:45:01 AM UTC 25
Finished Feb 09 02:06:06 AM UTC 25
Peak memory 720788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871914653 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.3871914653 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_test_vectors_shake_128.3268850929
Short name T1009
Test name
Test status
Simulation time 59542899661 ps
CPU time 5444.03 seconds
Started Feb 09 01:45:17 AM UTC 25
Finished Feb 09 03:17:00 AM UTC 25
Peak memory 2703196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268850929 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.3268850929 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/36.kmac_test_vectors_shake_256.1760882555
Short name T1042
Test name
Test status
Simulation time 640235604764 ps
CPU time 6688.43 seconds
Started Feb 09 01:45:24 AM UTC 25
Finished Feb 09 03:38:02 AM UTC 25
Peak memory 6479644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760882555 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.1760882555 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/36.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_alert_test.3223292535
Short name T795
Test name
Test status
Simulation time 29225027 ps
CPU time 1.25 seconds
Started Feb 09 01:53:17 AM UTC 25
Finished Feb 09 01:53:19 AM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223292535 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.3223292535 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_app.1143673897
Short name T791
Test name
Test status
Simulation time 3129575382 ps
CPU time 81.01 seconds
Started Feb 09 01:51:44 AM UTC 25
Finished Feb 09 01:53:07 AM UTC 25
Peak memory 249760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143673897 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1143673897 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_burst_write.234806012
Short name T790
Test name
Test status
Simulation time 8821749964 ps
CPU time 221.22 seconds
Started Feb 09 01:48:32 AM UTC 25
Finished Feb 09 01:52:17 AM UTC 25
Peak memory 237544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234806012 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.234806012 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_entropy_refresh.2398285060
Short name T800
Test name
Test status
Simulation time 82920574087 ps
CPU time 196.32 seconds
Started Feb 09 01:51:54 AM UTC 25
Finished Feb 09 01:55:13 AM UTC 25
Peak memory 274400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398285060 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2398285060 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_error.700223649
Short name T808
Test name
Test status
Simulation time 13135528179 ps
CPU time 381.27 seconds
Started Feb 09 01:52:18 AM UTC 25
Finished Feb 09 01:58:44 AM UTC 25
Peak memory 352212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700223649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_er
ror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 37.kmac_error.700223649 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_key_error.1081946134
Short name T792
Test name
Test status
Simulation time 201445090 ps
CPU time 3.34 seconds
Started Feb 09 01:53:07 AM UTC 25
Finished Feb 09 01:53:12 AM UTC 25
Peak memory 227224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081946134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 37.kmac_key_error.1081946134 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_lc_escalation.3906148296
Short name T794
Test name
Test status
Simulation time 161689933 ps
CPU time 2.2 seconds
Started Feb 09 01:53:13 AM UTC 25
Finished Feb 09 01:53:16 AM UTC 25
Peak memory 233588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906148296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3906148296 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_long_msg_and_output.4068460307
Short name T824
Test name
Test status
Simulation time 556617901615 ps
CPU time 1042.47 seconds
Started Feb 09 01:47:41 AM UTC 25
Finished Feb 09 02:05:17 AM UTC 25
Peak memory 1206140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068460307 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_and_output.4068460307 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_sideload.172516552
Short name T781
Test name
Test status
Simulation time 2091729515 ps
CPU time 36.61 seconds
Started Feb 09 01:48:13 AM UTC 25
Finished Feb 09 01:48:51 AM UTC 25
Peak memory 249840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172516552 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.172516552 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_smoke.745052511
Short name T782
Test name
Test status
Simulation time 11006664208 ps
CPU time 89.21 seconds
Started Feb 09 01:47:38 AM UTC 25
Finished Feb 09 01:49:09 AM UTC 25
Peak memory 234684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745052511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 37.kmac_smoke.745052511 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_stress_all.3833940820
Short name T867
Test name
Test status
Simulation time 55058620018 ps
CPU time 1766.4 seconds
Started Feb 09 01:53:17 AM UTC 25
Finished Feb 09 02:23:03 AM UTC 25
Peak memory 1382780 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833940820 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.3833940820 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_test_vectors_kmac.1241804606
Short name T787
Test name
Test status
Simulation time 86076407 ps
CPU time 7.09 seconds
Started Feb 09 01:51:24 AM UTC 25
Finished Feb 09 01:51:32 AM UTC 25
Peak memory 235400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1241804606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 37.kmac_test_vectors_kmac.1241804606 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_test_vectors_kmac_xof.2215788648
Short name T788
Test name
Test status
Simulation time 198663476 ps
CPU time 8.16 seconds
Started Feb 09 01:51:33 AM UTC 25
Finished Feb 09 01:51:43 AM UTC 25
Peak memory 235496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2215788648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 37.kmac_test_vectors_kmac_xof.2215788648 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_test_vectors_sha3_224.1671552045
Short name T902
Test name
Test status
Simulation time 137717452659 ps
CPU time 2914.42 seconds
Started Feb 09 01:48:41 AM UTC 25
Finished Feb 09 02:37:48 AM UTC 25
Peak memory 3245960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671552045 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1671552045 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_test_vectors_sha3_256.1661567512
Short name T907
Test name
Test status
Simulation time 893682159006 ps
CPU time 2958.61 seconds
Started Feb 09 01:48:51 AM UTC 25
Finished Feb 09 02:38:43 AM UTC 25
Peak memory 3100512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661567512 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.1661567512 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_test_vectors_sha3_384.3136366926
Short name T851
Test name
Test status
Simulation time 59635589477 ps
CPU time 1669.64 seconds
Started Feb 09 01:49:11 AM UTC 25
Finished Feb 09 02:17:19 AM UTC 25
Peak memory 931680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136366926 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.3136366926 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_test_vectors_sha3_512.2699559162
Short name T852
Test name
Test status
Simulation time 132132600534 ps
CPU time 1661.59 seconds
Started Feb 09 01:49:19 AM UTC 25
Finished Feb 09 02:17:20 AM UTC 25
Peak memory 1726300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699559162 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.2699559162 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/37.kmac_test_vectors_shake_256.1616466657
Short name T987
Test name
Test status
Simulation time 360208087761 ps
CPU time 4627.66 seconds
Started Feb 09 01:51:06 AM UTC 25
Finished Feb 09 03:09:04 AM UTC 25
Peak memory 2181000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616466657 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.1616466657 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_alert_test.237071717
Short name T814
Test name
Test status
Simulation time 13067650 ps
CPU time 1.26 seconds
Started Feb 09 02:00:25 AM UTC 25
Finished Feb 09 02:00:28 AM UTC 25
Peak memory 225708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237071717 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.237071717 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_app.1700037245
Short name T809
Test name
Test status
Simulation time 1147643375 ps
CPU time 82.17 seconds
Started Feb 09 01:57:39 AM UTC 25
Finished Feb 09 01:59:04 AM UTC 25
Peak memory 253936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700037245 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1700037245 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_burst_write.1432927614
Short name T860
Test name
Test status
Simulation time 120377997236 ps
CPU time 1520.19 seconds
Started Feb 09 01:54:42 AM UTC 25
Finished Feb 09 02:20:20 AM UTC 25
Peak memory 255920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432927614 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.1432927614 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_entropy_refresh.2882257709
Short name T813
Test name
Test status
Simulation time 13605013877 ps
CPU time 95.48 seconds
Started Feb 09 01:58:46 AM UTC 25
Finished Feb 09 02:00:24 AM UTC 25
Peak memory 296860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882257709 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2882257709 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_error.1176201208
Short name T822
Test name
Test status
Simulation time 17550745044 ps
CPU time 359.09 seconds
Started Feb 09 01:59:05 AM UTC 25
Finished Feb 09 02:05:09 AM UTC 25
Peak memory 354216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176201208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 38.kmac_error.1176201208 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_key_error.565620187
Short name T811
Test name
Test status
Simulation time 2482728010 ps
CPU time 9.35 seconds
Started Feb 09 01:59:13 AM UTC 25
Finished Feb 09 01:59:24 AM UTC 25
Peak memory 227284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565620187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ke
y_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.kmac_key_error.565620187 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_lc_escalation.2967826321
Short name T812
Test name
Test status
Simulation time 111173666 ps
CPU time 2.1 seconds
Started Feb 09 01:59:25 AM UTC 25
Finished Feb 09 01:59:28 AM UTC 25
Peak memory 233644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967826321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2967826321 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_long_msg_and_output.3448168452
Short name T880
Test name
Test status
Simulation time 15418845748 ps
CPU time 2013.19 seconds
Started Feb 09 01:54:27 AM UTC 25
Finished Feb 09 02:28:23 AM UTC 25
Peak memory 1136560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448168452 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_and_output.3448168452 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_sideload.3189238723
Short name T801
Test name
Test status
Simulation time 3743748262 ps
CPU time 75.35 seconds
Started Feb 09 01:54:39 AM UTC 25
Finished Feb 09 01:55:56 AM UTC 25
Peak memory 295076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189238723 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3189238723 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_smoke.2700916644
Short name T796
Test name
Test status
Simulation time 7734245171 ps
CPU time 63.13 seconds
Started Feb 09 01:53:20 AM UTC 25
Finished Feb 09 01:54:26 AM UTC 25
Peak memory 233636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700916644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 38.kmac_smoke.2700916644 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_stress_all.2385065632
Short name T877
Test name
Test status
Simulation time 50023317948 ps
CPU time 1563.6 seconds
Started Feb 09 01:59:29 AM UTC 25
Finished Feb 09 02:25:51 AM UTC 25
Peak memory 1322960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385065632 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.2385065632 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_test_vectors_kmac.3673730025
Short name T806
Test name
Test status
Simulation time 110879881 ps
CPU time 7.59 seconds
Started Feb 09 01:57:20 AM UTC 25
Finished Feb 09 01:57:29 AM UTC 25
Peak memory 227380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3673730025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 38.kmac_test_vectors_kmac.3673730025 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_test_vectors_kmac_xof.1404407491
Short name T807
Test name
Test status
Simulation time 98721108 ps
CPU time 7.54 seconds
Started Feb 09 01:57:30 AM UTC 25
Finished Feb 09 01:57:39 AM UTC 25
Peak memory 229552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1404407491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 38.kmac_test_vectors_kmac_xof.1404407491 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_test_vectors_sha3_224.323670267
Short name T936
Test name
Test status
Simulation time 273633019399 ps
CPU time 3217.43 seconds
Started Feb 09 01:55:02 AM UTC 25
Finished Feb 09 02:49:17 AM UTC 25
Peak memory 3163988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323670267 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.323670267 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_test_vectors_sha3_256.189292428
Short name T929
Test name
Test status
Simulation time 245696744429 ps
CPU time 2995.85 seconds
Started Feb 09 01:55:15 AM UTC 25
Finished Feb 09 02:45:44 AM UTC 25
Peak memory 3057560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189292428 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.189292428 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_test_vectors_sha3_384.1498749459
Short name T895
Test name
Test status
Simulation time 53290643334 ps
CPU time 2151.46 seconds
Started Feb 09 01:55:57 AM UTC 25
Finished Feb 09 02:32:13 AM UTC 25
Peak memory 2400216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498749459 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.1498749459 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_test_vectors_sha3_512.2209469602
Short name T876
Test name
Test status
Simulation time 276922236237 ps
CPU time 1729.74 seconds
Started Feb 09 01:56:11 AM UTC 25
Finished Feb 09 02:25:20 AM UTC 25
Peak memory 1754968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209469602 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.2209469602 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_test_vectors_shake_128.3852211572
Short name T1023
Test name
Test status
Simulation time 59882469304 ps
CPU time 5229.08 seconds
Started Feb 09 01:56:17 AM UTC 25
Finished Feb 09 03:24:22 AM UTC 25
Peak memory 2695060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852211572 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3852211572 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/38.kmac_test_vectors_shake_256.3818711401
Short name T1052
Test name
Test status
Simulation time 237226753783 ps
CPU time 7202.58 seconds
Started Feb 09 01:56:34 AM UTC 25
Finished Feb 09 03:57:52 AM UTC 25
Peak memory 6367248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818711401 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.3818711401 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_alert_test.3739458116
Short name T833
Test name
Test status
Simulation time 24168085 ps
CPU time 1.31 seconds
Started Feb 09 02:06:48 AM UTC 25
Finished Feb 09 02:06:50 AM UTC 25
Peak memory 225524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739458116 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3739458116 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_app.456429655
Short name T828
Test name
Test status
Simulation time 431448467 ps
CPU time 24.44 seconds
Started Feb 09 02:05:37 AM UTC 25
Finished Feb 09 02:06:03 AM UTC 25
Peak memory 243876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456429655 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.456429655 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_burst_write.795897173
Short name T836
Test name
Test status
Simulation time 23219447251 ps
CPU time 628.07 seconds
Started Feb 09 02:01:35 AM UTC 25
Finished Feb 09 02:12:11 AM UTC 25
Peak memory 243604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795897173 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.795897173 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_entropy_refresh.4289518726
Short name T843
Test name
Test status
Simulation time 59612474695 ps
CPU time 514.88 seconds
Started Feb 09 02:05:40 AM UTC 25
Finished Feb 09 02:14:22 AM UTC 25
Peak memory 518024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289518726 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.4289518726 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_error.3126696069
Short name T840
Test name
Test status
Simulation time 4510966760 ps
CPU time 470.7 seconds
Started Feb 09 02:06:04 AM UTC 25
Finished Feb 09 02:14:01 AM UTC 25
Peak memory 366500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126696069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 39.kmac_error.3126696069 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_key_error.1496332547
Short name T830
Test name
Test status
Simulation time 162385009 ps
CPU time 2.78 seconds
Started Feb 09 02:06:07 AM UTC 25
Finished Feb 09 02:06:11 AM UTC 25
Peak memory 227080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496332547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 39.kmac_key_error.1496332547 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_lc_escalation.2739874310
Short name T831
Test name
Test status
Simulation time 69386341 ps
CPU time 1.87 seconds
Started Feb 09 02:06:12 AM UTC 25
Finished Feb 09 02:06:15 AM UTC 25
Peak memory 231020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739874310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.2739874310 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_long_msg_and_output.3990692822
Short name T838
Test name
Test status
Simulation time 24705713284 ps
CPU time 713.13 seconds
Started Feb 09 02:00:38 AM UTC 25
Finished Feb 09 02:12:39 AM UTC 25
Peak memory 1140704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990692822 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_and_output.3990692822 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_sideload.1168651895
Short name T823
Test name
Test status
Simulation time 7600915924 ps
CPU time 236.99 seconds
Started Feb 09 02:01:12 AM UTC 25
Finished Feb 09 02:05:13 AM UTC 25
Peak memory 438244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168651895 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1168651895 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_smoke.3491255778
Short name T818
Test name
Test status
Simulation time 4209242188 ps
CPU time 108.94 seconds
Started Feb 09 02:00:29 AM UTC 25
Finished Feb 09 02:02:20 AM UTC 25
Peak memory 237660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491255778 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 39.kmac_smoke.3491255778 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_stress_all.3251568802
Short name T859
Test name
Test status
Simulation time 109167905563 ps
CPU time 813.59 seconds
Started Feb 09 02:06:16 AM UTC 25
Finished Feb 09 02:19:59 AM UTC 25
Peak memory 557020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251568802 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3251568802 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_test_vectors_kmac.1705975712
Short name T825
Test name
Test status
Simulation time 831328889 ps
CPU time 9.33 seconds
Started Feb 09 02:05:18 AM UTC 25
Finished Feb 09 02:05:28 AM UTC 25
Peak memory 235500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1705975712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.kmac_test_vectors_kmac.1705975712 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_test_vectors_kmac_xof.1387898163
Short name T827
Test name
Test status
Simulation time 248454700 ps
CPU time 8.91 seconds
Started Feb 09 02:05:29 AM UTC 25
Finished Feb 09 02:05:39 AM UTC 25
Peak memory 235364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1387898163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 39.kmac_test_vectors_kmac_xof.1387898163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_test_vectors_sha3_224.484002427
Short name T904
Test name
Test status
Simulation time 20383626187 ps
CPU time 2125.33 seconds
Started Feb 09 02:02:21 AM UTC 25
Finished Feb 09 02:38:10 AM UTC 25
Peak memory 1204248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484002427 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.484002427 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_test_vectors_sha3_256.1300918385
Short name T922
Test name
Test status
Simulation time 187098794974 ps
CPU time 2424.6 seconds
Started Feb 09 02:03:10 AM UTC 25
Finished Feb 09 02:44:00 AM UTC 25
Peak memory 3065672 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300918385 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.1300918385 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_test_vectors_sha3_384.939241465
Short name T915
Test name
Test status
Simulation time 76927428506 ps
CPU time 2228.74 seconds
Started Feb 09 02:04:53 AM UTC 25
Finished Feb 09 02:42:24 AM UTC 25
Peak memory 2504600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939241465 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.939241465 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_test_vectors_sha3_512.3930744646
Short name T893
Test name
Test status
Simulation time 56544350731 ps
CPU time 1569.5 seconds
Started Feb 09 02:05:00 AM UTC 25
Finished Feb 09 02:31:26 AM UTC 25
Peak memory 1757128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930744646 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.3930744646 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_test_vectors_shake_128.2085887586
Short name T1062
Test name
Test status
Simulation time 744473584245 ps
CPU time 7724.07 seconds
Started Feb 09 02:05:10 AM UTC 25
Finished Feb 09 04:15:10 AM UTC 25
Peak memory 7919448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085887586 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.2085887586 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/39.kmac_test_vectors_shake_256.1531405212
Short name T1040
Test name
Test status
Simulation time 52766526435 ps
CPU time 5365.29 seconds
Started Feb 09 02:05:14 AM UTC 25
Finished Feb 09 03:35:39 AM UTC 25
Peak memory 2221952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531405212 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1531405212 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/39.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_alert_test.4285341463
Short name T206
Test name
Test status
Simulation time 80433019 ps
CPU time 1.22 seconds
Started Feb 08 09:52:40 PM UTC 25
Finished Feb 08 09:52:42 PM UTC 25
Peak memory 225948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285341463 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.4285341463 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_app.3338676704
Short name T134
Test name
Test status
Simulation time 43337946858 ps
CPU time 401.46 seconds
Started Feb 08 09:48:25 PM UTC 25
Finished Feb 08 09:55:12 PM UTC 25
Peak memory 477108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338676704 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3338676704 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_app_with_partial_data.1195379332
Short name T205
Test name
Test status
Simulation time 83885603042 ps
CPU time 209.14 seconds
Started Feb 08 09:48:28 PM UTC 25
Finished Feb 08 09:52:01 PM UTC 25
Peak memory 321508 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195379332 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.1195379332 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_burst_write.223244141
Short name T150
Test name
Test status
Simulation time 1537054872 ps
CPU time 163.15 seconds
Started Feb 08 09:45:29 PM UTC 25
Finished Feb 08 09:48:15 PM UTC 25
Peak memory 235420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223244141 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.223244141 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_edn_timeout_error.3836769689
Short name T204
Test name
Test status
Simulation time 1893210026 ps
CPU time 59.96 seconds
Started Feb 08 09:50:03 PM UTC 25
Finished Feb 08 09:51:05 PM UTC 25
Peak memory 245360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836769689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3836769689 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_mode_error.1775791932
Short name T78
Test name
Test status
Simulation time 24737799 ps
CPU time 1.62 seconds
Started Feb 08 09:50:36 PM UTC 25
Finished Feb 08 09:50:39 PM UTC 25
Peak memory 227180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775791932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.1775791932 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_ready_error.3827898791
Short name T171
Test name
Test status
Simulation time 6920037541 ps
CPU time 98.21 seconds
Started Feb 08 09:50:40 PM UTC 25
Finished Feb 08 09:52:20 PM UTC 25
Peak memory 233640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827898791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
ntropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3827898791 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_entropy_refresh.3538097153
Short name T71
Test name
Test status
Simulation time 21578294696 ps
CPU time 344.63 seconds
Started Feb 08 09:49:22 PM UTC 25
Finished Feb 08 09:55:11 PM UTC 25
Peak memory 419808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538097153 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3538097153 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_error.891001237
Short name T44
Test name
Test status
Simulation time 25377567491 ps
CPU time 195.74 seconds
Started Feb 08 09:49:52 PM UTC 25
Finished Feb 08 09:53:11 PM UTC 25
Peak memory 384988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891001237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_er
ror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 4.kmac_error.891001237 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_key_error.79118208
Short name T114
Test name
Test status
Simulation time 715442131 ps
CPU time 8.62 seconds
Started Feb 08 09:49:53 PM UTC 25
Finished Feb 08 09:50:03 PM UTC 25
Peak memory 227216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79118208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key
_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.kmac_key_error.79118208 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_lc_escalation.3697066747
Short name T36
Test name
Test status
Simulation time 93149077 ps
CPU time 2.29 seconds
Started Feb 08 09:51:06 PM UTC 25
Finished Feb 08 09:51:09 PM UTC 25
Peak memory 233512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697066747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3697066747 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_long_msg_and_output.1425930898
Short name T320
Test name
Test status
Simulation time 28009391090 ps
CPU time 3368.24 seconds
Started Feb 08 09:44:33 PM UTC 25
Finished Feb 08 10:41:18 PM UTC 25
Peak memory 1908632 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425930898 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.1425930898 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_mubi.3626406163
Short name T60
Test name
Test status
Simulation time 6066216293 ps
CPU time 494.52 seconds
Started Feb 08 09:49:34 PM UTC 25
Finished Feb 08 09:57:56 PM UTC 25
Peak memory 346412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626406163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_m
ubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 4.kmac_mubi.3626406163 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_sec_cm.2438581906
Short name T115
Test name
Test status
Simulation time 8226968216 ps
CPU time 139.13 seconds
Started Feb 08 09:52:21 PM UTC 25
Finished Feb 08 09:54:43 PM UTC 25
Peak memory 318700 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438581906 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2438581906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_sideload.469376895
Short name T201
Test name
Test status
Simulation time 8493053397 ps
CPU time 175.81 seconds
Started Feb 08 09:45:00 PM UTC 25
Finished Feb 08 09:47:58 PM UTC 25
Peak memory 331740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469376895 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.469376895 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_smoke.961910369
Short name T200
Test name
Test status
Simulation time 709340680 ps
CPU time 13.85 seconds
Started Feb 08 09:44:17 PM UTC 25
Finished Feb 08 09:44:32 PM UTC 25
Peak memory 235360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961910369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 4.kmac_smoke.961910369 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_stress_all.2391368804
Short name T62
Test name
Test status
Simulation time 69557821701 ps
CPU time 715.32 seconds
Started Feb 08 09:51:10 PM UTC 25
Finished Feb 08 10:03:14 PM UTC 25
Peak memory 436500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391368804 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.2391368804 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac.254130642
Short name T202
Test name
Test status
Simulation time 130342580 ps
CPU time 7.53 seconds
Started Feb 08 09:48:15 PM UTC 25
Finished Feb 08 09:48:24 PM UTC 25
Peak memory 235588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=254130642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 4.kmac_test_vectors_kmac.254130642 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_kmac_xof.1081202181
Short name T203
Test name
Test status
Simulation time 107263114 ps
CPU time 8.05 seconds
Started Feb 08 09:48:18 PM UTC 25
Finished Feb 08 09:48:27 PM UTC 25
Peak memory 235392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1081202181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 4.kmac_test_vectors_kmac_xof.1081202181 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_224.2730538074
Short name T329
Test name
Test status
Simulation time 97844670323 ps
CPU time 3466 seconds
Started Feb 08 09:46:05 PM UTC 25
Finished Feb 08 10:44:30 PM UTC 25
Peak memory 3260504 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730538074 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2730538074 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_256.1447180690
Short name T305
Test name
Test status
Simulation time 76747979166 ps
CPU time 2858.93 seconds
Started Feb 08 09:46:46 PM UTC 25
Finished Feb 08 10:34:57 PM UTC 25
Peak memory 3061652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447180690 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1447180690 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_384.3345799496
Short name T251
Test name
Test status
Simulation time 15226071285 ps
CPU time 1692.33 seconds
Started Feb 08 09:46:49 PM UTC 25
Finished Feb 08 10:15:21 PM UTC 25
Peak memory 925520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345799496 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.3345799496 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_sha3_512.296439942
Short name T228
Test name
Test status
Simulation time 42254481684 ps
CPU time 1129.14 seconds
Started Feb 08 09:47:13 PM UTC 25
Finished Feb 08 10:06:15 PM UTC 25
Peak memory 722768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296439942 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.296439942 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_128.1292742480
Short name T404
Test name
Test status
Simulation time 254950504530 ps
CPU time 5516.33 seconds
Started Feb 08 09:47:56 PM UTC 25
Finished Feb 08 11:20:50 PM UTC 25
Peak memory 2756564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292742480 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1292742480 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/4.kmac_test_vectors_shake_256.2965044078
Short name T465
Test name
Test status
Simulation time 155098123069 ps
CPU time 6950.57 seconds
Started Feb 08 09:47:59 PM UTC 25
Finished Feb 08 11:45:04 PM UTC 25
Peak memory 6387548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965044078 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2965044078 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_alert_test.860499535
Short name T853
Test name
Test status
Simulation time 55565838 ps
CPU time 1.29 seconds
Started Feb 09 02:17:20 AM UTC 25
Finished Feb 09 02:17:23 AM UTC 25
Peak memory 225648 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860499535 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.860499535 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_app.575521401
Short name T862
Test name
Test status
Simulation time 21624986321 ps
CPU time 414.73 seconds
Started Feb 09 02:14:34 AM UTC 25
Finished Feb 09 02:21:34 AM UTC 25
Peak memory 335840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575521401 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.575521401 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_burst_write.1805215906
Short name T879
Test name
Test status
Simulation time 30879826873 ps
CPU time 872.21 seconds
Started Feb 09 02:12:12 AM UTC 25
Finished Feb 09 02:26:55 AM UTC 25
Peak memory 247728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805215906 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.1805215906 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_entropy_refresh.3659301180
Short name T863
Test name
Test status
Simulation time 29170152283 ps
CPU time 420.16 seconds
Started Feb 09 02:14:39 AM UTC 25
Finished Feb 09 02:21:45 AM UTC 25
Peak memory 497572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659301180 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.3659301180 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_error.2583631025
Short name T861
Test name
Test status
Simulation time 21377387884 ps
CPU time 398.09 seconds
Started Feb 09 02:14:42 AM UTC 25
Finished Feb 09 02:21:25 AM UTC 25
Peak memory 378848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583631025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 40.kmac_error.2583631025 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_key_error.413668998
Short name T849
Test name
Test status
Simulation time 1357208231 ps
CPU time 17.78 seconds
Started Feb 09 02:15:48 AM UTC 25
Finished Feb 09 02:16:07 AM UTC 25
Peak memory 229272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413668998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ke
y_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.kmac_key_error.413668998 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_lc_escalation.4240933655
Short name T850
Test name
Test status
Simulation time 204263553 ps
CPU time 2.73 seconds
Started Feb 09 02:16:09 AM UTC 25
Finished Feb 09 02:16:13 AM UTC 25
Peak memory 233512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240933655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.4240933655 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_long_msg_and_output.2741752794
Short name T954
Test name
Test status
Simulation time 91425548459 ps
CPU time 3122.32 seconds
Started Feb 09 02:07:14 AM UTC 25
Finished Feb 09 02:59:53 AM UTC 25
Peak memory 1622108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741752794 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_and_output.2741752794 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_sideload.3636046268
Short name T855
Test name
Test status
Simulation time 11230500415 ps
CPU time 349.82 seconds
Started Feb 09 02:11:53 AM UTC 25
Finished Feb 09 02:17:48 AM UTC 25
Peak memory 464936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636046268 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3636046268 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_smoke.2364116081
Short name T834
Test name
Test status
Simulation time 2549370844 ps
CPU time 20.81 seconds
Started Feb 09 02:06:51 AM UTC 25
Finished Feb 09 02:07:13 AM UTC 25
Peak memory 235424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364116081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 40.kmac_smoke.2364116081 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_stress_all.3134181333
Short name T856
Test name
Test status
Simulation time 10326818493 ps
CPU time 136.64 seconds
Started Feb 09 02:16:14 AM UTC 25
Finished Feb 09 02:18:33 AM UTC 25
Peak memory 301480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134181333 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.3134181333 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_kmac.710803532
Short name T845
Test name
Test status
Simulation time 2228372979 ps
CPU time 8.53 seconds
Started Feb 09 02:14:23 AM UTC 25
Finished Feb 09 02:14:33 AM UTC 25
Peak memory 235468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=710803532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 40.kmac_test_vectors_kmac.710803532 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_kmac_xof.738220253
Short name T847
Test name
Test status
Simulation time 818937920 ps
CPU time 7.77 seconds
Started Feb 09 02:14:32 AM UTC 25
Finished Feb 09 02:14:41 AM UTC 25
Peak memory 235472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=738220253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 40.kmac_test_vectors_kmac_xof.738220253 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_sha3_224.2796174334
Short name T950
Test name
Test status
Simulation time 132137894102 ps
CPU time 2611.53 seconds
Started Feb 09 02:12:33 AM UTC 25
Finished Feb 09 02:56:33 AM UTC 25
Peak memory 3161992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796174334 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.2796174334 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_sha3_256.4082909186
Short name T979
Test name
Test status
Simulation time 196261511517 ps
CPU time 3285.23 seconds
Started Feb 09 02:12:41 AM UTC 25
Finished Feb 09 03:08:02 AM UTC 25
Peak memory 3086296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082909186 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.4082909186 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_sha3_384.1362472990
Short name T918
Test name
Test status
Simulation time 49442673849 ps
CPU time 1772.98 seconds
Started Feb 09 02:13:36 AM UTC 25
Finished Feb 09 02:43:29 AM UTC 25
Peak memory 2389840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362472990 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.1362472990 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_sha3_512.2720427610
Short name T913
Test name
Test status
Simulation time 258127126723 ps
CPU time 1578.85 seconds
Started Feb 09 02:14:02 AM UTC 25
Finished Feb 09 02:40:40 AM UTC 25
Peak memory 1740640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720427610 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.2720427610 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_shake_128.3871791259
Short name T1067
Test name
Test status
Simulation time 737156588121 ps
CPU time 7786.51 seconds
Started Feb 09 02:14:09 AM UTC 25
Finished Feb 09 04:25:15 AM UTC 25
Peak memory 7823184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871791259 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.3871791259 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/40.kmac_test_vectors_shake_256.1081607567
Short name T1069
Test name
Test status
Simulation time 854311751926 ps
CPU time 7956.01 seconds
Started Feb 09 02:14:19 AM UTC 25
Finished Feb 09 04:28:20 AM UTC 25
Peak memory 6260572 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081607567 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.1081607567 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_alert_test.1129474689
Short name T871
Test name
Test status
Simulation time 22473896 ps
CPU time 0.97 seconds
Started Feb 09 02:23:27 AM UTC 25
Finished Feb 09 02:23:29 AM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129474689 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.1129474689 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_app.562730900
Short name T878
Test name
Test status
Simulation time 52909244506 ps
CPU time 256.61 seconds
Started Feb 09 02:21:46 AM UTC 25
Finished Feb 09 02:26:07 AM UTC 25
Peak memory 374708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562730900 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.562730900 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_burst_write.3976743366
Short name T872
Test name
Test status
Simulation time 5397067908 ps
CPU time 366.38 seconds
Started Feb 09 02:17:49 AM UTC 25
Finished Feb 09 02:24:01 AM UTC 25
Peak memory 239540 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976743366 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3976743366 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_entropy_refresh.881930668
Short name T883
Test name
Test status
Simulation time 75157358755 ps
CPU time 418.51 seconds
Started Feb 09 02:21:52 AM UTC 25
Finished Feb 09 02:28:56 AM UTC 25
Peak memory 505900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881930668 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.881930668 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_error.1748356121
Short name T869
Test name
Test status
Simulation time 4613034438 ps
CPU time 86.33 seconds
Started Feb 09 02:21:56 AM UTC 25
Finished Feb 09 02:23:24 AM UTC 25
Peak memory 278428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748356121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.kmac_error.1748356121 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_key_error.4081354032
Short name T868
Test name
Test status
Simulation time 5009172325 ps
CPU time 16.47 seconds
Started Feb 09 02:23:04 AM UTC 25
Finished Feb 09 02:23:22 AM UTC 25
Peak memory 227208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081354032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 41.kmac_key_error.4081354032 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_lc_escalation.1915607797
Short name T870
Test name
Test status
Simulation time 72489005 ps
CPU time 1.86 seconds
Started Feb 09 02:23:23 AM UTC 25
Finished Feb 09 02:23:26 AM UTC 25
Peak memory 230960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915607797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1915607797 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_long_msg_and_output.569830759
Short name T910
Test name
Test status
Simulation time 12194132654 ps
CPU time 1286.93 seconds
Started Feb 09 02:17:24 AM UTC 25
Finished Feb 09 02:39:05 AM UTC 25
Peak memory 944100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569830759 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and_output.569830759 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_sideload.4225693838
Short name T865
Test name
Test status
Simulation time 9908679441 ps
CPU time 260.34 seconds
Started Feb 09 02:17:26 AM UTC 25
Finished Feb 09 02:21:50 AM UTC 25
Peak memory 298980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225693838 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.4225693838 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_smoke.3209854068
Short name T858
Test name
Test status
Simulation time 14991698080 ps
CPU time 131.62 seconds
Started Feb 09 02:17:21 AM UTC 25
Finished Feb 09 02:19:36 AM UTC 25
Peak memory 235424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209854068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.kmac_smoke.3209854068 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_stress_all.4032685609
Short name T889
Test name
Test status
Simulation time 12349236971 ps
CPU time 385.14 seconds
Started Feb 09 02:23:25 AM UTC 25
Finished Feb 09 02:29:56 AM UTC 25
Peak memory 274884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032685609 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.4032685609 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_kmac.2745764323
Short name T864
Test name
Test status
Simulation time 193856434 ps
CPU time 8.22 seconds
Started Feb 09 02:21:36 AM UTC 25
Finished Feb 09 02:21:45 AM UTC 25
Peak memory 235368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2745764323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 41.kmac_test_vectors_kmac.2745764323 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_kmac_xof.1111674640
Short name T866
Test name
Test status
Simulation time 210932985 ps
CPU time 7.65 seconds
Started Feb 09 02:21:46 AM UTC 25
Finished Feb 09 02:21:55 AM UTC 25
Peak memory 235592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1111674640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 41.kmac_test_vectors_kmac_xof.1111674640 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_sha3_224.1335668573
Short name T955
Test name
Test status
Simulation time 21505111544 ps
CPU time 2498.22 seconds
Started Feb 09 02:18:35 AM UTC 25
Finished Feb 09 03:00:42 AM UTC 25
Peak memory 1234968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335668573 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.1335668573 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_sha3_256.1048886003
Short name T971
Test name
Test status
Simulation time 118775133697 ps
CPU time 2815.62 seconds
Started Feb 09 02:19:32 AM UTC 25
Finished Feb 09 03:07:01 AM UTC 25
Peak memory 3063636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048886003 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1048886003 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_sha3_384.2552488658
Short name T931
Test name
Test status
Simulation time 15097000277 ps
CPU time 1571.14 seconds
Started Feb 09 02:19:36 AM UTC 25
Finished Feb 09 02:46:05 AM UTC 25
Peak memory 923488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552488658 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.2552488658 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_sha3_512.3991195555
Short name T911
Test name
Test status
Simulation time 11028630341 ps
CPU time 1158.69 seconds
Started Feb 09 02:20:01 AM UTC 25
Finished Feb 09 02:39:33 AM UTC 25
Peak memory 712520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991195555 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3991195555 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_shake_128.4021234040
Short name T1071
Test name
Test status
Simulation time 699714679313 ps
CPU time 7700.84 seconds
Started Feb 09 02:20:21 AM UTC 25
Finished Feb 09 04:30:00 AM UTC 25
Peak memory 7763804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021234040 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.4021234040 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/41.kmac_test_vectors_shake_256.983296734
Short name T1068
Test name
Test status
Simulation time 226695575463 ps
CPU time 7385.55 seconds
Started Feb 09 02:21:26 AM UTC 25
Finished Feb 09 04:25:49 AM UTC 25
Peak memory 6365068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983296734 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.983296734 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/41.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_alert_test.1290682597
Short name T890
Test name
Test status
Simulation time 45382090 ps
CPU time 1.19 seconds
Started Feb 09 02:29:57 AM UTC 25
Finished Feb 09 02:29:59 AM UTC 25
Peak memory 226232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290682597 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1290682597 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_app.4226148825
Short name T730
Test name
Test status
Simulation time 24505448998 ps
CPU time 182.63 seconds
Started Feb 09 02:28:56 AM UTC 25
Finished Feb 09 02:32:02 AM UTC 25
Peak memory 325668 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226148825 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.4226148825 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_burst_write.3808820536
Short name T897
Test name
Test status
Simulation time 4008441357 ps
CPU time 510.97 seconds
Started Feb 09 02:24:21 AM UTC 25
Finished Feb 09 02:32:59 AM UTC 25
Peak memory 241768 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808820536 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.3808820536 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_entropy_refresh.1433618483
Short name T899
Test name
Test status
Simulation time 22853091336 ps
CPU time 431.66 seconds
Started Feb 09 02:29:07 AM UTC 25
Finished Feb 09 02:36:25 AM UTC 25
Peak memory 331680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433618483 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.1433618483 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_error.193754128
Short name T886
Test name
Test status
Simulation time 1516300237 ps
CPU time 15.72 seconds
Started Feb 09 02:29:19 AM UTC 25
Finished Feb 09 02:29:36 AM UTC 25
Peak memory 245660 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193754128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_er
ror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 42.kmac_error.193754128 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_key_error.2723844344
Short name T887
Test name
Test status
Simulation time 2145442609 ps
CPU time 10.5 seconds
Started Feb 09 02:29:37 AM UTC 25
Finished Feb 09 02:29:49 AM UTC 25
Peak memory 227296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723844344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 42.kmac_key_error.2723844344 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_lc_escalation.2903320539
Short name T888
Test name
Test status
Simulation time 42716472 ps
CPU time 2.1 seconds
Started Feb 09 02:29:49 AM UTC 25
Finished Feb 09 02:29:53 AM UTC 25
Peak memory 231544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903320539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2903320539 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_long_msg_and_output.1718236354
Short name T996
Test name
Test status
Simulation time 1259947800508 ps
CPU time 2897.41 seconds
Started Feb 09 02:24:01 AM UTC 25
Finished Feb 09 03:12:48 AM UTC 25
Peak memory 3264424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718236354 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_and_output.1718236354 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_sideload.234363656
Short name T892
Test name
Test status
Simulation time 6192529272 ps
CPU time 389.76 seconds
Started Feb 09 02:24:16 AM UTC 25
Finished Feb 09 02:30:51 AM UTC 25
Peak memory 370796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234363656 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.234363656 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_smoke.3241363539
Short name T874
Test name
Test status
Simulation time 3711790295 ps
CPU time 48.16 seconds
Started Feb 09 02:23:30 AM UTC 25
Finished Feb 09 02:24:20 AM UTC 25
Peak memory 235404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241363539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 42.kmac_smoke.3241363539 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_stress_all.1571349273
Short name T932
Test name
Test status
Simulation time 21361235062 ps
CPU time 987.91 seconds
Started Feb 09 02:29:54 AM UTC 25
Finished Feb 09 02:46:34 AM UTC 25
Peak memory 763812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571349273 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1571349273 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_test_vectors_kmac.3371053494
Short name T882
Test name
Test status
Simulation time 167056733 ps
CPU time 7.85 seconds
Started Feb 09 02:28:45 AM UTC 25
Finished Feb 09 02:28:54 AM UTC 25
Peak memory 235368 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3371053494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 42.kmac_test_vectors_kmac.3371053494 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_test_vectors_kmac_xof.2620474928
Short name T884
Test name
Test status
Simulation time 480540400 ps
CPU time 9.26 seconds
Started Feb 09 02:28:55 AM UTC 25
Finished Feb 09 02:29:05 AM UTC 25
Peak memory 229476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2620474928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 42.kmac_test_vectors_kmac_xof.2620474928 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_test_vectors_sha3_224.1049042453
Short name T969
Test name
Test status
Simulation time 79525038742 ps
CPU time 2485.66 seconds
Started Feb 09 02:24:44 AM UTC 25
Finished Feb 09 03:06:39 AM UTC 25
Peak memory 1220440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049042453 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.1049042453 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_test_vectors_sha3_256.4017846464
Short name T995
Test name
Test status
Simulation time 60939536550 ps
CPU time 2780.68 seconds
Started Feb 09 02:25:21 AM UTC 25
Finished Feb 09 03:12:12 AM UTC 25
Peak memory 3026968 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017846464 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.4017846464 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_test_vectors_sha3_384.4234667485
Short name T959
Test name
Test status
Simulation time 203777105600 ps
CPU time 2158.15 seconds
Started Feb 09 02:25:52 AM UTC 25
Finished Feb 09 03:02:14 AM UTC 25
Peak memory 2412552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234667485 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.4234667485 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_test_vectors_sha3_512.768300720
Short name T949
Test name
Test status
Simulation time 115822049278 ps
CPU time 1787.6 seconds
Started Feb 09 02:26:08 AM UTC 25
Finished Feb 09 02:56:16 AM UTC 25
Peak memory 1800144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768300720 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.768300720 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_test_vectors_shake_128.667427780
Short name T1056
Test name
Test status
Simulation time 63557559160 ps
CPU time 5711.5 seconds
Started Feb 09 02:26:56 AM UTC 25
Finished Feb 09 04:03:09 AM UTC 25
Peak memory 2658136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667427780 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.667427780 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/42.kmac_test_vectors_shake_256.3090766683
Short name T1065
Test name
Test status
Simulation time 329206382846 ps
CPU time 6523.21 seconds
Started Feb 09 02:28:25 AM UTC 25
Finished Feb 09 04:18:14 AM UTC 25
Peak memory 6422612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090766683 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.3090766683 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_alert_test.1847166853
Short name T908
Test name
Test status
Simulation time 24762036 ps
CPU time 1.33 seconds
Started Feb 09 02:38:43 AM UTC 25
Finished Feb 09 02:38:46 AM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847166853 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1847166853 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_app.3633053403
Short name T914
Test name
Test status
Simulation time 24420493187 ps
CPU time 295.34 seconds
Started Feb 09 02:36:46 AM UTC 25
Finished Feb 09 02:41:45 AM UTC 25
Peak memory 463016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633053403 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.3633053403 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_burst_write.1236080126
Short name T960
Test name
Test status
Simulation time 362559237173 ps
CPU time 1860.76 seconds
Started Feb 09 02:31:27 AM UTC 25
Finished Feb 09 03:02:50 AM UTC 25
Peak memory 274484 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236080126 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1236080126 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_entropy_refresh.477472902
Short name T909
Test name
Test status
Simulation time 1180344759 ps
CPU time 65.95 seconds
Started Feb 09 02:37:49 AM UTC 25
Finished Feb 09 02:38:57 AM UTC 25
Peak memory 251736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477472902 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.477472902 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_error.1909688951
Short name T923
Test name
Test status
Simulation time 10937016521 ps
CPU time 357.44 seconds
Started Feb 09 02:38:08 AM UTC 25
Finished Feb 09 02:44:10 AM UTC 25
Peak memory 532392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909688951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 43.kmac_error.1909688951 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_key_error.2086928349
Short name T905
Test name
Test status
Simulation time 4580907164 ps
CPU time 11.48 seconds
Started Feb 09 02:38:11 AM UTC 25
Finished Feb 09 02:38:23 AM UTC 25
Peak memory 229408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086928349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 43.kmac_key_error.2086928349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_lc_escalation.3629076160
Short name T906
Test name
Test status
Simulation time 39003374 ps
CPU time 2.1 seconds
Started Feb 09 02:38:24 AM UTC 25
Finished Feb 09 02:38:27 AM UTC 25
Peak memory 231416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629076160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.3629076160 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_long_msg_and_output.2807365972
Short name T939
Test name
Test status
Simulation time 206115425911 ps
CPU time 1148.26 seconds
Started Feb 09 02:30:47 AM UTC 25
Finished Feb 09 02:50:08 AM UTC 25
Peak memory 1257436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807365972 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_and_output.2807365972 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_sideload.136009088
Short name T903
Test name
Test status
Simulation time 55554853902 ps
CPU time 430 seconds
Started Feb 09 02:30:52 AM UTC 25
Finished Feb 09 02:38:08 AM UTC 25
Peak memory 565300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136009088 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.136009088 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_smoke.1224575478
Short name T891
Test name
Test status
Simulation time 1683254471 ps
CPU time 43.77 seconds
Started Feb 09 02:30:00 AM UTC 25
Finished Feb 09 02:30:46 AM UTC 25
Peak memory 235360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224575478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 43.kmac_smoke.1224575478 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_stress_all.2067774640
Short name T991
Test name
Test status
Simulation time 150085449169 ps
CPU time 1919.5 seconds
Started Feb 09 02:38:28 AM UTC 25
Finished Feb 09 03:10:49 AM UTC 25
Peak memory 704808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067774640 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2067774640 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_kmac.2414850496
Short name T900
Test name
Test status
Simulation time 129783420 ps
CPU time 7.96 seconds
Started Feb 09 02:36:26 AM UTC 25
Finished Feb 09 02:36:35 AM UTC 25
Peak memory 235428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2414850496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 43.kmac_test_vectors_kmac.2414850496 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_kmac_xof.2290140971
Short name T901
Test name
Test status
Simulation time 408031045 ps
CPU time 7.38 seconds
Started Feb 09 02:36:36 AM UTC 25
Finished Feb 09 02:36:45 AM UTC 25
Peak memory 235360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2290140971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 43.kmac_test_vectors_kmac_xof.2290140971 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_sha3_224.2629124368
Short name T973
Test name
Test status
Simulation time 41662177627 ps
CPU time 2091.96 seconds
Started Feb 09 02:31:55 AM UTC 25
Finished Feb 09 03:07:10 AM UTC 25
Peak memory 1193812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629124368 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.2629124368 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_sha3_256.2616919542
Short name T982
Test name
Test status
Simulation time 19110468514 ps
CPU time 2151.1 seconds
Started Feb 09 02:32:03 AM UTC 25
Finished Feb 09 03:08:18 AM UTC 25
Peak memory 1132436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616919542 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.2616919542 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_sha3_384.2156882571
Short name T1007
Test name
Test status
Simulation time 75222102012 ps
CPU time 2603.97 seconds
Started Feb 09 02:32:13 AM UTC 25
Finished Feb 09 03:16:07 AM UTC 25
Peak memory 2359132 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156882571 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2156882571 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_sha3_512.1420683610
Short name T947
Test name
Test status
Simulation time 43488414955 ps
CPU time 1297.55 seconds
Started Feb 09 02:32:39 AM UTC 25
Finished Feb 09 02:54:31 AM UTC 25
Peak memory 724828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420683610 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1420683610 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_shake_128.3878638250
Short name T1066
Test name
Test status
Simulation time 74339164717 ps
CPU time 6419.26 seconds
Started Feb 09 02:33:00 AM UTC 25
Finished Feb 09 04:21:10 AM UTC 25
Peak memory 2695068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878638250 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.3878638250 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/43.kmac_test_vectors_shake_256.3359365360
Short name T1073
Test name
Test status
Simulation time 632745898429 ps
CPU time 7092.37 seconds
Started Feb 09 02:36:08 AM UTC 25
Finished Feb 09 04:35:36 AM UTC 25
Peak memory 6461400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359365360 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3359365360 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_alert_test.1478718052
Short name T927
Test name
Test status
Simulation time 18995874 ps
CPU time 1.28 seconds
Started Feb 09 02:45:17 AM UTC 25
Finished Feb 09 02:45:20 AM UTC 25
Peak memory 225524 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478718052 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.1478718052 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_app.287285704
Short name T935
Test name
Test status
Simulation time 18508749136 ps
CPU time 249.5 seconds
Started Feb 09 02:43:47 AM UTC 25
Finished Feb 09 02:48:00 AM UTC 25
Peak memory 387024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287285704 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.287285704 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_burst_write.2506682229
Short name T942
Test name
Test status
Simulation time 59991374506 ps
CPU time 765.51 seconds
Started Feb 09 02:39:34 AM UTC 25
Finished Feb 09 02:52:30 AM UTC 25
Peak memory 252012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506682229 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.2506682229 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_entropy_refresh.3486528746
Short name T941
Test name
Test status
Simulation time 99231427046 ps
CPU time 512.01 seconds
Started Feb 09 02:43:50 AM UTC 25
Finished Feb 09 02:52:29 AM UTC 25
Peak memory 501664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486528746 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3486528746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_error.2102995006
Short name T928
Test name
Test status
Simulation time 8785958439 ps
CPU time 99.79 seconds
Started Feb 09 02:44:01 AM UTC 25
Finished Feb 09 02:45:43 AM UTC 25
Peak memory 301068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102995006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 44.kmac_error.2102995006 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_key_error.4197118699
Short name T924
Test name
Test status
Simulation time 903691616 ps
CPU time 4.12 seconds
Started Feb 09 02:44:11 AM UTC 25
Finished Feb 09 02:44:17 AM UTC 25
Peak memory 227296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197118699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 44.kmac_key_error.4197118699 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_lc_escalation.2276865420
Short name T925
Test name
Test status
Simulation time 43544667 ps
CPU time 2.03 seconds
Started Feb 09 02:44:18 AM UTC 25
Finished Feb 09 02:44:21 AM UTC 25
Peak memory 231544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276865420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2276865420 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_long_msg_and_output.1855537017
Short name T988
Test name
Test status
Simulation time 58100400513 ps
CPU time 1811.09 seconds
Started Feb 09 02:38:58 AM UTC 25
Finished Feb 09 03:09:30 AM UTC 25
Peak memory 1058720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855537017 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_and_output.1855537017 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_sideload.2827243864
Short name T917
Test name
Test status
Simulation time 32066389802 ps
CPU time 221.33 seconds
Started Feb 09 02:39:06 AM UTC 25
Finished Feb 09 02:42:51 AM UTC 25
Peak memory 407464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827243864 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2827243864 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_smoke.2950206984
Short name T912
Test name
Test status
Simulation time 10451374575 ps
CPU time 78.79 seconds
Started Feb 09 02:38:47 AM UTC 25
Finished Feb 09 02:40:07 AM UTC 25
Peak memory 235424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950206984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 44.kmac_smoke.2950206984 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_stress_all.3660988631
Short name T926
Test name
Test status
Simulation time 9571038375 ps
CPU time 52.33 seconds
Started Feb 09 02:44:22 AM UTC 25
Finished Feb 09 02:45:16 AM UTC 25
Peak memory 251976 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660988631 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.3660988631 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_test_vectors_kmac.3377800270
Short name T919
Test name
Test status
Simulation time 185453178 ps
CPU time 8.74 seconds
Started Feb 09 02:43:30 AM UTC 25
Finished Feb 09 02:43:40 AM UTC 25
Peak memory 229420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3377800270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 44.kmac_test_vectors_kmac.3377800270 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_test_vectors_kmac_xof.2219901742
Short name T921
Test name
Test status
Simulation time 233689612 ps
CPU time 6.38 seconds
Started Feb 09 02:43:41 AM UTC 25
Finished Feb 09 02:43:49 AM UTC 25
Peak memory 229584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2219901742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 44.kmac_test_vectors_kmac_xof.2219901742 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_test_vectors_sha3_224.285262705
Short name T1018
Test name
Test status
Simulation time 34385373116 ps
CPU time 2380.47 seconds
Started Feb 09 02:40:09 AM UTC 25
Finished Feb 09 03:20:17 AM UTC 25
Peak memory 1212256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285262705 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.285262705 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_test_vectors_sha3_256.1725479700
Short name T1034
Test name
Test status
Simulation time 91718006349 ps
CPU time 3130.38 seconds
Started Feb 09 02:40:41 AM UTC 25
Finished Feb 09 03:33:25 AM UTC 25
Peak memory 3067712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725479700 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.1725479700 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_test_vectors_sha3_384.1367074947
Short name T1016
Test name
Test status
Simulation time 49182703613 ps
CPU time 2273.79 seconds
Started Feb 09 02:41:47 AM UTC 25
Finished Feb 09 03:20:07 AM UTC 25
Peak memory 2398048 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367074947 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.1367074947 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_test_vectors_sha3_512.2719918215
Short name T972
Test name
Test status
Simulation time 44739316114 ps
CPU time 1466.16 seconds
Started Feb 09 02:42:25 AM UTC 25
Finished Feb 09 03:07:08 AM UTC 25
Peak memory 1718304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719918215 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.2719918215 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_test_vectors_shake_128.265859402
Short name T1077
Test name
Test status
Simulation time 1079098242062 ps
CPU time 8878.33 seconds
Started Feb 09 02:42:43 AM UTC 25
Finished Feb 09 05:12:14 AM UTC 25
Peak memory 7819256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265859402 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.265859402 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/44.kmac_test_vectors_shake_256.2031636317
Short name T1061
Test name
Test status
Simulation time 116582223553 ps
CPU time 5464.47 seconds
Started Feb 09 02:42:52 AM UTC 25
Finished Feb 09 04:14:56 AM UTC 25
Peak memory 2232124 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031636317 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2031636317 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_alert_test.1692258894
Short name T945
Test name
Test status
Simulation time 17983238 ps
CPU time 1.24 seconds
Started Feb 09 02:52:44 AM UTC 25
Finished Feb 09 02:52:47 AM UTC 25
Peak memory 225884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692258894 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1692258894 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_app.2281547407
Short name T946
Test name
Test status
Simulation time 3838347952 ps
CPU time 188.31 seconds
Started Feb 09 02:49:38 AM UTC 25
Finished Feb 09 02:52:50 AM UTC 25
Peak memory 280532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281547407 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2281547407 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_burst_write.2271176203
Short name T958
Test name
Test status
Simulation time 68694185603 ps
CPU time 907.97 seconds
Started Feb 09 02:45:56 AM UTC 25
Finished Feb 09 03:01:15 AM UTC 25
Peak memory 257960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271176203 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2271176203 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_entropy_refresh.1620928577
Short name T951
Test name
Test status
Simulation time 28129941434 ps
CPU time 426.66 seconds
Started Feb 09 02:50:10 AM UTC 25
Finished Feb 09 02:57:22 AM UTC 25
Peak memory 561040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620928577 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1620928577 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_error.3275528420
Short name T953
Test name
Test status
Simulation time 130177466470 ps
CPU time 404.52 seconds
Started Feb 09 02:52:13 AM UTC 25
Finished Feb 09 02:59:04 AM UTC 25
Peak memory 438156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275528420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 45.kmac_error.3275528420 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_key_error.3418285769
Short name T944
Test name
Test status
Simulation time 3586628662 ps
CPU time 12.63 seconds
Started Feb 09 02:52:30 AM UTC 25
Finished Feb 09 02:52:44 AM UTC 25
Peak memory 227232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418285769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 45.kmac_key_error.3418285769 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_lc_escalation.2899633237
Short name T943
Test name
Test status
Simulation time 40790193 ps
CPU time 2.24 seconds
Started Feb 09 02:52:31 AM UTC 25
Finished Feb 09 02:52:34 AM UTC 25
Peak memory 233456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899633237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2899633237 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_long_msg_and_output.1968068198
Short name T1003
Test name
Test status
Simulation time 78019187102 ps
CPU time 1753.43 seconds
Started Feb 09 02:45:45 AM UTC 25
Finished Feb 09 03:15:18 AM UTC 25
Peak memory 2054040 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968068198 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_and_output.1968068198 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_sideload.3965431569
Short name T934
Test name
Test status
Simulation time 4560631566 ps
CPU time 97.9 seconds
Started Feb 09 02:45:45 AM UTC 25
Finished Feb 09 02:47:25 AM UTC 25
Peak memory 301012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965431569 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3965431569 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_smoke.2903132937
Short name T930
Test name
Test status
Simulation time 1256933142 ps
CPU time 32.87 seconds
Started Feb 09 02:45:20 AM UTC 25
Finished Feb 09 02:45:55 AM UTC 25
Peak memory 233740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903132937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 45.kmac_smoke.2903132937 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_stress_all.2059002080
Short name T1010
Test name
Test status
Simulation time 164589712793 ps
CPU time 1500.61 seconds
Started Feb 09 02:52:35 AM UTC 25
Finished Feb 09 03:17:54 AM UTC 25
Peak memory 645392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059002080 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2059002080 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_test_vectors_kmac.4054857385
Short name T937
Test name
Test status
Simulation time 250175710 ps
CPU time 5.74 seconds
Started Feb 09 02:49:19 AM UTC 25
Finished Feb 09 02:49:26 AM UTC 25
Peak memory 229428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=4054857385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 45.kmac_test_vectors_kmac.4054857385 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_test_vectors_kmac_xof.3085308086
Short name T938
Test name
Test status
Simulation time 187357874 ps
CPU time 8.58 seconds
Started Feb 09 02:49:27 AM UTC 25
Finished Feb 09 02:49:37 AM UTC 25
Peak memory 235416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3085308086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 45.kmac_test_vectors_kmac_xof.3085308086 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_test_vectors_sha3_224.2324401778
Short name T1014
Test name
Test status
Simulation time 21975961987 ps
CPU time 1973.82 seconds
Started Feb 09 02:46:06 AM UTC 25
Finished Feb 09 03:19:22 AM UTC 25
Peak memory 1183828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324401778 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2324401778 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_test_vectors_sha3_256.2843592585
Short name T1037
Test name
Test status
Simulation time 185041917876 ps
CPU time 2864.1 seconds
Started Feb 09 02:46:36 AM UTC 25
Finished Feb 09 03:34:50 AM UTC 25
Peak memory 3094336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843592585 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.2843592585 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_test_vectors_sha3_512.339247044
Short name T997
Test name
Test status
Simulation time 138569560496 ps
CPU time 1541.49 seconds
Started Feb 09 02:47:18 AM UTC 25
Finished Feb 09 03:13:16 AM UTC 25
Peak memory 1738588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339247044 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.339247044 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_test_vectors_shake_128.3996975090
Short name T1070
Test name
Test status
Simulation time 498046819577 ps
CPU time 6001.95 seconds
Started Feb 09 02:47:26 AM UTC 25
Finished Feb 09 04:28:31 AM UTC 25
Peak memory 2682716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996975090 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.3996975090 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/45.kmac_test_vectors_shake_256.1820642026
Short name T1059
Test name
Test status
Simulation time 480663710389 ps
CPU time 4781.48 seconds
Started Feb 09 02:48:01 AM UTC 25
Finished Feb 09 04:08:34 AM UTC 25
Peak memory 2209684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820642026 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.1820642026 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/45.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_alert_test.106666137
Short name T965
Test name
Test status
Simulation time 51390956 ps
CPU time 1.29 seconds
Started Feb 09 03:03:10 AM UTC 25
Finished Feb 09 03:03:12 AM UTC 25
Peak memory 225708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106666137 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.106666137 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_app.2244230330
Short name T962
Test name
Test status
Simulation time 6071408572 ps
CPU time 121.47 seconds
Started Feb 09 03:01:04 AM UTC 25
Finished Feb 09 03:03:08 AM UTC 25
Peak memory 290728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244230330 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2244230330 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_burst_write.3725452368
Short name T978
Test name
Test status
Simulation time 74369553809 ps
CPU time 775.19 seconds
Started Feb 09 02:54:41 AM UTC 25
Finished Feb 09 03:07:45 AM UTC 25
Peak memory 258220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725452368 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.3725452368 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_entropy_refresh.3512993343
Short name T961
Test name
Test status
Simulation time 8491575987 ps
CPU time 109.12 seconds
Started Feb 09 03:01:16 AM UTC 25
Finished Feb 09 03:03:08 AM UTC 25
Peak memory 284640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512993343 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3512993343 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_error.1804719263
Short name T966
Test name
Test status
Simulation time 3887634359 ps
CPU time 65.51 seconds
Started Feb 09 03:02:16 AM UTC 25
Finished Feb 09 03:03:23 AM UTC 25
Peak memory 274340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804719263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 46.kmac_error.1804719263 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_key_error.3175149476
Short name T963
Test name
Test status
Simulation time 4124907418 ps
CPU time 16.8 seconds
Started Feb 09 03:02:51 AM UTC 25
Finished Feb 09 03:03:09 AM UTC 25
Peak memory 227284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175149476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 46.kmac_key_error.3175149476 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_lc_escalation.236328062
Short name T964
Test name
Test status
Simulation time 45773311 ps
CPU time 2.15 seconds
Started Feb 09 03:03:08 AM UTC 25
Finished Feb 09 03:03:11 AM UTC 25
Peak memory 231464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236328062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.236328062 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_sideload.2365115208
Short name T952
Test name
Test status
Simulation time 24421081821 ps
CPU time 240.65 seconds
Started Feb 09 02:54:33 AM UTC 25
Finished Feb 09 02:58:37 AM UTC 25
Peak memory 395180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365115208 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.2365115208 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_smoke.2842645176
Short name T948
Test name
Test status
Simulation time 5784440337 ps
CPU time 109.56 seconds
Started Feb 09 02:52:48 AM UTC 25
Finished Feb 09 02:54:40 AM UTC 25
Peak memory 235480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842645176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 46.kmac_smoke.2842645176 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_stress_all.1881831050
Short name T968
Test name
Test status
Simulation time 2816316619 ps
CPU time 129.83 seconds
Started Feb 09 03:03:10 AM UTC 25
Finished Feb 09 03:05:22 AM UTC 25
Peak memory 268244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881831050 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.1881831050 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_kmac.239493367
Short name T956
Test name
Test status
Simulation time 196915090 ps
CPU time 8.57 seconds
Started Feb 09 03:00:43 AM UTC 25
Finished Feb 09 03:00:53 AM UTC 25
Peak memory 235532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=239493367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 46.kmac_test_vectors_kmac.239493367 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_kmac_xof.3528532567
Short name T957
Test name
Test status
Simulation time 386169245 ps
CPU time 7.91 seconds
Started Feb 09 03:00:54 AM UTC 25
Finished Feb 09 03:01:03 AM UTC 25
Peak memory 229424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3528532567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 46.kmac_test_vectors_kmac_xof.3528532567 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_sha3_224.2027857170
Short name T1048
Test name
Test status
Simulation time 67584857412 ps
CPU time 2845.85 seconds
Started Feb 09 02:56:17 AM UTC 25
Finished Feb 09 03:44:15 AM UTC 25
Peak memory 3225620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027857170 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.2027857170 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_sha3_256.2837574849
Short name T1030
Test name
Test status
Simulation time 75512542009 ps
CPU time 1973.27 seconds
Started Feb 09 02:56:34 AM UTC 25
Finished Feb 09 03:29:48 AM UTC 25
Peak memory 1128264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837574849 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.2837574849 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_sha3_384.506512662
Short name T1028
Test name
Test status
Simulation time 196567674333 ps
CPU time 1828.91 seconds
Started Feb 09 02:57:23 AM UTC 25
Finished Feb 09 03:28:12 AM UTC 25
Peak memory 2369420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506512662 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.506512662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_sha3_512.2229228459
Short name T1027
Test name
Test status
Simulation time 179480237965 ps
CPU time 1716.94 seconds
Started Feb 09 02:58:39 AM UTC 25
Finished Feb 09 03:27:35 AM UTC 25
Peak memory 1775560 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229228459 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2229228459 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_shake_128.3870424071
Short name T1076
Test name
Test status
Simulation time 194702897844 ps
CPU time 7870.98 seconds
Started Feb 09 02:59:04 AM UTC 25
Finished Feb 09 05:11:37 AM UTC 25
Peak memory 7792444 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870424071 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.3870424071 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/46.kmac_test_vectors_shake_256.1327307842
Short name T1063
Test name
Test status
Simulation time 73507538399 ps
CPU time 4611.76 seconds
Started Feb 09 02:59:55 AM UTC 25
Finished Feb 09 04:17:35 AM UTC 25
Peak memory 2250636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327307842 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1327307842 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_alert_test.1281860678
Short name T983
Test name
Test status
Simulation time 50109415 ps
CPU time 1.24 seconds
Started Feb 09 03:08:19 AM UTC 25
Finished Feb 09 03:08:21 AM UTC 25
Peak memory 225944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281860678 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1281860678 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_app.1743636155
Short name T992
Test name
Test status
Simulation time 45713214548 ps
CPU time 224.42 seconds
Started Feb 09 03:07:26 AM UTC 25
Finished Feb 09 03:11:14 AM UTC 25
Peak memory 374752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743636155 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.1743636155 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_burst_write.2327319192
Short name T980
Test name
Test status
Simulation time 3653393881 ps
CPU time 212.86 seconds
Started Feb 09 03:04:36 AM UTC 25
Finished Feb 09 03:08:13 AM UTC 25
Peak memory 235440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327319192 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2327319192 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_entropy_refresh.1249169977
Short name T986
Test name
Test status
Simulation time 11464561394 ps
CPU time 58 seconds
Started Feb 09 03:07:38 AM UTC 25
Finished Feb 09 03:08:37 AM UTC 25
Peak memory 262184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249169977 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.1249169977 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_error.62373895
Short name T985
Test name
Test status
Simulation time 1185943899 ps
CPU time 44.16 seconds
Started Feb 09 03:07:46 AM UTC 25
Finished Feb 09 03:08:32 AM UTC 25
Peak memory 278424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62373895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_err
or_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 47.kmac_error.62373895 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_key_error.362727923
Short name T984
Test name
Test status
Simulation time 3268931566 ps
CPU time 22.18 seconds
Started Feb 09 03:08:03 AM UTC 25
Finished Feb 09 03:08:27 AM UTC 25
Peak memory 227288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362727923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ke
y_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.kmac_key_error.362727923 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_lc_escalation.3665121588
Short name T48
Test name
Test status
Simulation time 1691678226 ps
CPU time 15.02 seconds
Started Feb 09 03:08:13 AM UTC 25
Finished Feb 09 03:08:30 AM UTC 25
Peak memory 245724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665121588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3665121588 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_long_msg_and_output.2110735298
Short name T1031
Test name
Test status
Simulation time 12531138189 ps
CPU time 1595.42 seconds
Started Feb 09 03:03:13 AM UTC 25
Finished Feb 09 03:30:07 AM UTC 25
Peak memory 944084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110735298 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_and_output.2110735298 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_sideload.391305180
Short name T974
Test name
Test status
Simulation time 26203754007 ps
CPU time 226.55 seconds
Started Feb 09 03:03:23 AM UTC 25
Finished Feb 09 03:07:13 AM UTC 25
Peak memory 401328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391305180 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.391305180 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_smoke.3577934056
Short name T967
Test name
Test status
Simulation time 1797387486 ps
CPU time 80.52 seconds
Started Feb 09 03:03:12 AM UTC 25
Finished Feb 09 03:04:34 AM UTC 25
Peak memory 235492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577934056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 47.kmac_smoke.3577934056 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_stress_all.2859754511
Short name T1002
Test name
Test status
Simulation time 9880500263 ps
CPU time 395.82 seconds
Started Feb 09 03:08:19 AM UTC 25
Finished Feb 09 03:15:00 AM UTC 25
Peak memory 389472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859754511 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.2859754511 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_kmac.2668828863
Short name T975
Test name
Test status
Simulation time 1359633404 ps
CPU time 8.82 seconds
Started Feb 09 03:07:15 AM UTC 25
Finished Feb 09 03:07:25 AM UTC 25
Peak memory 229400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2668828863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 47.kmac_test_vectors_kmac.2668828863 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_kmac_xof.21527367
Short name T977
Test name
Test status
Simulation time 887193500 ps
CPU time 9.33 seconds
Started Feb 09 03:07:26 AM UTC 25
Finished Feb 09 03:07:37 AM UTC 25
Peak memory 235344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=21527367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 47.kmac_test_vectors_kmac_xof.21527367 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_sha3_224.801225581
Short name T1046
Test name
Test status
Simulation time 41909930809 ps
CPU time 2059.97 seconds
Started Feb 09 03:05:23 AM UTC 25
Finished Feb 09 03:40:05 AM UTC 25
Peak memory 1218448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801225581 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.801225581 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_sha3_256.221409341
Short name T1053
Test name
Test status
Simulation time 93179020329 ps
CPU time 3077.05 seconds
Started Feb 09 03:06:40 AM UTC 25
Finished Feb 09 03:58:30 AM UTC 25
Peak memory 3061592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221409341 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.221409341 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_sha3_384.1286049165
Short name T1038
Test name
Test status
Simulation time 30533267636 ps
CPU time 1669.06 seconds
Started Feb 09 03:06:43 AM UTC 25
Finished Feb 09 03:34:50 AM UTC 25
Peak memory 937820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286049165 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1286049165 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_sha3_512.1802033685
Short name T1026
Test name
Test status
Simulation time 10742751214 ps
CPU time 1215.06 seconds
Started Feb 09 03:07:02 AM UTC 25
Finished Feb 09 03:27:31 AM UTC 25
Peak memory 724880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802033685 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1802033685 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_shake_128.4205193841
Short name T1079
Test name
Test status
Simulation time 1963118981594 ps
CPU time 8838.51 seconds
Started Feb 09 03:07:09 AM UTC 25
Finished Feb 09 05:35:58 AM UTC 25
Peak memory 7737336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205193841 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.4205193841 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/47.kmac_test_vectors_shake_256.245519496
Short name T1072
Test name
Test status
Simulation time 99881346020 ps
CPU time 5007.6 seconds
Started Feb 09 03:07:10 AM UTC 25
Finished Feb 09 04:31:33 AM UTC 25
Peak memory 2213748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245519496 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.245519496 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/47.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_alert_test.1523184958
Short name T1001
Test name
Test status
Simulation time 26600637 ps
CPU time 1.24 seconds
Started Feb 09 03:14:31 AM UTC 25
Finished Feb 09 03:14:33 AM UTC 25
Peak memory 225704 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523184958 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.1523184958 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_app.1745421097
Short name T1020
Test name
Test status
Simulation time 75498207835 ps
CPU time 532.07 seconds
Started Feb 09 03:11:34 AM UTC 25
Finished Feb 09 03:20:34 AM UTC 25
Peak memory 563120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745421097 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1745421097 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_burst_write.866034410
Short name T1036
Test name
Test status
Simulation time 28222161578 ps
CPU time 1529.81 seconds
Started Feb 09 03:08:32 AM UTC 25
Finished Feb 09 03:34:19 AM UTC 25
Peak memory 255972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866034410 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.866034410 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_entropy_refresh.4238609004
Short name T1013
Test name
Test status
Simulation time 16277538980 ps
CPU time 419.01 seconds
Started Feb 09 03:12:13 AM UTC 25
Finished Feb 09 03:19:17 AM UTC 25
Peak memory 481188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238609004 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.4238609004 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_error.3985671044
Short name T1005
Test name
Test status
Simulation time 9457406299 ps
CPU time 173.41 seconds
Started Feb 09 03:12:49 AM UTC 25
Finished Feb 09 03:15:45 AM UTC 25
Peak memory 301148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985671044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 48.kmac_error.3985671044 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_key_error.330191035
Short name T998
Test name
Test status
Simulation time 11977006549 ps
CPU time 21.2 seconds
Started Feb 09 03:13:16 AM UTC 25
Finished Feb 09 03:13:39 AM UTC 25
Peak memory 227428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330191035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ke
y_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.kmac_key_error.330191035 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_lc_escalation.2040036672
Short name T999
Test name
Test status
Simulation time 864985280 ps
CPU time 20.59 seconds
Started Feb 09 03:13:40 AM UTC 25
Finished Feb 09 03:14:02 AM UTC 25
Peak memory 245804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040036672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2040036672 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_long_msg_and_output.4169598401
Short name T1045
Test name
Test status
Simulation time 299890219452 ps
CPU time 1815.69 seconds
Started Feb 09 03:08:28 AM UTC 25
Finished Feb 09 03:39:03 AM UTC 25
Peak memory 1122272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169598401 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_and_output.4169598401 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_sideload.1020028076
Short name T1008
Test name
Test status
Simulation time 5906796191 ps
CPU time 474.61 seconds
Started Feb 09 03:08:31 AM UTC 25
Finished Feb 09 03:16:32 AM UTC 25
Peak memory 405600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020028076 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1020028076 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_smoke.1148384500
Short name T989
Test name
Test status
Simulation time 2906800165 ps
CPU time 85.58 seconds
Started Feb 09 03:08:22 AM UTC 25
Finished Feb 09 03:09:50 AM UTC 25
Peak memory 235428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148384500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 48.kmac_smoke.1148384500 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_stress_all.3782374896
Short name T1021
Test name
Test status
Simulation time 36305121434 ps
CPU time 495.38 seconds
Started Feb 09 03:14:03 AM UTC 25
Finished Feb 09 03:22:25 AM UTC 25
Peak memory 446820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782374896 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.3782374896 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_kmac.670498850
Short name T993
Test name
Test status
Simulation time 212399653 ps
CPU time 8.56 seconds
Started Feb 09 03:11:15 AM UTC 25
Finished Feb 09 03:11:25 AM UTC 25
Peak memory 235348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=670498850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 48.kmac_test_vectors_kmac.670498850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_kmac_xof.3182259254
Short name T994
Test name
Test status
Simulation time 269766303 ps
CPU time 6.71 seconds
Started Feb 09 03:11:25 AM UTC 25
Finished Feb 09 03:11:33 AM UTC 25
Peak memory 229424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3182259254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 48.kmac_test_vectors_kmac_xof.3182259254 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_sha3_224.2929703404
Short name T1057
Test name
Test status
Simulation time 537718865821 ps
CPU time 3234.78 seconds
Started Feb 09 03:08:38 AM UTC 25
Finished Feb 09 04:03:09 AM UTC 25
Peak memory 3227532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929703404 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.2929703404 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_sha3_256.3653968015
Short name T1047
Test name
Test status
Simulation time 45277329721 ps
CPU time 2036.63 seconds
Started Feb 09 03:09:05 AM UTC 25
Finished Feb 09 03:43:24 AM UTC 25
Peak memory 1161112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653968015 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.3653968015 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_sha3_384.3810172682
Short name T1049
Test name
Test status
Simulation time 198319381560 ps
CPU time 2082.33 seconds
Started Feb 09 03:09:31 AM UTC 25
Finished Feb 09 03:44:36 AM UTC 25
Peak memory 2406416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810172682 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3810172682 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_sha3_512.3772164260
Short name T1032
Test name
Test status
Simulation time 11005728773 ps
CPU time 1276.73 seconds
Started Feb 09 03:09:51 AM UTC 25
Finished Feb 09 03:31:22 AM UTC 25
Peak memory 726928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772164260 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3772164260 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_shake_128.3295159407
Short name T1080
Test name
Test status
Simulation time 260749395510 ps
CPU time 9036.13 seconds
Started Feb 09 03:10:34 AM UTC 25
Finished Feb 09 05:42:44 AM UTC 25
Peak memory 7817152 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295159407 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.3295159407 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/48.kmac_test_vectors_shake_256.1465874463
Short name T1078
Test name
Test status
Simulation time 908009781601 ps
CPU time 7800.85 seconds
Started Feb 09 03:10:51 AM UTC 25
Finished Feb 09 05:22:17 AM UTC 25
Peak memory 6377356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465874463 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1465874463 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/48.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_alert_test.2008717816
Short name T1019
Test name
Test status
Simulation time 23678915 ps
CPU time 1.27 seconds
Started Feb 09 03:20:17 AM UTC 25
Finished Feb 09 03:20:19 AM UTC 25
Peak memory 224264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008717816 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.2008717816 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_app.2043363538
Short name T1022
Test name
Test status
Simulation time 23303819988 ps
CPU time 248.44 seconds
Started Feb 09 03:19:18 AM UTC 25
Finished Feb 09 03:23:31 AM UTC 25
Peak memory 350176 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043363538 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2043363538 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_burst_write.3537436570
Short name T1044
Test name
Test status
Simulation time 27617274109 ps
CPU time 1394.22 seconds
Started Feb 09 03:15:20 AM UTC 25
Finished Feb 09 03:38:50 AM UTC 25
Peak memory 270448 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537436570 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3537436570 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_entropy_refresh.3023850662
Short name T1024
Test name
Test status
Simulation time 9211296677 ps
CPU time 372.44 seconds
Started Feb 09 03:19:23 AM UTC 25
Finished Feb 09 03:25:40 AM UTC 25
Peak memory 331744 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023850662 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3023850662 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_error.3969543152
Short name T1025
Test name
Test status
Simulation time 8380425479 ps
CPU time 419.31 seconds
Started Feb 09 03:19:26 AM UTC 25
Finished Feb 09 03:26:31 AM UTC 25
Peak memory 344224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969543152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 49.kmac_error.3969543152 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_key_error.3185897076
Short name T99
Test name
Test status
Simulation time 208619617 ps
CPU time 2.59 seconds
Started Feb 09 03:20:07 AM UTC 25
Finished Feb 09 03:20:11 AM UTC 25
Peak memory 227168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185897076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 49.kmac_key_error.3185897076 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_lc_escalation.2289341434
Short name T1017
Test name
Test status
Simulation time 133320087 ps
CPU time 1.44 seconds
Started Feb 09 03:20:12 AM UTC 25
Finished Feb 09 03:20:14 AM UTC 25
Peak memory 230960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289341434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2289341434 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_long_msg_and_output.2724471027
Short name T1060
Test name
Test status
Simulation time 158585405672 ps
CPU time 3178.3 seconds
Started Feb 09 03:15:01 AM UTC 25
Finished Feb 09 04:08:35 AM UTC 25
Peak memory 3297192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724471027 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_and_output.2724471027 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_sideload.3843682576
Short name T1006
Test name
Test status
Simulation time 361561826 ps
CPU time 34.21 seconds
Started Feb 09 03:15:18 AM UTC 25
Finished Feb 09 03:15:54 AM UTC 25
Peak memory 237600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843682576 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3843682576 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_smoke.1337484046
Short name T1004
Test name
Test status
Simulation time 868476425 ps
CPU time 43.66 seconds
Started Feb 09 03:14:34 AM UTC 25
Finished Feb 09 03:15:19 AM UTC 25
Peak memory 231468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337484046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 49.kmac_smoke.1337484046 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_stress_all.2558386206
Short name T1033
Test name
Test status
Simulation time 52611056067 ps
CPU time 699.37 seconds
Started Feb 09 03:20:15 AM UTC 25
Finished Feb 09 03:32:03 AM UTC 25
Peak memory 612260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558386206 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2558386206 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_kmac.668307890
Short name T1012
Test name
Test status
Simulation time 215464056 ps
CPU time 9.05 seconds
Started Feb 09 03:19:06 AM UTC 25
Finished Feb 09 03:19:16 AM UTC 25
Peak memory 229592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=668307890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 49.kmac_test_vectors_kmac.668307890 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_kmac_xof.1665594558
Short name T1015
Test name
Test status
Simulation time 1859055244 ps
CPU time 7.13 seconds
Started Feb 09 03:19:17 AM UTC 25
Finished Feb 09 03:19:25 AM UTC 25
Peak memory 235400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=1665594558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 49.kmac_test_vectors_kmac_xof.1665594558 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_sha3_224.3858443241
Short name T1055
Test name
Test status
Simulation time 380144458545 ps
CPU time 2654.81 seconds
Started Feb 09 03:15:46 AM UTC 25
Finished Feb 09 04:00:28 AM UTC 25
Peak memory 3174488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858443241 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.3858443241 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_sha3_256.2156693949
Short name T1054
Test name
Test status
Simulation time 62585771407 ps
CPU time 2604.68 seconds
Started Feb 09 03:15:55 AM UTC 25
Finished Feb 09 03:59:49 AM UTC 25
Peak memory 2979680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156693949 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.2156693949 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_sha3_384.861044973
Short name T1051
Test name
Test status
Simulation time 95031303102 ps
CPU time 2235.06 seconds
Started Feb 09 03:16:08 AM UTC 25
Finished Feb 09 03:53:48 AM UTC 25
Peak memory 2412380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861044973 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.861044973 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_sha3_512.1869079575
Short name T1043
Test name
Test status
Simulation time 18403579209 ps
CPU time 1312.41 seconds
Started Feb 09 03:16:33 AM UTC 25
Finished Feb 09 03:38:41 AM UTC 25
Peak memory 716688 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869079575 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.1869079575 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_shake_128.3027331476
Short name T1074
Test name
Test status
Simulation time 401979377018 ps
CPU time 5624.4 seconds
Started Feb 09 03:17:01 AM UTC 25
Finished Feb 09 04:51:46 AM UTC 25
Peak memory 2738060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027331476 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.3027331476 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/49.kmac_test_vectors_shake_256.3830834009
Short name T1075
Test name
Test status
Simulation time 439058939817 ps
CPU time 6720.77 seconds
Started Feb 09 03:17:55 AM UTC 25
Finished Feb 09 05:11:07 AM UTC 25
Peak memory 6602716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830834009 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3830834009 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_alert_test.2995397209
Short name T210
Test name
Test status
Simulation time 109426557 ps
CPU time 1.25 seconds
Started Feb 08 09:59:24 PM UTC 25
Finished Feb 08 09:59:26 PM UTC 25
Peak memory 224740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995397209 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2995397209 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_app.2321750659
Short name T213
Test name
Test status
Simulation time 12882288744 ps
CPU time 348.24 seconds
Started Feb 08 09:55:23 PM UTC 25
Finished Feb 08 10:01:16 PM UTC 25
Peak memory 472980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321750659 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2321750659 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_app_with_partial_data.3417030180
Short name T137
Test name
Test status
Simulation time 9075956484 ps
CPU time 62.28 seconds
Started Feb 08 09:55:31 PM UTC 25
Finished Feb 08 09:56:35 PM UTC 25
Peak memory 249756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417030180 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.3417030180 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_burst_write.2227558339
Short name T247
Test name
Test status
Simulation time 12185351229 ps
CPU time 1219.99 seconds
Started Feb 08 09:53:12 PM UTC 25
Finished Feb 08 10:13:45 PM UTC 25
Peak memory 251812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227558339 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2227558339 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_edn_timeout_error.1230791730
Short name T74
Test name
Test status
Simulation time 20380931 ps
CPU time 1.42 seconds
Started Feb 08 09:58:36 PM UTC 25
Finished Feb 08 09:58:39 PM UTC 25
Peak memory 227156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230791730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1230791730 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_mode_error.1128566853
Short name T208
Test name
Test status
Simulation time 709676533 ps
CPU time 18.17 seconds
Started Feb 08 09:58:39 PM UTC 25
Finished Feb 08 09:58:59 PM UTC 25
Peak memory 231460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128566853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1128566853 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_ready_error.3590924850
Short name T212
Test name
Test status
Simulation time 5805824869 ps
CPU time 64.72 seconds
Started Feb 08 09:58:48 PM UTC 25
Finished Feb 08 09:59:55 PM UTC 25
Peak memory 235440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590924850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
ntropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3590924850 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_entropy_refresh.2630937566
Short name T209
Test name
Test status
Simulation time 40683980211 ps
CPU time 214.05 seconds
Started Feb 08 09:55:45 PM UTC 25
Finished Feb 08 09:59:22 PM UTC 25
Peak memory 356324 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630937566 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2630937566 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_error.839477888
Short name T20
Test name
Test status
Simulation time 3089109553 ps
CPU time 227.67 seconds
Started Feb 08 09:57:57 PM UTC 25
Finished Feb 08 10:01:48 PM UTC 25
Peak memory 300960 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839477888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_er
ror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 5.kmac_error.839477888 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_key_error.473243837
Short name T207
Test name
Test status
Simulation time 821164112 ps
CPU time 7.71 seconds
Started Feb 08 09:58:26 PM UTC 25
Finished Feb 08 09:58:35 PM UTC 25
Peak memory 227160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473243837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ke
y_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.kmac_key_error.473243837 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_lc_escalation.1726289066
Short name T100
Test name
Test status
Simulation time 33764116 ps
CPU time 2.45 seconds
Started Feb 08 09:58:59 PM UTC 25
Finished Feb 08 09:59:03 PM UTC 25
Peak memory 233512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726289066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.1726289066 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_long_msg_and_output.368366460
Short name T285
Test name
Test status
Simulation time 106316550729 ps
CPU time 2138.37 seconds
Started Feb 08 09:52:46 PM UTC 25
Finished Feb 08 10:28:48 PM UTC 25
Peak memory 1179564 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368366460 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.368366460 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_mubi.3417021836
Short name T61
Test name
Test status
Simulation time 1899443284 ps
CPU time 106.2 seconds
Started Feb 08 09:56:36 PM UTC 25
Finished Feb 08 09:58:25 PM UTC 25
Peak memory 254312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417021836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_m
ubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 5.kmac_mubi.3417021836 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_sideload.186969787
Short name T190
Test name
Test status
Simulation time 11776725083 ps
CPU time 385.96 seconds
Started Feb 08 09:52:59 PM UTC 25
Finished Feb 08 09:59:30 PM UTC 25
Peak memory 372616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186969787 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.186969787 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_smoke.1192433208
Short name T133
Test name
Test status
Simulation time 2085838014 ps
CPU time 57.52 seconds
Started Feb 08 09:52:43 PM UTC 25
Finished Feb 08 09:53:42 PM UTC 25
Peak memory 235376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192433208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 5.kmac_smoke.1192433208 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_stress_all.3817059229
Short name T218
Test name
Test status
Simulation time 8741784130 ps
CPU time 267.34 seconds
Started Feb 08 09:59:03 PM UTC 25
Finished Feb 08 10:03:35 PM UTC 25
Peak memory 305456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817059229 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.3817059229 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_test_vectors_kmac.122196053
Short name T135
Test name
Test status
Simulation time 366529739 ps
CPU time 7.83 seconds
Started Feb 08 09:55:13 PM UTC 25
Finished Feb 08 09:55:22 PM UTC 25
Peak memory 229592 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=122196053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 5.kmac_test_vectors_kmac.122196053 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_test_vectors_kmac_xof.2505929598
Short name T136
Test name
Test status
Simulation time 125842114 ps
CPU time 7.47 seconds
Started Feb 08 09:55:22 PM UTC 25
Finished Feb 08 09:55:31 PM UTC 25
Peak memory 227352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2505929598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 5.kmac_test_vectors_kmac_xof.2505929598 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_test_vectors_sha3_224.2179132871
Short name T291
Test name
Test status
Simulation time 23616180255 ps
CPU time 2204.44 seconds
Started Feb 08 09:53:28 PM UTC 25
Finished Feb 08 10:30:37 PM UTC 25
Peak memory 1202196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179132871 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.2179132871 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_test_vectors_sha3_256.1244513105
Short name T324
Test name
Test status
Simulation time 437728148121 ps
CPU time 2885.79 seconds
Started Feb 08 09:53:43 PM UTC 25
Finished Feb 08 10:42:19 PM UTC 25
Peak memory 3020696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244513105 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1244513105 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_test_vectors_sha3_384.1988657024
Short name T288
Test name
Test status
Simulation time 65445364306 ps
CPU time 2115.85 seconds
Started Feb 08 09:53:47 PM UTC 25
Finished Feb 08 10:29:26 PM UTC 25
Peak memory 2465808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988657024 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.1988657024 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_test_vectors_sha3_512.3735668436
Short name T257
Test name
Test status
Simulation time 135317775737 ps
CPU time 1377.77 seconds
Started Feb 08 09:54:32 PM UTC 25
Finished Feb 08 10:17:45 PM UTC 25
Peak memory 1767264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735668436 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.3735668436 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_test_vectors_shake_128.717971693
Short name T595
Test name
Test status
Simulation time 1709897450783 ps
CPU time 9881.27 seconds
Started Feb 08 09:54:44 PM UTC 25
Finished Feb 09 12:41:12 AM UTC 25
Peak memory 7753904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717971693 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.717971693 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/5.kmac_test_vectors_shake_256.1496442475
Short name T538
Test name
Test status
Simulation time 1030107035697 ps
CPU time 8341.96 seconds
Started Feb 08 09:55:12 PM UTC 25
Finished Feb 09 12:15:45 AM UTC 25
Peak memory 6494224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496442475 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.1496442475 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_alert_test.1319401900
Short name T226
Test name
Test status
Simulation time 18488357 ps
CPU time 1.31 seconds
Started Feb 08 10:05:05 PM UTC 25
Finished Feb 08 10:05:07 PM UTC 25
Peak memory 225640 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319401900 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1319401900 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_app.2226951889
Short name T227
Test name
Test status
Simulation time 24378905786 ps
CPU time 188.26 seconds
Started Feb 08 10:02:52 PM UTC 25
Finished Feb 08 10:06:03 PM UTC 25
Peak memory 358312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226951889 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2226951889 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_app_with_partial_data.3504421089
Short name T221
Test name
Test status
Simulation time 3493010637 ps
CPU time 53.63 seconds
Started Feb 08 10:03:13 PM UTC 25
Finished Feb 08 10:04:08 PM UTC 25
Peak memory 251808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504421089 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.3504421089 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_burst_write.952569001
Short name T153
Test name
Test status
Simulation time 696692193 ps
CPU time 46.8 seconds
Started Feb 08 09:59:56 PM UTC 25
Finished Feb 08 10:00:44 PM UTC 25
Peak memory 235360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952569001 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.952569001 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_edn_timeout_error.1505049702
Short name T222
Test name
Test status
Simulation time 42849291 ps
CPU time 1.24 seconds
Started Feb 08 10:04:10 PM UTC 25
Finished Feb 08 10:04:12 PM UTC 25
Peak memory 227156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505049702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.1505049702 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_mode_error.429543361
Short name T223
Test name
Test status
Simulation time 356366091 ps
CPU time 1.38 seconds
Started Feb 08 10:04:13 PM UTC 25
Finished Feb 08 10:04:15 PM UTC 25
Peak memory 224144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429543361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.429543361 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_ready_error.3277001112
Short name T172
Test name
Test status
Simulation time 8300990652 ps
CPU time 125.08 seconds
Started Feb 08 10:04:16 PM UTC 25
Finished Feb 08 10:06:24 PM UTC 25
Peak memory 235432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277001112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
ntropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.3277001112 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_entropy_refresh.841483420
Short name T236
Test name
Test status
Simulation time 19005228577 ps
CPU time 303.34 seconds
Started Feb 08 10:03:15 PM UTC 25
Finished Feb 08 10:08:23 PM UTC 25
Peak memory 405396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841483420 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.841483420 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_error.1071647251
Short name T225
Test name
Test status
Simulation time 653302265 ps
CPU time 30.37 seconds
Started Feb 08 10:03:52 PM UTC 25
Finished Feb 08 10:04:24 PM UTC 25
Peak memory 251756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071647251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 6.kmac_error.1071647251 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_key_error.2497813306
Short name T224
Test name
Test status
Simulation time 4065365738 ps
CPU time 10.44 seconds
Started Feb 08 10:04:04 PM UTC 25
Finished Feb 08 10:04:15 PM UTC 25
Peak memory 227288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497813306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.kmac_key_error.2497813306 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_long_msg_and_output.2194518776
Short name T250
Test name
Test status
Simulation time 8921377918 ps
CPU time 918.72 seconds
Started Feb 08 09:59:31 PM UTC 25
Finished Feb 08 10:15:00 PM UTC 25
Peak memory 706516 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194518776 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.2194518776 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_mubi.184815176
Short name T244
Test name
Test status
Simulation time 55562647814 ps
CPU time 423.21 seconds
Started Feb 08 10:03:35 PM UTC 25
Finished Feb 08 10:10:44 PM UTC 25
Peak memory 553304 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184815176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mu
bi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 6.kmac_mubi.184815176 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_sideload.1574006627
Short name T214
Test name
Test status
Simulation time 2593652752 ps
CPU time 101.3 seconds
Started Feb 08 09:59:35 PM UTC 25
Finished Feb 08 10:01:18 PM UTC 25
Peak memory 301020 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574006627 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1574006627 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_smoke.2876188174
Short name T211
Test name
Test status
Simulation time 585635495 ps
CPU time 6.26 seconds
Started Feb 08 09:59:27 PM UTC 25
Finished Feb 08 09:59:34 PM UTC 25
Peak memory 235428 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876188174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 6.kmac_smoke.2876188174 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_stress_all.1368148338
Short name T273
Test name
Test status
Simulation time 112091975941 ps
CPU time 1189.89 seconds
Started Feb 08 10:04:22 PM UTC 25
Finished Feb 08 10:24:26 PM UTC 25
Peak memory 659956 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368148338 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.1368148338 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_test_vectors_kmac.2726094746
Short name T215
Test name
Test status
Simulation time 415639269 ps
CPU time 7.97 seconds
Started Feb 08 10:02:31 PM UTC 25
Finished Feb 08 10:02:40 PM UTC 25
Peak memory 227404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2726094746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.kmac_test_vectors_kmac.2726094746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_test_vectors_kmac_xof.3574380985
Short name T216
Test name
Test status
Simulation time 408230556 ps
CPU time 8.73 seconds
Started Feb 08 10:02:41 PM UTC 25
Finished Feb 08 10:02:51 PM UTC 25
Peak memory 227376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3574380985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 6.kmac_test_vectors_kmac_xof.3574380985 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_test_vectors_sha3_224.3592629735
Short name T347
Test name
Test status
Simulation time 96820588974 ps
CPU time 3186.99 seconds
Started Feb 08 10:00:45 PM UTC 25
Finished Feb 08 10:54:27 PM UTC 25
Peak memory 3231576 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592629735 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.3592629735 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_test_vectors_sha3_256.3572589771
Short name T345
Test name
Test status
Simulation time 110648342962 ps
CPU time 3110.12 seconds
Started Feb 08 10:01:20 PM UTC 25
Finished Feb 08 10:53:44 PM UTC 25
Peak memory 3106696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572589771 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3572589771 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_test_vectors_sha3_384.1603135599
Short name T283
Test name
Test status
Simulation time 111065309971 ps
CPU time 1607.24 seconds
Started Feb 08 10:01:20 PM UTC 25
Finished Feb 08 10:28:25 PM UTC 25
Peak memory 901016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603135599 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.1603135599 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_test_vectors_sha3_512.2118061185
Short name T293
Test name
Test status
Simulation time 141562028191 ps
CPU time 1743.77 seconds
Started Feb 08 10:01:20 PM UTC 25
Finished Feb 08 10:30:44 PM UTC 25
Peak memory 1769312 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118061185 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2118061185 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_test_vectors_shake_128.358498091
Short name T511
Test name
Test status
Simulation time 186864277212 ps
CPU time 7209.83 seconds
Started Feb 08 10:01:49 PM UTC 25
Finished Feb 09 12:03:10 AM UTC 25
Peak memory 7897044 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358498091 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.358498091 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/6.kmac_test_vectors_shake_256.2886495209
Short name T488
Test name
Test status
Simulation time 316880282157 ps
CPU time 6503.65 seconds
Started Feb 08 10:02:19 PM UTC 25
Finished Feb 08 11:51:51 PM UTC 25
Peak memory 6518752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886495209 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.2886495209 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_alert_test.4228962576
Short name T241
Test name
Test status
Simulation time 22557044 ps
CPU time 1.28 seconds
Started Feb 08 10:09:29 PM UTC 25
Finished Feb 08 10:09:31 PM UTC 25
Peak memory 224260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228962576 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.4228962576 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_app.1134563110
Short name T246
Test name
Test status
Simulation time 11294933664 ps
CPU time 284.64 seconds
Started Feb 08 10:08:08 PM UTC 25
Finished Feb 08 10:12:57 PM UTC 25
Peak memory 421864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134563110 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1134563110 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_app_with_partial_data.3653191379
Short name T237
Test name
Test status
Simulation time 1426417607 ps
CPU time 40.69 seconds
Started Feb 08 10:08:17 PM UTC 25
Finished Feb 08 10:09:00 PM UTC 25
Peak memory 251884 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653191379 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.3653191379 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_burst_write.3982619727
Short name T232
Test name
Test status
Simulation time 1380298075 ps
CPU time 90.01 seconds
Started Feb 08 10:06:16 PM UTC 25
Finished Feb 08 10:07:48 PM UTC 25
Peak memory 245796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982619727 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3982619727 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_edn_timeout_error.2557436989
Short name T242
Test name
Test status
Simulation time 1063377244 ps
CPU time 48.74 seconds
Started Feb 08 10:09:08 PM UTC 25
Finished Feb 08 10:09:58 PM UTC 25
Peak memory 235156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557436989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2557436989 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_mode_error.2804634625
Short name T240
Test name
Test status
Simulation time 38567608 ps
CPU time 1.52 seconds
Started Feb 08 10:09:14 PM UTC 25
Finished Feb 08 10:09:16 PM UTC 25
Peak memory 227180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804634625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.2804634625 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_ready_error.145471746
Short name T173
Test name
Test status
Simulation time 12713834667 ps
CPU time 76.03 seconds
Started Feb 08 10:09:17 PM UTC 25
Finished Feb 08 10:10:35 PM UTC 25
Peak memory 233708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145471746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_en
tropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.145471746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_entropy_refresh.2747930709
Short name T243
Test name
Test status
Simulation time 17858494444 ps
CPU time 130.71 seconds
Started Feb 08 10:08:24 PM UTC 25
Finished Feb 08 10:10:37 PM UTC 25
Peak memory 303208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747930709 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2747930709 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_error.2784165233
Short name T29
Test name
Test status
Simulation time 3640371224 ps
CPU time 349.54 seconds
Started Feb 08 10:09:00 PM UTC 25
Finished Feb 08 10:14:55 PM UTC 25
Peak memory 325604 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784165233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 7.kmac_error.2784165233 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_key_error.2734326813
Short name T239
Test name
Test status
Simulation time 559088780 ps
CPU time 9.15 seconds
Started Feb 08 10:09:03 PM UTC 25
Finished Feb 08 10:09:13 PM UTC 25
Peak memory 227212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734326813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.kmac_key_error.2734326813 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_lc_escalation.637555349
Short name T33
Test name
Test status
Simulation time 82667535 ps
CPU time 2.16 seconds
Started Feb 08 10:09:22 PM UTC 25
Finished Feb 08 10:09:25 PM UTC 25
Peak memory 231468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637555349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.637555349 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_long_msg_and_output.4208040552
Short name T292
Test name
Test status
Simulation time 50732620562 ps
CPU time 1452.73 seconds
Started Feb 08 10:06:11 PM UTC 25
Finished Feb 08 10:30:40 PM UTC 25
Peak memory 950052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208040552 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.4208040552 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_mubi.31406766
Short name T238
Test name
Test status
Simulation time 1561776229 ps
CPU time 11.18 seconds
Started Feb 08 10:08:54 PM UTC 25
Finished Feb 08 10:09:07 PM UTC 25
Peak memory 250092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31406766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mub
i_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.kmac_mubi.31406766 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_sideload.1648250282
Short name T230
Test name
Test status
Simulation time 3646331925 ps
CPU time 70.1 seconds
Started Feb 08 10:06:11 PM UTC 25
Finished Feb 08 10:07:23 PM UTC 25
Peak memory 257964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648250282 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.1648250282 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_smoke.1715025369
Short name T194
Test name
Test status
Simulation time 3867852387 ps
CPU time 119.11 seconds
Started Feb 08 10:05:08 PM UTC 25
Finished Feb 08 10:07:10 PM UTC 25
Peak memory 235608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715025369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 7.kmac_smoke.1715025369 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_test_vectors_kmac.2089729222
Short name T233
Test name
Test status
Simulation time 149596178 ps
CPU time 8.14 seconds
Started Feb 08 10:07:49 PM UTC 25
Finished Feb 08 10:07:58 PM UTC 25
Peak memory 229580 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2089729222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 7.kmac_test_vectors_kmac.2089729222 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_test_vectors_kmac_xof.415267580
Short name T234
Test name
Test status
Simulation time 113003623 ps
CPU time 7.36 seconds
Started Feb 08 10:07:59 PM UTC 25
Finished Feb 08 10:08:07 PM UTC 25
Peak memory 229424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=415267580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 7.kmac_test_vectors_kmac_xof.415267580 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_test_vectors_sha3_224.825492590
Short name T361
Test name
Test status
Simulation time 364328809263 ps
CPU time 3242.63 seconds
Started Feb 08 10:06:24 PM UTC 25
Finished Feb 08 11:01:01 PM UTC 25
Peak memory 3235716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825492590 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.825492590 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_test_vectors_sha3_256.78120986
Short name T360
Test name
Test status
Simulation time 90340343243 ps
CPU time 3228.35 seconds
Started Feb 08 10:06:28 PM UTC 25
Finished Feb 08 11:00:53 PM UTC 25
Peak memory 3018644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78120986 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/km
ac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.78120986 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_test_vectors_sha3_384.979368308
Short name T327
Test name
Test status
Simulation time 99211858688 ps
CPU time 2221.47 seconds
Started Feb 08 10:06:36 PM UTC 25
Finished Feb 08 10:44:02 PM UTC 25
Peak memory 2432816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979368308 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.979368308 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_test_vectors_sha3_512.1619017320
Short name T290
Test name
Test status
Simulation time 103359936879 ps
CPU time 1388.07 seconds
Started Feb 08 10:07:11 PM UTC 25
Finished Feb 08 10:30:34 PM UTC 25
Peak memory 1736584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619017320 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.1619017320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_test_vectors_shake_128.1484029344
Short name T558
Test name
Test status
Simulation time 369757375887 ps
CPU time 7928.91 seconds
Started Feb 08 10:07:24 PM UTC 25
Finished Feb 09 12:20:57 AM UTC 25
Peak memory 7901144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484029344 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.1484029344 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/7.kmac_test_vectors_shake_256.1869480105
Short name T415
Test name
Test status
Simulation time 212322041191 ps
CPU time 4528.27 seconds
Started Feb 08 10:07:47 PM UTC 25
Finished Feb 08 11:24:02 PM UTC 25
Peak memory 2266948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869480105 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.1869480105 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_alert_test.73337560
Short name T260
Test name
Test status
Simulation time 47942138 ps
CPU time 1.27 seconds
Started Feb 08 10:17:58 PM UTC 25
Finished Feb 08 10:18:00 PM UTC 25
Peak memory 225636 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73337560 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.73337560 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_app.2057955605
Short name T268
Test name
Test status
Simulation time 21645284788 ps
CPU time 405.4 seconds
Started Feb 08 10:14:26 PM UTC 25
Finished Feb 08 10:21:17 PM UTC 25
Peak memory 446380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057955605 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2057955605 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_app_with_partial_data.3660631379
Short name T265
Test name
Test status
Simulation time 57169014752 ps
CPU time 325.12 seconds
Started Feb 08 10:14:56 PM UTC 25
Finished Feb 08 10:20:25 PM UTC 25
Peak memory 440280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660631379 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.3660631379 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_burst_write.1232419125
Short name T294
Test name
Test status
Simulation time 21806840778 ps
CPU time 1203.72 seconds
Started Feb 08 10:10:35 PM UTC 25
Finished Feb 08 10:30:53 PM UTC 25
Peak memory 264288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232419125 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.1232419125 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_edn_timeout_error.2671141469
Short name T258
Test name
Test status
Simulation time 565287340 ps
CPU time 27.84 seconds
Started Feb 08 10:17:26 PM UTC 25
Finished Feb 08 10:17:55 PM UTC 25
Peak memory 235108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671141469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2671141469 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_mode_error.3809009442
Short name T256
Test name
Test status
Simulation time 1342993460 ps
CPU time 12.75 seconds
Started Feb 08 10:17:26 PM UTC 25
Finished Feb 08 10:17:40 PM UTC 25
Peak memory 235104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809009442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.3809009442 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_ready_error.3171044434
Short name T259
Test name
Test status
Simulation time 3445310103 ps
CPU time 15.5 seconds
Started Feb 08 10:17:41 PM UTC 25
Finished Feb 08 10:17:57 PM UTC 25
Peak memory 235456 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171044434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
ntropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.3171044434 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_entropy_refresh.717239334
Short name T267
Test name
Test status
Simulation time 14084638154 ps
CPU time 323.16 seconds
Started Feb 08 10:15:01 PM UTC 25
Finished Feb 08 10:20:28 PM UTC 25
Peak memory 493528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717239334 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_
masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.717239334 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_error.2368324360
Short name T30
Test name
Test status
Simulation time 7490420357 ps
CPU time 427.12 seconds
Started Feb 08 10:16:01 PM UTC 25
Finished Feb 08 10:23:14 PM UTC 25
Peak memory 382888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368324360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
rror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 8.kmac_error.2368324360 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_key_error.2454817573
Short name T255
Test name
Test status
Simulation time 5335756207 ps
CPU time 14.06 seconds
Started Feb 08 10:17:09 PM UTC 25
Finished Feb 08 10:17:25 PM UTC 25
Peak memory 229332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454817573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.kmac_key_error.2454817573 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_lc_escalation.4189410696
Short name T55
Test name
Test status
Simulation time 50826476 ps
CPU time 3.09 seconds
Started Feb 08 10:17:46 PM UTC 25
Finished Feb 08 10:17:50 PM UTC 25
Peak memory 233708 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189410696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_l
c_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.4189410696 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_mubi.2638394650
Short name T261
Test name
Test status
Simulation time 29316724219 ps
CPU time 244.43 seconds
Started Feb 08 10:15:22 PM UTC 25
Finished Feb 08 10:19:30 PM UTC 25
Peak memory 381420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638394650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_m
ubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 8.kmac_mubi.2638394650 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_sideload.987381412
Short name T263
Test name
Test status
Simulation time 38964684199 ps
CPU time 553.96 seconds
Started Feb 08 10:10:13 PM UTC 25
Finished Feb 08 10:19:34 PM UTC 25
Peak memory 616416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987381412 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_maske
d-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.987381412 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_smoke.2503586736
Short name T195
Test name
Test status
Simulation time 9636313329 ps
CPU time 38.44 seconds
Started Feb 08 10:09:32 PM UTC 25
Finished Feb 08 10:10:12 PM UTC 25
Peak memory 231544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503586736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 8.kmac_smoke.2503586736 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_stress_all.2422286271
Short name T297
Test name
Test status
Simulation time 28969990606 ps
CPU time 800.02 seconds
Started Feb 08 10:17:51 PM UTC 25
Finished Feb 08 10:31:20 PM UTC 25
Peak memory 623008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422286271 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2422286271 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_test_vectors_kmac.2619699920
Short name T248
Test name
Test status
Simulation time 233468966 ps
CPU time 8.58 seconds
Started Feb 08 10:14:05 PM UTC 25
Finished Feb 08 10:14:15 PM UTC 25
Peak memory 229412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2619699920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.kmac_test_vectors_kmac.2619699920 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_test_vectors_kmac_xof.3923848145
Short name T249
Test name
Test status
Simulation time 116780569 ps
CPU time 7.66 seconds
Started Feb 08 10:14:16 PM UTC 25
Finished Feb 08 10:14:25 PM UTC 25
Peak memory 235492 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3923848145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 8.kmac_test_vectors_kmac_xof.3923848145 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_test_vectors_sha3_224.4062678964
Short name T365
Test name
Test status
Simulation time 497672573094 ps
CPU time 3225.9 seconds
Started Feb 08 10:10:38 PM UTC 25
Finished Feb 08 11:05:00 PM UTC 25
Peak memory 3250072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062678964 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.4062678964 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_test_vectors_sha3_256.743772322
Short name T372
Test name
Test status
Simulation time 369377808250 ps
CPU time 3421.01 seconds
Started Feb 08 10:10:45 PM UTC 25
Finished Feb 08 11:08:28 PM UTC 25
Peak memory 3082256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743772322 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.743772322 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_test_vectors_sha3_384.1031493843
Short name T316
Test name
Test status
Simulation time 15807976176 ps
CPU time 1652.75 seconds
Started Feb 08 10:12:54 PM UTC 25
Finished Feb 08 10:40:45 PM UTC 25
Peak memory 960416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031493843 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.1031493843 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_test_vectors_sha3_512.989436694
Short name T322
Test name
Test status
Simulation time 128302260741 ps
CPU time 1690.4 seconds
Started Feb 08 10:12:58 PM UTC 25
Finished Feb 08 10:41:29 PM UTC 25
Peak memory 1679192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989436694 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/k
mac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.989436694 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_test_vectors_shake_128.3439971645
Short name T616
Test name
Test status
Simulation time 264243700176 ps
CPU time 9220.87 seconds
Started Feb 08 10:13:19 PM UTC 25
Finished Feb 09 12:48:33 AM UTC 25
Peak memory 7882664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439971645 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.3439971645 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/8.kmac_test_vectors_shake_256.3552546736
Short name T430
Test name
Test status
Simulation time 207920969713 ps
CPU time 4539.39 seconds
Started Feb 08 10:13:46 PM UTC 25
Finished Feb 08 11:30:14 PM UTC 25
Peak memory 2215828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552546736 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.3552546736 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_test_vectors_shake_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_alert_test.196934016
Short name T284
Test name
Test status
Simulation time 20237551 ps
CPU time 1.35 seconds
Started Feb 08 10:28:26 PM UTC 25
Finished Feb 08 10:28:28 PM UTC 25
Peak memory 225644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196934016 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.196934016 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_app.1679611953
Short name T276
Test name
Test status
Simulation time 11565009055 ps
CPU time 216.36 seconds
Started Feb 08 10:23:31 PM UTC 25
Finished Feb 08 10:27:11 PM UTC 25
Peak memory 346204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679611953 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.1679611953 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_app/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_app_with_partial_data.713036256
Short name T275
Test name
Test status
Simulation time 10533033865 ps
CPU time 176.12 seconds
Started Feb 08 10:23:36 PM UTC 25
Finished Feb 08 10:26:35 PM UTC 25
Peak memory 325532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713036256 -assert nopostproc +UVM_TESTNAME=kmac_ba
se_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.713036256 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_burst_write.3866718806
Short name T274
Test name
Test status
Simulation time 9341624113 ps
CPU time 315.02 seconds
Started Feb 08 10:19:36 PM UTC 25
Finished Feb 08 10:24:55 PM UTC 25
Peak memory 239588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866718806 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3866718806 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_burst_write/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_edn_timeout_error.205636700
Short name T279
Test name
Test status
Simulation time 47395266 ps
CPU time 1.37 seconds
Started Feb 08 10:27:18 PM UTC 25
Finished Feb 08 10:27:21 PM UTC 25
Peak memory 225652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205636700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.205636700 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_mode_error.3508629746
Short name T280
Test name
Test status
Simulation time 529568684 ps
CPU time 23.42 seconds
Started Feb 08 10:27:20 PM UTC 25
Finished Feb 08 10:27:45 PM UTC 25
Peak memory 235080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508629746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3508629746 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_ready_error.2268788219
Short name T287
Test name
Test status
Simulation time 6934781144 ps
CPU time 114.72 seconds
Started Feb 08 10:27:21 PM UTC 25
Finished Feb 08 10:29:18 PM UTC 25
Peak memory 235440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268788219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_e
ntropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2268788219 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_entropy_refresh.3063171020
Short name T282
Test name
Test status
Simulation time 7611127574 ps
CPU time 211.73 seconds
Started Feb 08 10:24:27 PM UTC 25
Finished Feb 08 10:28:02 PM UTC 25
Peak memory 290724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063171020 -assert nopostproc +UVM_TESTNAME=kmac_b
ase_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac
_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3063171020 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_error.418514775
Short name T310
Test name
Test status
Simulation time 6415829401 ps
CPU time 639.3 seconds
Started Feb 08 10:26:36 PM UTC 25
Finished Feb 08 10:37:24 PM UTC 25
Peak memory 405404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418514775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_er
ror_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 9.kmac_error.418514775 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_key_error.3497613034
Short name T278
Test name
Test status
Simulation time 1411417541 ps
CPU time 6.3 seconds
Started Feb 08 10:27:12 PM UTC 25
Finished Feb 08 10:27:19 PM UTC 25
Peak memory 227164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497613034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_k
ey_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.kmac_key_error.3497613034 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_key_error/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_lc_escalation.852863559
Short name T281
Test name
Test status
Simulation time 102150062 ps
CPU time 2.09 seconds
Started Feb 08 10:27:46 PM UTC 25
Finished Feb 08 10:27:50 PM UTC 25
Peak memory 233436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852863559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc
_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.852863559 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_long_msg_and_output.308320248
Short name T393
Test name
Test status
Simulation time 239906189430 ps
CPU time 3353.84 seconds
Started Feb 08 10:19:31 PM UTC 25
Finished Feb 08 11:16:01 PM UTC 25
Peak memory 3573676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308320248 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.308320248 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_mubi.904719962
Short name T277
Test name
Test status
Simulation time 9081189122 ps
CPU time 138.33 seconds
Started Feb 08 10:24:57 PM UTC 25
Finished Feb 08 10:27:17 PM UTC 25
Peak memory 319832 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904719962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mu
bi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 9.kmac_mubi.904719962 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_mubi/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_sideload.2220270376
Short name T269
Test name
Test status
Simulation time 3109422392 ps
CPU time 137.89 seconds
Started Feb 08 10:19:34 PM UTC 25
Finished Feb 08 10:21:55 PM UTC 25
Peak memory 266148 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220270376 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mask
ed-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.2220270376 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_sideload/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_smoke.478748158
Short name T264
Test name
Test status
Simulation time 66237987484 ps
CPU time 101.35 seconds
Started Feb 08 10:18:01 PM UTC 25
Finished Feb 08 10:19:44 PM UTC 25
Peak memory 235372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478748158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 9.kmac_smoke.478748158 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_stress_all.2200303804
Short name T337
Test name
Test status
Simulation time 46358500895 ps
CPU time 1218.89 seconds
Started Feb 08 10:27:50 PM UTC 25
Finished Feb 08 10:48:23 PM UTC 25
Peak memory 383384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspaces/repo/scratch/os_
regression/kmac_masked-sim-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200303804 -assert nopostproc +UVM_TESTNAME=kmac_
base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_mas
ked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.2200303804 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_test_vectors_kmac.3499540320
Short name T270
Test name
Test status
Simulation time 766035014 ps
CPU time 8.64 seconds
Started Feb 08 10:23:15 PM UTC 25
Finished Feb 08 10:23:25 PM UTC 25
Peak memory 229420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=3499540320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.kmac_test_vectors_kmac.3499540320 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_kmac/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_test_vectors_kmac_xof.2258018461
Short name T272
Test name
Test status
Simulation time 127321875 ps
CPU time 7.75 seconds
Started Feb 08 10:23:26 PM UTC 25
Finished Feb 08 10:23:35 PM UTC 25
Peak memory 229400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/h
w/dv/tools/sim.tcl +ntb_random_seed=2258018461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 9.kmac_test_vectors_kmac_xof.2258018461 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_kmac_xof/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_test_vectors_sha3_224.1041816084
Short name T363
Test name
Test status
Simulation time 65015410583 ps
CPU time 2511.95 seconds
Started Feb 08 10:19:46 PM UTC 25
Finished Feb 08 11:02:04 PM UTC 25
Peak memory 3211088 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041816084 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1041816084 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_sha3_224/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_test_vectors_sha3_256.2618708902
Short name T383
Test name
Test status
Simulation time 247260600949 ps
CPU time 3084.1 seconds
Started Feb 08 10:20:27 PM UTC 25
Finished Feb 08 11:12:25 PM UTC 25
Peak memory 3071840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618708902 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.2618708902 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_sha3_256/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_test_vectors_sha3_384.3507200359
Short name T342
Test name
Test status
Simulation time 22233431882 ps
CPU time 1901.88 seconds
Started Feb 08 10:20:29 PM UTC 25
Finished Feb 08 10:52:34 PM UTC 25
Peak memory 925336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507200359 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.3507200359 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_sha3_384/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_test_vectors_sha3_512.3240638216
Short name T314
Test name
Test status
Simulation time 10882413828 ps
CPU time 1136.13 seconds
Started Feb 08 10:20:29 PM UTC 25
Finished Feb 08 10:39:38 PM UTC 25
Peak memory 714480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240638216 -assert nopostproc +UVM_TESTNAME=kmac
_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/
kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.3240638216 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_sha3_512/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_test_vectors_shake_128.1543308640
Short name T533
Test name
Test status
Simulation time 64603280133 ps
CPU time 6493.64 seconds
Started Feb 08 10:21:17 PM UTC 25
Finished Feb 09 12:10:43 AM UTC 25
Peak memory 2709404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543308640 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.1543308640 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_shake_128/latest

Test location /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/coverage/default/9.kmac_test_vectors_shake_256.2127692476
Short name T476
Test name
Test status
Simulation time 71976277686 ps
CPU time 5091.23 seconds
Started Feb 08 10:21:55 PM UTC 25
Finished Feb 08 11:47:42 PM UTC 25
Peak memory 2228116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/d
efault/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127692476 -assert nopostproc +UVM_TESTNAME=kma
c_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.2127692476 +enable_masking=1 +sw_key_masked=0
Directory /workspaces/repo/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_shake_256/latest
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