KMAC/UNMASKED Simulation Results

Tuesday May 16 2023 07:02:31 UTC

GitHub Revision: `50278df8b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1341560578

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.110m	17.647ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.100s	105.623us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.180s	30.025us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.320s	1.570ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.200s	615.856us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.410s	137.103us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.180s	30.025us	20	20	100.00
		kmac_csr_aliasing	11.200s	615.856us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	34.460us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	43.978us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	43.161m	185.381ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.128m	81.639ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.125m	201.083ms	50	50	100.00
		kmac_test_vectors_sha3_256	37.391m	1.032s	50	50	100.00
		kmac_test_vectors_sha3_384	28.057m	874.594ms	50	50	100.00
		kmac_test_vectors_sha3_512	18.630m	209.233ms	50	50	100.00
		kmac_test_vectors_shake_128	1.511h	1.188s	50	50	100.00
		kmac_test_vectors_shake_256	1.288h	1.351s	50	50	100.00
		kmac_test_vectors_kmac	5.420s	1.103ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.180s	642.108us	50	50	100.00
V2	sideload	kmac_sideload	7.417m	22.223ms	50	50	100.00
V2	app	kmac_app	5.507m	18.588ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.183m	28.686ms	8	10	80.00
V2	entropy_refresh	kmac_entropy_refresh	5.327m	190.216ms	48	50	96.00
V2	error	kmac_error	7.071m	76.728ms	50	50	100.00
V2	key_error	kmac_key_error	8.800s	5.890ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.580s	5.953ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	44.580s	10.613ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.071m	27.650ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	24.660s	1.687ms	50	50	100.00
V2	stress_all	kmac_stress_all	34.284m	98.535ms	48	50	96.00
V2	intr_test	kmac_intr_test	1.030s	12.620us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	44.205us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.190s	103.969us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.190s	103.969us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.100s	105.623us	5	5	100.00
		kmac_csr_rw	1.180s	30.025us	20	20	100.00
		kmac_csr_aliasing	11.200s	615.856us	5	5	100.00
		kmac_same_csr_outstanding	2.690s	235.477us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.100s	105.623us	5	5	100.00
		kmac_csr_rw	1.180s	30.025us	20	20	100.00
		kmac_csr_aliasing	11.200s	615.856us	5	5	100.00
		kmac_same_csr_outstanding	2.690s	235.477us	20	20	100.00
V2		TOTAL			1038	1050	98.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.900s	74.369us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.900s	74.369us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.900s	74.369us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.900s	74.369us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.630s	1.355ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.316m	24.030ms	5	5	100.00
		kmac_tl_intg_err	5.920s	504.763us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.920s	504.763us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	24.660s	1.687ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.110m	17.647ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.417m	22.223ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.900s	74.369us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.316m	24.030ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.316m	24.030ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.316m	24.030ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.110m	17.647ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	24.660s	1.687ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.316m	24.030ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.865m	57.426ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.110m	17.647ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	46.968m	112.021ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1266	1290	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.46	96.65	92.55	100.00	88.64	94.67	98.82	96.88

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 12 failures:

Test kmac_stress_all_with_rand_reset has 12 failures.

1.kmac_stress_all_with_rand_reset.1351464221
Line 261, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 559088050 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 559088050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_stress_all_with_rand_reset.1340810224
Line 269, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5536715880 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5536715880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 7 failures:

Test kmac_stress_all has 2 failures.

4.kmac_stress_all.3770227712
Line 535, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all/latest/run.log

  UVM_FATAL @ 80493453489 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (255 [0xff] vs 95 [0x5f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 80493453489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_stress_all.3266491340
Line 421, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_stress_all/latest/run.log

  UVM_FATAL @ 64418491569 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (10 [0xa] vs 98 [0x62]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 64418491569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app_with_partial_data has 2 failures.

6.kmac_app_with_partial_data.4273735463
Line 342, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 15590015557 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (231 [0xe7] vs 252 [0xfc]) Mismatch between unmasked_digest[1] and dpi_digest[1]
  UVM_INFO @ 15590015557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_app_with_partial_data.1466628843
Line 245, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/7.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 2618886981 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (207 [0xcf] vs 31 [0x1f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2618886981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

28.kmac_app.1089652749
Line 224, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_app/latest/run.log

  UVM_FATAL @ 1561411006 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (124 [0x7c] vs 159 [0x9f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1561411006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.kmac_app.3337505864
Line 248, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/45.kmac_app/latest/run.log

  UVM_FATAL @ 2687582579 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (246 [0xf6] vs 74 [0x4a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2687582579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

48.kmac_entropy_refresh.2174217076
Line 227, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/48.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 4071746073 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (55 [0x37] vs 207 [0xcf]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4071746073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:

Test kmac_burst_write has 3 failures.

28.kmac_burst_write.2423932473
Line 268, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.kmac_burst_write.2051366610
Line 297, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_entropy_refresh has 1 failures.

40.kmac_entropy_refresh.3158204569
Line 373, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/40.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

42.kmac_app.23691582
Line 368, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/42.kmac_app/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---