12e3b8572e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.636m | 40.785ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.760s | 36.793us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.490s | 17.266us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 19.560s | 1.872ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 9.970s | 382.533us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 3.020s | 86.844us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.490s | 17.266us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 9.970s | 382.533us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 1.080s | 15.042us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.920s | 34.442us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 1.326h | 526.196ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 18.922m | 67.530ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 47.295m | 370.447ms | 5 | 5 | 100.00 |
| kmac_test_vectors_sha3_256 | 41.835m | 88.898ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 24.468m | 42.968ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 26.540s | 2.202ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_128 | 49.361m | 325.184ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_shake_256 | 45.247m | 869.479ms | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac | 3.350s | 42.552us | 5 | 5 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 3.720s | 83.397us | 5 | 5 | 100.00 | ||
| V2 | sideload | kmac_sideload | 8.773m | 18.605ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 7.010m | 97.326ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 4.131m | 30.316ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.217m | 66.957ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 8.351m | 14.434ms | 50 | 50 | 100.00 |
| V2 | key_error | kmac_key_error | 19.730s | 3.930ms | 49 | 50 | 98.00 |
| V2 | sideload_invalid | kmac_sideload_invalid | 2.562m | 10.011ms | 38 | 50 | 76.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 47.990s | 6.389ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 54.130s | 6.980ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.357m | 19.328ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 1.422m | 2.024ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 41.791m | 140.401ms | 50 | 50 | 100.00 |
| V2 | intr_test | kmac_intr_test | 1.180s | 34.945us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 1.360s | 85.859us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 4.710s | 1.476ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 4.710s | 1.476ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.760s | 36.793us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.490s | 17.266us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.970s | 382.533us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.900s | 506.800us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.760s | 36.793us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.490s | 17.266us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.970s | 382.533us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.900s | 506.800us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 727 | 740 | 98.24 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 2.480s | 131.164us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 2.480s | 131.164us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 2.480s | 131.164us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 2.480s | 131.164us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.280s | 458.077us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 1.671m | 6.127ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 6.660s | 378.739us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 6.660s | 378.739us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 1.422m | 2.024ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.636m | 40.785ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.773m | 18.605ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 2.480s | 131.164us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 1.671m | 6.127ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 1.671m | 6.127ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 1.671m | 6.127ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.636m | 40.785ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 1.422m | 2.024ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 1.671m | 6.127ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.978m | 17.202ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.636m | 40.785ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 4.133m | 3.582ms | 2 | 10 | 20.00 |
| V3 | TOTAL | 2 | 10 | 20.00 | |||
| TOTAL | 919 | 940 | 97.77 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 26 | 26 | 24 | 92.31 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 93.15 | 96.19 | 92.52 | 100.00 | 73.55 | 94.61 | 99.03 | 96.15 |
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
4.kmac_stress_all_with_rand_reset.41687352418889705422688313953924853685186411412471901205637776163964705255671
Line 173, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2582924199 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
UVM_INFO @ 2582924199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.kmac_stress_all_with_rand_reset.54553950078374808934221365524034337945055166983475937912062700947745896010080
Line 234, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4119481191 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
UVM_INFO @ 4119481191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
0.kmac_stress_all_with_rand_reset.17496469283628565188766026043628428547828106264183147039549239091733504072509
Line 91, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5805987277 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5805987277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.kmac_stress_all_with_rand_reset.4991873357000261089987183132919372344198265905000780414544437429409346032681
Line 107, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3741710187 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3741710187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:
7.kmac_sideload_invalid.33498730226513986843222638417346475451185158582317809181562354079582874514948
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10011282592 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6259e000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10011282592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.kmac_sideload_invalid.27154573017439144796462090576736806971972553778489789001824653339680354280261
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10011359344 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x761f5000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
UVM_INFO @ 10011359344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
27.kmac_sideload_invalid.34871141829224685338853612727993337177573637263788556982163474680828662723708
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10037085957 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9beb4000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10037085957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.kmac_sideload_invalid.33527212463005168167515702896129075896853256259004235433022957962507361865672
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10159849006 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xddd23000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
UVM_INFO @ 10159849006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
11.kmac_key_error.99988119493430657223279326451727155433951908506444564945112267340688716206012
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/11.kmac_key_error/latest/run.log
UVM_ERROR @ 120341943 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 120341943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
13.kmac_sideload_invalid.96386907942316846229914045064755961214004536491263249698649370060841695958743
Line 76, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10217729977 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb4537000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
UVM_INFO @ 10217729977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
30.kmac_sideload_invalid.103724244407205921999643910336641663784043714562009564103008979648477829046727
Line 80, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/30.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10160386423 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x22cd8000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
UVM_INFO @ 10160386423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
32.kmac_sideload_invalid.98919072143497337289416891820142267652439420336596595622295749794081902865468
Line 110, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/32.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10787329537 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb3d3e000, Comparison=CompareOpEq, exp_data=0x1, call_count=27)
UVM_INFO @ 10787329537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
41.kmac_sideload_invalid.45725711813658134478049594564575914926320099589094778748719511179701790697200
Line 80, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/41.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10285948961 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x45ad6000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
UVM_INFO @ 10285948961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=29) has 1 failures:
42.kmac_sideload_invalid.103147382066495351925912304662011446330898810471204835485687512905141022595431
Line 108, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10179543007 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb1fa000, Comparison=CompareOpEq, exp_data=0x1, call_count=29)
UVM_INFO @ 10179543007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
43.kmac_sideload_invalid.114185469622182091989683053067260028878429683515937991803063360748627011680195
Line 70, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10064158603 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8e1d4000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
UVM_INFO @ 10064158603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
45.kmac_sideload_invalid.96514472775627135070355145040530504313137430353563628946719070346293205453557
Line 96, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/45.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10379766978 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3215a000, Comparison=CompareOpEq, exp_data=0x1, call_count=21)
UVM_INFO @ 10379766978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
49.kmac_sideload_invalid.51631120265077216404794172579179668898966584079134552583008242524836068368086
Line 104, in log /workspaces/repo/scratch/os_regression_2024_10_14/kmac_unmasked-sim-vcs/49.kmac_sideload_invalid/latest/run.log
UVM_FATAL @ 10285325167 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd8dd5000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
UVM_INFO @ 10285325167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---