KMAC/UNMASKED Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.122m	54.535ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	227.587us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	32.967us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.930s	5.684ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.920s	759.328us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.380s	136.457us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	32.967us	20	20	100.00
		kmac_csr_aliasing	7.920s	759.328us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	19.764us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.540s	47.518us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.567m	1.176s	50	50	100.00
V2	burst_write	kmac_burst_write	14.303m	77.151ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.841m	330.539ms	50	50	100.00
		kmac_test_vectors_sha3_256	41.133m	1.849s	50	50	100.00
		kmac_test_vectors_sha3_384	26.814m	480.309ms	50	50	100.00
		kmac_test_vectors_sha3_512	16.878m	49.672ms	50	50	100.00
		kmac_test_vectors_shake_128	1.564h	1.057s	50	50	100.00
		kmac_test_vectors_shake_256	1.324h	893.351ms	50	50	100.00
		kmac_test_vectors_kmac	6.400s	4.568ms	50	50	100.00
		kmac_test_vectors_kmac_xof	6.380s	3.952ms	50	50	100.00
V2	sideload	kmac_sideload	7.179m	85.221ms	50	50	100.00
V2	app	kmac_app	4.540m	46.308ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.150m	98.243ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.485m	20.051ms	50	50	100.00
V2	error	kmac_error	6.579m	23.562ms	50	50	100.00
V2	key_error	kmac_key_error	10.060s	14.701ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.360s	2.463ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.860s	2.424ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.066m	14.152ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	48.400s	8.064ms	50	50	100.00
V2	stress_all	kmac_stress_all	37.862m	579.639ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.890s	17.027us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	142.320us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.530s	557.020us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.530s	557.020us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	227.587us	5	5	100.00
		kmac_csr_rw	1.190s	32.967us	20	20	100.00
		kmac_csr_aliasing	7.920s	759.328us	5	5	100.00
		kmac_same_csr_outstanding	2.830s	722.112us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	227.587us	5	5	100.00
		kmac_csr_rw	1.190s	32.967us	20	20	100.00
		kmac_csr_aliasing	7.920s	759.328us	5	5	100.00
		kmac_same_csr_outstanding	2.830s	722.112us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.430s	50.171us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.430s	50.171us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.430s	50.171us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.430s	50.171us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.040s	508.613us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.081m	9.567ms	5	5	100.00
		kmac_tl_intg_err	5.270s	928.924us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.270s	928.924us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	48.400s	8.064ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.122m	54.535ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.179m	85.221ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.430s	50.171us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.081m	9.567ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.081m	9.567ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.081m	9.567ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.122m	54.535ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	48.400s	8.064ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.081m	9.567ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.987m	12.602ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.122m	54.535ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	22.241m	80.992ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1238	1250	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	24	96.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.11	95.89	92.27	100.00	66.94	94.11	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 1.kmac_stress_all_with_rand_reset.65577428797241062644752635601822096356802456780784673758757690522508956572787
    Line 261, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2803963349 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2803963349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.kmac_stress_all_with_rand_reset.83418207734852986609106648996039749730029364972476293385582581566278633807353
    Line 633, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30137761865 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30137761865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_mubi has 1 failures.

5.kmac_mubi.63577261964928331675393730124574346264976444924978489089022776075670121825082
Line 777, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_mubi/latest/run.log

  UVM_FATAL @ 3096492042 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (64 [0x40] vs 130 [0x82]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3096492042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

27.kmac_stress_all.45927036254625437781166493696620949639023596995323607961697339253620558084895
Line 903, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/27.kmac_stress_all/latest/run.log

  UVM_FATAL @ 28882066948 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (204 [0xcc] vs 5 [0x5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 28882066948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.kmac_stress_all.93927780409843165708396596083069594541338911259580690181696523011374602188735
Line 569, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/31.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2208261420 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (75 [0x4b] vs 27 [0x1b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2208261420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 2.kmac_stress_all_with_rand_reset.32408575680631956173548171621694476324147046883654754170484017050407177595665
    Line 1142, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120120799908 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 120120799908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```