KMAC/UNMASKED Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.093m	29.936ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	30.727us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.240s	35.242us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.370s	5.053ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.020s	2.836ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.750s	152.324us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.240s	35.242us	20	20	100.00
		kmac_csr_aliasing	10.020s	2.836ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	11.149us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.420s	152.477us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.967m	255.362ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.731m	98.409ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.347m	1.411s	50	50	100.00
		kmac_test_vectors_sha3_256	33.768m	375.304ms	50	50	100.00
		kmac_test_vectors_sha3_384	25.313m	410.575ms	50	50	100.00
		kmac_test_vectors_sha3_512	16.697m	171.314ms	50	50	100.00
		kmac_test_vectors_shake_128	1.725h	3.282s	50	50	100.00
		kmac_test_vectors_shake_256	1.405h	2.379s	50	50	100.00
		kmac_test_vectors_kmac	5.730s	1.604ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.550s	1.521ms	50	50	100.00
V2	sideload	kmac_sideload	6.906m	62.945ms	50	50	100.00
V2	app	kmac_app	5.577m	12.183ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.137m	40.088ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.853m	104.447ms	50	50	100.00
V2	error	kmac_error	6.228m	19.659ms	50	50	100.00
V2	key_error	kmac_key_error	6.830s	2.687ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	33.190s	3.016ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	36.880s	1.353ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.090m	31.797ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	32.850s	982.308us	50	50	100.00
V2	stress_all	kmac_stress_all	44.051m	124.749ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.830s	16.289us	50	50	100.00
V2	alert_test	kmac_alert_test	0.890s	239.364us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.540s	626.070us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.540s	626.070us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	30.727us	5	5	100.00
		kmac_csr_rw	1.240s	35.242us	20	20	100.00
		kmac_csr_aliasing	10.020s	2.836ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	918.777us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	30.727us	5	5	100.00
		kmac_csr_rw	1.240s	35.242us	20	20	100.00
		kmac_csr_aliasing	10.020s	2.836ms	5	5	100.00
		kmac_same_csr_outstanding	2.670s	918.777us	20	20	100.00
V2		TOTAL			1048	1050	99.81
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.440s	295.971us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.440s	295.971us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.440s	295.971us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.440s	295.971us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.090s	191.369us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	53.710s	17.074ms	5	5	100.00
		kmac_tl_intg_err	5.130s	274.804us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.130s	274.804us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	32.850s	982.308us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.093m	29.936ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.906m	62.945ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.440s	295.971us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	53.710s	17.074ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	53.710s	17.074ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	53.710s	17.074ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.093m	29.936ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	32.850s	982.308us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	53.710s	17.074ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.456m	12.734ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.093m	29.936ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.572m	69.325ms	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			1245	1290	96.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.63	96.18	92.44	100.00	90.91	94.60	98.84	96.45

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:

  • Test kmac_stress_all_with_rand_reset has 37 failures.

    • 0.kmac_stress_all_with_rand_reset.22973731101038199984996020263584838834344150269578026000483901096594168986307
      Line 1019, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17787983462 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17787983462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.23610160361192394482432340126719964587494265566669383244584343615577727221576
      Line 598, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 90732719433 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 90732719433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 35 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:

  • Test kmac_stress_all_with_rand_reset has 5 failures.

    • 5.kmac_stress_all_with_rand_reset.107997780083177013031838548660307047505441702363083345876954882465294117803458
      Line 632, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14918657007 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 14918657007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.kmac_stress_all_with_rand_reset.50007452889548980951791147053895580512076842537356848820734170753516780052839
      Line 580, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 173581351049 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 173581351049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 2.kmac_stress_all_with_rand_reset.34023369701645288682708748898075967167341494948273597482220820659210003090454
      Line 1182, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 5477921419 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (205 [0xcd] vs 155 [0x9b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 5477921419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_app has 1 failures.

    • 4.kmac_app.56660484925299656047299937761966191170873607223110229947917919997092160384830
      Line 321, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_app/latest/run.log

        UVM_FATAL @ 13217267885 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (78 [0x4e] vs 61 [0x3d]) Mismatch between unmasked_digest[0] and dpi_digest[0]
        UVM_INFO @ 13217267885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_burst_write has 1 failures.

    • 4.kmac_burst_write.114416913158547284011833709550645672324311740340161913087845836815919529207352
      Line 782, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_burst_write/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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