KMAC/UNMASKED Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.465m	15.396ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.700s	31.870us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.720s	36.896us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	9.770s	522.949us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.590s	557.807us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.560s	89.929us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.720s	36.896us	20	20	100.00
		kmac_csr_aliasing	8.590s	557.807us	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.110s	14.821us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.740s	589.999us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.201h	121.756ms	50	50	100.00
V2	burst_write	kmac_burst_write	22.663m	135.652ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	57.443m	346.389ms	50	50	100.00
		kmac_test_vectors_sha3_256	50.629m	207.569ms	50	50	100.00
		kmac_test_vectors_sha3_384	42.014m	459.645ms	50	50	100.00
		kmac_test_vectors_sha3_512	27.310m	600.322ms	50	50	100.00
		kmac_test_vectors_shake_128	2.343h	1.594s	50	50	100.00
		kmac_test_vectors_shake_256	1.964h	228.970ms	50	50	100.00
		kmac_test_vectors_kmac	8.180s	1.064ms	50	50	100.00
		kmac_test_vectors_kmac_xof	9.090s	3.317ms	50	50	100.00
V2	sideload	kmac_sideload	9.357m	65.927ms	50	50	100.00
V2	app	kmac_app	7.754m	15.541ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.904m	49.973ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.376m	14.016ms	50	50	100.00
V2	error	kmac_error	9.221m	200.000ms	48	50	96.00
V2	key_error	kmac_key_error	20.100s	6.726ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	56.990s	4.476ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	48.640s	5.485ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.413m	6.368ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	33.680s	4.018ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.983m	105.220ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.220s	14.365us	50	50	100.00
V2	alert_test	kmac_alert_test	1.440s	78.171us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.220s	218.206us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.220s	218.206us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.700s	31.870us	5	5	100.00
		kmac_csr_rw	1.720s	36.896us	20	20	100.00
		kmac_csr_aliasing	8.590s	557.807us	5	5	100.00
		kmac_same_csr_outstanding	3.890s	455.720us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.700s	31.870us	5	5	100.00
		kmac_csr_rw	1.720s	36.896us	20	20	100.00
		kmac_csr_aliasing	8.590s	557.807us	5	5	100.00
		kmac_same_csr_outstanding	3.890s	455.720us	20	20	100.00
V2		TOTAL			1046	1050	99.62
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.980s	65.863us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.980s	65.863us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.980s	65.863us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.980s	65.863us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.070s	439.193us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.738m	21.327ms	5	5	100.00
		kmac_tl_intg_err	6.330s	877.293us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.330s	877.293us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	33.680s	4.018ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.465m	15.396ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.357m	65.927ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.980s	65.863us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.738m	21.327ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.738m	21.327ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.738m	21.327ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.465m	15.396ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	33.680s	4.018ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.738m	21.327ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.351m	28.326ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.465m	15.396ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	10.887m	59.322ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1235	1250	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	23	92.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.78	95.77	90.51	100.00	66.94	93.67	98.84	96.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 1.kmac_stress_all_with_rand_reset.30771852969532709574400116852042260406932914453790178383561639451437032607358
    Line 415, in log /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7846843672 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7846843672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.28213036228814469641720315221873537348278461307297844902888594954031569367180
    Line 90, in log /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 845863702 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 845863702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1638) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_stress_all_with_rand_reset has 1 failures.

0.kmac_stress_all_with_rand_reset.26245740008076321640262679044335805925198175466161892119389770822304673125059
Line 848, in log /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 23005235550 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (231 [0xe7] vs 16 [0x10]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 23005235550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 2 failures.

26.kmac_app.78630681152957620480924008417652701625299669329857302053224716662389046851319
Line 140, in log /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/26.kmac_app/latest/run.log

  UVM_FATAL @ 340950916 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (116 [0x74] vs 182 [0xb6]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 340950916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.kmac_app.37602570537895958912406995436600297806230309672566443247192747420742579683849
Line 132, in log /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_app/latest/run.log

  UVM_FATAL @ 833967026 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (112 [0x70] vs 172 [0xac]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 833967026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_error has 1 failures.

30.kmac_error.33618979329254934310104908730595806346740825386428577984549960152853965615696
Line 490, in log /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/30.kmac_error/latest/run.log

  UVM_FATAL @ 7757597793 ps: (kmac_scoreboard.sv:1638) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (111 [0x6f] vs 52 [0x34]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 7757597793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 5.kmac_shadow_reg_errors_with_csr_rw.25966134245781231132349398796380164344807605212738780742148959452288939316100
    Line 78, in log /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  24292558 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (259 [0x103] vs 0 [0x0]) Regname: kmac_reg_block.entropy_period reset value: 0x0
  UVM_INFO @  24292558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 13.kmac_error.109806228817065850428519497489824433838082510912253564778923767062226648940037
    Line 1064, in log /workspaces/repo/scratch/os_regression/kmac_unmasked-sim-vcs/13.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```