Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	238773875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

183061425

1

T1

955

T11

89

T12

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	222761015	1			T1	770		T11	61		T12	11
values[0x0]	95729020	1			T1	315		T11	31		T12	2
values[0x1]	103345265	1			T1	287		T11	30		T12	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	186384115	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

235451185

1

T1

1087

T11

100

T12

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1646605	1			T13	2		T92	28		T56	2
valid_sources[0x01]	1637120	1			T13	2		T92	12		T118	12
valid_sources[0x02]	1656420	1			T1	10		T11	5		T13	4
valid_sources[0x03]	1609540	1			T1	18		T92	39		T2	2
valid_sources[0x04]	1723015	1			T1	8		T13	1		T92	20
valid_sources[0x05]	1637525	1			T1	7		T13	2		T92	17
valid_sources[0x06]	1659305	1			T1	4		T92	11		T3	4
valid_sources[0x07]	1722225	1			T1	1		T92	33		T2	1
valid_sources[0x08]	1644775	1			T1	14		T12	1		T15	1
valid_sources[0x09]	1683105	1			T1	13		T92	23		T3	13
valid_sources[0x0a]	1715830	1			T1	14		T16	3		T92	37
valid_sources[0x0b]	1599885	1			T1	3		T13	6		T92	16
valid_sources[0x0c]	1628820	1			T1	11		T16	1		T92	24
valid_sources[0x0d]	1593570	1			T1	2		T13	1		T92	11
valid_sources[0x0e]	1646225	1			T1	10		T13	3		T92	14
valid_sources[0x0f]	1662160	1			T1	2		T92	52		T2	1
valid_sources[0x10]	1677905	1			T92	22		T118	22		T113	22
valid_sources[0x11]	1686425	1			T1	4		T92	22		T3	4
valid_sources[0x12]	1678940	1			T92	46		T118	46		T100	2
valid_sources[0x13]	1613455	1			T92	37		T2	1		T118	37
valid_sources[0x14]	1647375	1			T1	3		T92	35		T3	3
valid_sources[0x15]	1639310	1			T1	7		T92	31		T2	3
valid_sources[0x16]	1647625	1			T1	2		T16	2		T92	15
valid_sources[0x17]	1670750	1			T1	5		T19	4		T92	27
valid_sources[0x18]	1658985	1			T1	6		T13	3		T92	37
valid_sources[0x19]	1712260	1			T1	7		T16	3		T92	15
valid_sources[0x1a]	1693150	1			T1	11		T11	2		T14	2
valid_sources[0x1b]	1664460	1			T1	47		T11	3		T13	21
valid_sources[0x1c]	1636970	1			T1	12		T13	1		T92	31
valid_sources[0x1d]	1660840	1			T1	2		T13	4		T19	15
valid_sources[0x1e]	1655075	1			T13	9		T19	3		T92	23
valid_sources[0x1f]	1656750	1			T1	2		T19	3		T92	38
valid_sources[0x20]	1638365	1			T1	2		T13	1		T19	1
valid_sources[0x21]	1634690	1			T13	5		T92	39		T2	1
valid_sources[0x22]	1648835	1			T1	4		T11	1		T13	6
valid_sources[0x23]	1660920	1			T13	4		T92	24		T118	24
valid_sources[0x24]	1694560	1			T1	10		T13	10		T92	17
valid_sources[0x25]	1646115	1			T1	2		T92	25		T3	2
valid_sources[0x26]	1679505	1			T1	9		T13	4		T92	16
valid_sources[0x27]	1603975	1			T13	3		T92	28		T118	28
valid_sources[0x28]	1592050	1			T1	5		T92	39		T2	7
valid_sources[0x29]	1668050	1			T1	10		T13	2		T92	52
valid_sources[0x2a]	1667195	1			T11	3		T13	1		T14	3
valid_sources[0x2b]	1604945	1			T11	1		T13	16		T14	1
valid_sources[0x2c]	1702840	1			T1	5		T13	2		T16	2
valid_sources[0x2d]	1620620	1			T1	31		T92	33		T2	2
valid_sources[0x2e]	1677735	1			T1	5		T19	3		T92	21
valid_sources[0x2f]	1641925	1			T1	6		T13	1		T92	14
valid_sources[0x30]	1605060	1			T13	3		T92	28		T118	28
valid_sources[0x31]	1661525	1			T92	24		T118	24		T100	4
valid_sources[0x32]	1630420	1			T1	5		T92	22		T2	3
valid_sources[0x33]	1693710	1			T1	1		T19	2		T92	31
valid_sources[0x34]	1620065	1			T1	8		T92	28		T2	6
valid_sources[0x35]	1631480	1			T1	1		T13	3		T16	7
valid_sources[0x36]	1645445	1			T1	2		T92	5		T2	2
valid_sources[0x37]	1633150	1			T1	19		T12	2		T13	10
valid_sources[0x38]	1608390	1			T1	4		T92	26		T2	2
valid_sources[0x39]	1620430	1			T1	4		T92	22		T3	4
valid_sources[0x3a]	1656100	1			T13	10		T19	7		T92	12
valid_sources[0x3b]	1697655	1			T1	7		T11	1		T13	6
valid_sources[0x3c]	1653105	1			T1	18		T19	9		T92	39
valid_sources[0x3d]	1623495	1			T1	3		T92	37		T3	3
valid_sources[0x3e]	1578025	1			T1	10		T92	28		T3	10
valid_sources[0x3f]	1653935	1			T1	2		T13	7		T92	28
valid_sources[0x40]	1693360	1			T1	7		T11	3		T13	5
valid_sources[0x41]	1608915	1			T13	2		T92	9		T118	9
valid_sources[0x42]	1634590	1			T13	1		T92	5		T2	1
valid_sources[0x43]	1655605	1			T92	32		T2	1		T118	32
valid_sources[0x44]	1640335	1			T1	5		T11	3		T12	2
valid_sources[0x45]	1696825	1			T1	5		T92	23		T3	5
valid_sources[0x46]	1686060	1			T13	1		T92	25		T2	1
valid_sources[0x47]	1634890	1			T1	4		T92	53		T3	4
valid_sources[0x48]	1742215	1			T1	2		T92	25		T3	2
valid_sources[0x49]	1667755	1			T1	10		T13	1		T92	54
valid_sources[0x4a]	1657495	1			T1	7		T16	3		T92	38
valid_sources[0x4b]	1639365	1			T1	20		T92	30		T2	1
valid_sources[0x4c]	1688435	1			T1	1		T11	3		T14	3
valid_sources[0x4d]	1672745	1			T92	25		T2	3		T118	25
valid_sources[0x4e]	1648580	1			T1	1		T13	2		T92	20
valid_sources[0x4f]	1644235	1			T1	2		T13	10		T92	34
valid_sources[0x50]	1642950	1			T1	3		T19	1		T92	32
valid_sources[0x51]	1639685	1			T1	10		T13	3		T92	12
valid_sources[0x52]	1592220	1			T1	25		T92	113		T3	25
valid_sources[0x53]	1660745	1			T11	3		T13	7		T14	3
valid_sources[0x54]	1674190	1			T1	1		T92	15		T3	1
valid_sources[0x55]	1679485	1			T1	15		T92	24		T2	5
valid_sources[0x56]	1614720	1			T92	36		T2	1		T118	36
valid_sources[0x57]	1605715	1			T92	4		T118	4		T100	2
valid_sources[0x58]	1565950	1			T1	1		T19	4		T92	54
valid_sources[0x59]	1633530	1			T1	13		T11	3		T14	3
valid_sources[0x5a]	1662855	1			T1	7		T13	7		T92	41
valid_sources[0x5b]	1673930	1			T1	5		T13	2		T92	13
valid_sources[0x5c]	1644340	1			T92	28		T118	28		T113	28
valid_sources[0x5d]	1669515	1			T1	16		T92	71		T3	16
valid_sources[0x5e]	1712975	1			T1	16		T13	6		T16	1
valid_sources[0x5f]	1640965	1			T92	2		T118	2		T113	2
valid_sources[0x60]	1666830	1			T1	1		T92	40		T2	1
valid_sources[0x61]	1654800	1			T1	10		T16	1		T92	36
valid_sources[0x62]	1637320	1			T1	4		T16	1		T92	25
valid_sources[0x63]	1647320	1			T92	30		T118	30		T113	30
valid_sources[0x64]	1675920	1			T1	11		T13	7		T92	14
valid_sources[0x65]	1600685	1			T1	8		T12	2		T13	14
valid_sources[0x66]	1603280	1			T13	1		T16	1		T92	33
valid_sources[0x67]	1649845	1			T92	25		T2	2		T56	1
valid_sources[0x68]	1643265	1			T1	2		T19	3		T92	15
valid_sources[0x69]	1649865	1			T1	5		T92	21		T56	5
valid_sources[0x6a]	1621930	1			T1	5		T11	2		T14	2
valid_sources[0x6b]	1652090	1			T92	26		T118	26		T113	26
valid_sources[0x6c]	1659625	1			T1	4		T19	2		T92	28
valid_sources[0x6d]	1641340	1			T1	17		T13	6		T92	22
valid_sources[0x6e]	1618215	1			T1	1		T11	4		T13	2
valid_sources[0x6f]	1613080	1			T1	15		T92	23		T2	2
valid_sources[0x70]	1631945	1			T1	19		T13	2		T92	17
valid_sources[0x71]	1603145	1			T1	7		T92	26		T3	7
valid_sources[0x72]	1653760	1			T1	12		T13	1		T92	15
valid_sources[0x73]	1586920	1			T1	13		T13	4		T19	4
valid_sources[0x74]	1599895	1			T1	8		T92	14		T3	8
valid_sources[0x75]	1658165	1			T1	16		T13	3		T92	25
valid_sources[0x76]	1653525	1			T1	2		T92	42		T3	2
valid_sources[0x77]	1633195	1			T1	1		T92	29		T3	1
valid_sources[0x78]	1677810	1			T92	46		T118	46		T113	46
valid_sources[0x79]	1659800	1			T92	56		T2	1		T118	56
valid_sources[0x7a]	1615425	1			T1	6		T92	6		T3	6
valid_sources[0x7b]	1633775	1			T1	7		T13	1		T92	33
valid_sources[0x7c]	1691525	1			T1	2		T13	2		T92	16
valid_sources[0x7d]	1658250	1			T1	2		T13	2		T19	2
valid_sources[0x7e]	1657675	1			T1	3		T13	2		T16	1
valid_sources[0x7f]	1694955	1			T1	2		T12	4		T13	2
valid_sources[0x80]	1621300	1			T13	5		T19	2		T92	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79737185

1

T1

394

T11

34

T12

6

values[0x0]

all_enables

biggest_size

55791170

1

T1

295

T11

29

T13

125

values[0x1]

all_enables

biggest_size

47533070

1

T1

266

T11

26

T12

1