Unified Coverage Report :: Module :: prim_count

Module Definition

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Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_kmac_core.u_key_index_count	100.00			100.00
tb.dut.u_sha3.u_pad.u_sentmsg_count	100.00			100.00
tb.dut.u_sha3.u_keccak.u_round_count	100.00			100.00

Module Instance : tb.dut.u_kmac_core.u_key_index_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.46	98.55	92.86		75.00	92.00	88.89	u_kmac_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sha3.u_pad.u_sentmsg_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.16	99.38	88.37		82.35	95.70	100.00	u_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sha3.u_keccak.u_round_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.11	71.25	100.00		30.00	79.31	100.00	u_keccak

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00


Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rst_ni	Yes	Yes	T20,T23,T39	Yes	T20,T21,T22	INPUT
clr_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
cnt_next_o[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
err_o	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT

Toggle Coverage for Instance : tb.dut.u_kmac_core.u_key_index_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00


Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rst_ni	Yes	Yes	T20,T23,T39	Yes	T20,T21,T22	INPUT
clr_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
cnt_next_o[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
err_o	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT

Toggle Coverage for Instance : tb.dut.u_sha3.u_pad.u_sentmsg_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00


Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rst_ni	Yes	Yes	T20,T23,T39	Yes	T20,T21,T22	INPUT
clr_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
cnt_next_o[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
err_o	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT

Toggle Coverage for Instance : tb.dut.u_sha3.u_keccak.u_round_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	30	30	100.00
Total Bits 0->1	15	15	100.00
Total Bits 1->0	15	15	100.00


Ports	7	7	100.00
Port Bits	30	30	100.00
Port Bits 0->1	15	15	100.00
Port Bits 1->0	15	15	100.00

**Port Details**
Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rst_ni	Yes	Yes	T20,T23,T39	Yes	T20,T21,T22	INPUT
clr_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
cnt_next_o[4:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
err_o	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT

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