Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	99319240	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1240	1240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	99319240	0	0
T2	5781	292	0	0
T4	0	292	0	0
T5	0	292	0	0
T6	0	292	0	0
T7	0	292	0	0
T8	0	292	0	0
T16	1700	15	0	0
T17	1284	0	0	0
T18	1284	0	0	0
T19	1837	0	0	0
T56	2174	0	0	0
T83	1284	0	0	0
T84	947	0	0	0
T86	0	15	0	0
T90	0	15	0	0
T91	0	280	0	0
T92	52357	0	0	0
T93	1837	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240	1240	0	0
T1	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	99097615	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1240	1240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	99097615	0	0
T2	5781	284	0	0
T4	0	284	0	0
T5	0	284	0	0
T6	0	284	0	0
T7	0	284	0	0
T8	0	284	0	0
T16	1700	15	0	0
T17	1284	0	0	0
T18	1284	0	0	0
T19	1837	0	0	0
T56	2174	0	0	0
T83	1284	0	0	0
T84	947	0	0	0
T86	0	15	0	0
T90	0	15	0	0
T91	0	260	0	0
T92	52357	0	0	0
T93	1837	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240	1240	0	0
T1	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	290678945	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1240	1240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	290678945	0	0
T1	10814	1491	0	0
T11	1644	136	0	0
T12	1284	22	0	0
T13	5422	669	0	0
T14	1644	136	0	0
T15	1284	22	0	0
T16	1700	82	0	0
T17	1284	22	0	0
T18	1284	22	0	0
T19	1837	144	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240	1240	0	0
T1	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	290672825	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1240	1240	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	290672825	0	0
T1	10814	1375	0	0
T11	1644	122	0	0
T12	1284	22	0	0
T13	5422	621	0	0
T14	1644	122	0	0
T15	1284	22	0	0
T16	1700	77	0	0
T17	1284	22	0	0
T18	1284	22	0	0
T19	1837	132	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	10814	9978	0	0
T11	1644	1526	0	0
T12	1284	1222	0	0
T13	5422	5158	0	0
T14	1644	1526	0	0
T15	1284	1222	0	0
T16	1700	1632	0	0
T17	1284	1222	0	0
T18	1284	1222	0	0
T19	1837	1775	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1240	1240	0	0
T1	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0