Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
7.14						7.14

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	7.14						7.14

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
7.14						7.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
7.14						7.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.98	96.32	91.89	100.00	76.92	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	1	7.14
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	1	7.14

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2760	0	0
entropy_period_rd_A	2147483647	0	0	0
intr_enable_rd_A	2147483647	0	0	0
prefix_0_rd_A	2147483647	0	0	0
prefix_10_rd_A	2147483647	0	0	0
prefix_1_rd_A	2147483647	0	0	0
prefix_2_rd_A	2147483647	0	0	0
prefix_3_rd_A	2147483647	0	0	0
prefix_4_rd_A	2147483647	0	0	0
prefix_5_rd_A	2147483647	0	0	0
prefix_6_rd_A	2147483647	0	0	0
prefix_7_rd_A	2147483647	0	0	0
prefix_8_rd_A	2147483647	0	0	0
prefix_9_rd_A	2147483647	0	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2760	0	0
T1	10814	1	0	0
T2	0	137	0	0
T3	0	1	0	0
T4	0	137	0	0
T5	0	137	0	0
T6	0	137	0	0
T7	0	137	0	0
T8	0	137	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	1644	0	0	0
T12	1284	0	0	0
T13	5422	0	0	0
T14	1644	0	0	0
T15	1284	0	0	0
T16	1700	0	0	0
T17	1284	0	0	0
T18	1284	0	0	0
T19	1837	0	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0