KMAC/UNMASKED Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	19.540s	1.554ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.920s	29.369us	5	5	100.00
V1	csr_rw	kmac_csr_rw	0.980s	32.815us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.610s	934.951us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.570s	403.473us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.270s	30.369us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.980s	32.815us	20	20	100.00
		kmac_csr_aliasing	5.570s	403.473us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	16.922us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.220s	46.940us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	12.492m	45.518ms	50	50	100.00
V2	burst_write	kmac_burst_write	4.245m	14.813ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.231m	115.269ms	50	50	100.00
		kmac_test_vectors_sha3_256	28.306m	107.886ms	50	50	100.00
		kmac_test_vectors_sha3_384	22.064m	83.071ms	50	50	100.00
		kmac_test_vectors_sha3_512	15.617m	58.504ms	50	50	100.00
		kmac_test_vectors_shake_128	1.302h	307.767ms	50	50	100.00
		kmac_test_vectors_shake_256	1.070h	258.047ms	50	50	100.00
		kmac_test_vectors_kmac	4.750s	298.813us	50	50	100.00
		kmac_test_vectors_kmac_xof	4.360s	289.902us	50	50	100.00
V2	sideload	kmac_sideload	1.980m	7.733ms	50	50	100.00
V2	app	kmac_app	1.321m	5.660ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.401m	7.616ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.309m	6.743ms	50	50	100.00
V2	error	kmac_error	2.301m	8.615ms	50	50	100.00
V2	key_error	kmac_key_error	5.650s	1.580ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.490s	2.342ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	31.490s	2.211ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	18.840s	2.783ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.310s	58.172us	50	50	100.00
V2	stress_all	kmac_stress_all	10.611m	41.434ms	50	50	100.00
V2	intr_test	kmac_intr_test	0.800s	22.940us	50	50	100.00
V2	alert_test	kmac_alert_test	0.790s	21.119us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.020s	103.243us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.020s	103.243us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.920s	29.369us	5	5	100.00
		kmac_csr_rw	0.980s	32.815us	20	20	100.00
		kmac_csr_aliasing	5.570s	403.473us	5	5	100.00
		kmac_same_csr_outstanding	1.620s	88.047us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.920s	29.369us	5	5	100.00
		kmac_csr_rw	0.980s	32.815us	20	20	100.00
		kmac_csr_aliasing	5.570s	403.473us	5	5	100.00
		kmac_same_csr_outstanding	1.620s	88.047us	20	20	100.00
V2		TOTAL			1050	1050	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.010s	38.833us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.010s	38.833us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.010s	38.833us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.010s	38.833us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.820s	96.832us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	33.220s	4.128ms	5	5	100.00
		kmac_tl_intg_err	3.000s	193.117us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.000s	193.117us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.310s	58.172us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	19.540s	1.554ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.980m	7.733ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.010s	38.833us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	33.220s	4.128ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	33.220s	4.128ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	33.220s	4.128ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	19.540s	1.554ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.310s	58.172us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	33.220s	4.128ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.313m	5.641ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	19.540s	1.554ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.085m	7.553ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1240	1290	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	25	100.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.00	96.28	87.03	100.00	76.14	93.85	96.36	87.38

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 50 failures:
  • Test kmac_stress_all_with_rand_reset has 50 failures.

    • 0.kmac_stress_all_with_rand_reset.21849633751622338813208533244688818073661478943991388280372029955858867375333
      Line 317, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7553129778 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7553129778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.kmac_stress_all_with_rand_reset.64123861783127999189922313787517482226294336917508089442695830192983989609338
      Line 317, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7553129778 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 7553129778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 48 more failures.

Past Results

• Latest
• 2023.11.02_03.36.55
• 2023.10.30_18.18.16
• 2023.10.26_03.00.07
• 2023.10.23_18.18.11
• 2023.10.19_02.17.54
• 2023.10.16_18.17.38
• 2023.10.12_18.19.59