Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	347	1			T1	8		T8	5		T7	1
all_values[1]	347	1			T1	8		T8	5		T7	1
all_values[2]	347	1			T1	8		T8	5		T7	1

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

528

1

T1

12

T8

4

T7

3

auto[1]

513

1

T1

12

T8

11

T9

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T1

18

T8

12

T7

3

auto[1]

393

1

T1

6

T8

3

T9

21

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	100	1			T1	4		T7	1		T10	1
all_values[0]	auto[0]	auto[1]	53	1			T1	2		T9	2		T10	3
all_values[0]	auto[1]	auto[0]	116	1			T1	2		T8	4		T9	1
all_values[0]	auto[1]	auto[1]	78	1			T8	1		T9	5		T10	1
all_values[1]	auto[0]	auto[0]	115	1			T1	1		T7	1		T10	2
all_values[1]	auto[0]	auto[1]	58	1			T1	1		T9	1		T10	1
all_values[1]	auto[1]	auto[0]	101	1			T1	5		T8	4		T9	1
all_values[1]	auto[1]	auto[1]	73	1			T1	1		T8	1		T9	6
all_values[2]	auto[0]	auto[0]	129	1			T1	2		T8	3		T7	1
all_values[2]	auto[0]	auto[1]	73	1			T1	2		T8	1		T9	3
all_values[2]	auto[1]	auto[0]	87	1			T1	4		T8	1		T9	1
all_values[2]	auto[1]	auto[1]	58	1			T9	4		T10	1		T77	4