Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
49.00	49.31	65.68	16.53	0.00	49.06	100.00	62.41

Total tests in report: 215

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
43.89	43.89	48.83	48.83	58.54	58.54	15.98	15.98	0.00	0.00	47.86	47.86	91.88	91.88	44.11	44.11	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3473698848
45.58	1.69	49.25	0.41	61.20	2.66	16.46	0.48	0.00	0.00	48.54	0.68	93.98	2.09	49.65	5.53	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.4058768743
47.00	1.42	49.25	0.00	63.21	2.00	16.59	0.13	0.00	0.00	48.76	0.23	98.43	4.45	52.77	3.12	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.316085978
48.03	1.03	49.31	0.06	63.90	0.69	16.68	0.09	0.00	0.00	49.06	0.30	98.43	0.00	58.87	6.10	/workspace/coverage/cover_reg_top/29.kmac_intr_test.3942706820
48.34	0.31	49.31	0.00	64.44	0.55	17.29	0.61	0.00	0.00	49.06	0.00	98.43	0.00	59.86	0.99	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1555640202
48.57	0.22	49.31	0.00	64.44	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	1.57	59.86	0.00	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1517006304
48.69	0.12	49.31	0.00	64.44	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	60.71	0.85	/workspace/coverage/cover_reg_top/23.kmac_intr_test.4025028229
48.81	0.12	49.31	0.00	65.28	0.84	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	60.71	0.00	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.672066109
48.89	0.08	49.31	0.00	65.28	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	61.28	0.57	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.237800191
48.95	0.06	49.31	0.00	65.54	0.26	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	61.42	0.14	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.16807468
48.99	0.04	49.31	0.00	65.54	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	61.70	0.28	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1601394830
49.01	0.03	49.31	0.00	65.57	0.04	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	61.84	0.14	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3146144302
49.03	0.02	49.31	0.00	65.57	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	61.99	0.14	/workspace/coverage/cover_reg_top/0.kmac_intr_test.1020498419
49.05	0.02	49.31	0.00	65.57	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	62.13	0.14	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.312387907
49.07	0.02	49.31	0.00	65.57	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	62.27	0.14	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1703373698
49.09	0.02	49.31	0.00	65.57	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	62.41	0.14	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.26824210
49.11	0.02	49.31	0.00	65.68	0.11	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	62.41	0.00	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3053801454

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2794645703
/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2971766669
/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.698699719
/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2209716937
/workspace/coverage/cover_reg_top/0.kmac_csr_rw.63772997
/workspace/coverage/cover_reg_top/0.kmac_mem_walk.3859540957
/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1821622028
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3508616576
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3179570483
/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.267780924
/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1131896155
/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.196146253
/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2062981863
/workspace/coverage/cover_reg_top/1.kmac_intr_test.3519920404
/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3548822686
/workspace/coverage/cover_reg_top/1.kmac_mem_walk.1661934779
/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3582598540
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.753915980
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.4193597987
/workspace/coverage/cover_reg_top/1.kmac_tl_errors.3976085918
/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2941246883
/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1776723439
/workspace/coverage/cover_reg_top/10.kmac_csr_rw.2562892528
/workspace/coverage/cover_reg_top/10.kmac_intr_test.4179300714
/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1807157616
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.650697424
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1016631915
/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3749855448
/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2108645800
/workspace/coverage/cover_reg_top/11.kmac_intr_test.3268072000
/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.840681483
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.300295835
/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2615067283
/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.503371612
/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1704022576
/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2924970741
/workspace/coverage/cover_reg_top/12.kmac_intr_test.3802794011
/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3550132414
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1962378893
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2255593831
/workspace/coverage/cover_reg_top/12.kmac_tl_errors.1634786858
/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2457814408
/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3159748059
/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2824141632
/workspace/coverage/cover_reg_top/13.kmac_intr_test.91059685
/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1128243924
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1642788688
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3089379119
/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1730655309
/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1928753993
/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3688506433
/workspace/coverage/cover_reg_top/14.kmac_csr_rw.3361218067
/workspace/coverage/cover_reg_top/14.kmac_intr_test.1954137309
/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3571196805
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.491185856
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1787349919
/workspace/coverage/cover_reg_top/14.kmac_tl_errors.1336868803
/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2999547464
/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2856400780
/workspace/coverage/cover_reg_top/15.kmac_csr_rw.43855114
/workspace/coverage/cover_reg_top/15.kmac_intr_test.462475179
/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2259555106
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.692480695
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1631824989
/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2877269280
/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3823400174
/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1415608004
/workspace/coverage/cover_reg_top/16.kmac_intr_test.3789056820
/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3548912924
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1546040749
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.925445994
/workspace/coverage/cover_reg_top/16.kmac_tl_errors.2147867524
/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.699946236
/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2834845013
/workspace/coverage/cover_reg_top/17.kmac_csr_rw.626772389
/workspace/coverage/cover_reg_top/17.kmac_intr_test.1281841484
/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3449881214
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.933364193
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.4139474556
/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3893621198
/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3514972330
/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2188814973
/workspace/coverage/cover_reg_top/18.kmac_csr_rw.3253357350
/workspace/coverage/cover_reg_top/18.kmac_intr_test.4164453807
/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2465676772
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.4280633970
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3817052872
/workspace/coverage/cover_reg_top/18.kmac_tl_errors.3995887015
/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3881812746
/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2742982978
/workspace/coverage/cover_reg_top/19.kmac_csr_rw.1934388564
/workspace/coverage/cover_reg_top/19.kmac_intr_test.792291434
/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.495854609
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.689652615
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.416845053
/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.507908003
/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.829862588
/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.948224082
/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.692838790
/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.392085762
/workspace/coverage/cover_reg_top/2.kmac_csr_rw.2323155710
/workspace/coverage/cover_reg_top/2.kmac_intr_test.2049748361
/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.679143449
/workspace/coverage/cover_reg_top/2.kmac_mem_walk.1702672249
/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2521170374
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2400020600
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.453173350
/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1783738957
/workspace/coverage/cover_reg_top/20.kmac_intr_test.2223768914
/workspace/coverage/cover_reg_top/21.kmac_intr_test.1704026432
/workspace/coverage/cover_reg_top/22.kmac_intr_test.719111653
/workspace/coverage/cover_reg_top/24.kmac_intr_test.2354481954
/workspace/coverage/cover_reg_top/25.kmac_intr_test.3700582294
/workspace/coverage/cover_reg_top/26.kmac_intr_test.1252584130
/workspace/coverage/cover_reg_top/27.kmac_intr_test.3776464737
/workspace/coverage/cover_reg_top/28.kmac_intr_test.3428852473
/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1769083137
/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1623738606
/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2859288417
/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2563086004
/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1398067675
/workspace/coverage/cover_reg_top/3.kmac_intr_test.1640411968
/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.4133396551
/workspace/coverage/cover_reg_top/3.kmac_mem_walk.3365097630
/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3959557147
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4083735626
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1648073673
/workspace/coverage/cover_reg_top/3.kmac_tl_errors.3190800288
/workspace/coverage/cover_reg_top/30.kmac_intr_test.3459180051
/workspace/coverage/cover_reg_top/31.kmac_intr_test.565543047
/workspace/coverage/cover_reg_top/32.kmac_intr_test.2796369269
/workspace/coverage/cover_reg_top/33.kmac_intr_test.2783379074
/workspace/coverage/cover_reg_top/34.kmac_intr_test.3439359844
/workspace/coverage/cover_reg_top/35.kmac_intr_test.3054514177
/workspace/coverage/cover_reg_top/36.kmac_intr_test.2459421001
/workspace/coverage/cover_reg_top/37.kmac_intr_test.2834569913
/workspace/coverage/cover_reg_top/38.kmac_intr_test.3520912370
/workspace/coverage/cover_reg_top/39.kmac_intr_test.355922191
/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1357172400
/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.458373533
/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3956085689
/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1763448253
/workspace/coverage/cover_reg_top/4.kmac_csr_rw.1187783248
/workspace/coverage/cover_reg_top/4.kmac_intr_test.3673084491
/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2128658453
/workspace/coverage/cover_reg_top/4.kmac_mem_walk.3064083846
/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2494917217
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.889354734
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2733108280
/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3820524205
/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.248418060
/workspace/coverage/cover_reg_top/40.kmac_intr_test.1427281246
/workspace/coverage/cover_reg_top/41.kmac_intr_test.3534921410
/workspace/coverage/cover_reg_top/42.kmac_intr_test.626336121
/workspace/coverage/cover_reg_top/43.kmac_intr_test.2410528771
/workspace/coverage/cover_reg_top/44.kmac_intr_test.2951564529
/workspace/coverage/cover_reg_top/45.kmac_intr_test.4173067191
/workspace/coverage/cover_reg_top/46.kmac_intr_test.1895096
/workspace/coverage/cover_reg_top/47.kmac_intr_test.1793592350
/workspace/coverage/cover_reg_top/48.kmac_intr_test.2272370651
/workspace/coverage/cover_reg_top/49.kmac_intr_test.1245043562
/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.527713428
/workspace/coverage/cover_reg_top/5.kmac_csr_rw.3917241715
/workspace/coverage/cover_reg_top/5.kmac_intr_test.1448387644
/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2207722560
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1729104089
/workspace/coverage/cover_reg_top/5.kmac_tl_errors.3330461981
/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3264497616
/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.43718923
/workspace/coverage/cover_reg_top/6.kmac_csr_rw.920168156
/workspace/coverage/cover_reg_top/6.kmac_intr_test.974161220
/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4202663802
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2288738475
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3538196
/workspace/coverage/cover_reg_top/6.kmac_tl_errors.1666612318
/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3787557977
/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1388010406
/workspace/coverage/cover_reg_top/7.kmac_csr_rw.3233970818
/workspace/coverage/cover_reg_top/7.kmac_intr_test.2455448968
/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1833959966
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2140104279
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3150505381
/workspace/coverage/cover_reg_top/7.kmac_tl_errors.3838675414
/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.179000402
/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1245783504
/workspace/coverage/cover_reg_top/8.kmac_csr_rw.2599101563
/workspace/coverage/cover_reg_top/8.kmac_intr_test.3550773682
/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2692705567
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2118638169
/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3225706767
/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.305403379
/workspace/coverage/cover_reg_top/9.kmac_csr_rw.3734960721
/workspace/coverage/cover_reg_top/9.kmac_intr_test.2155151831
/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.4129025419
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2453564713
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3162928209
/workspace/coverage/cover_reg_top/9.kmac_tl_errors.3112066853
/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2313462223

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Total test records in report: 215

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tests.html | tests1.html | tests2.html | tests3.html

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/34.kmac_intr_test.3439359844			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:25 PM PST 23	30811334 ps
T2	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1776723439			Dec 20 12:37:00 PM PST 23	Dec 20 12:37:39 PM PST 23	16075387 ps
T3	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2108645800			Dec 20 12:36:56 PM PST 23	Dec 20 12:37:33 PM PST 23	27175026 ps
T4	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3179570483			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:21 PM PST 23	70168306 ps
T8	/workspace/coverage/cover_reg_top/44.kmac_intr_test.2951564529			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:01 PM PST 23	12696897 ps
T5	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3473698848			Dec 20 12:37:08 PM PST 23	Dec 20 12:37:53 PM PST 23	460266857 ps
T6	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3089379119			Dec 20 12:36:46 PM PST 23	Dec 20 12:37:16 PM PST 23	200277699 ps
T12	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3548912924			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:03 PM PST 23	411214881 ps
T7	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.4058768743			Dec 20 12:37:27 PM PST 23	Dec 20 12:38:46 PM PST 23	69267603 ps
T13	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1601394830			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:17 PM PST 23	385939207 ps
T24	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2733108280			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:21 PM PST 23	153928362 ps
T25	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1787349919			Dec 20 12:37:12 PM PST 23	Dec 20 12:38:01 PM PST 23	133049195 ps
T26	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1769083137			Dec 20 12:37:22 PM PST 23	Dec 20 12:38:35 PM PST 23	307592594 ps
T27	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.316085978			Dec 20 12:36:50 PM PST 23	Dec 20 12:37:23 PM PST 23	148497585 ps
T11	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2859288417			Dec 20 12:37:16 PM PST 23	Dec 20 12:38:10 PM PST 23	21179689 ps
T28	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1555640202			Dec 20 12:36:37 PM PST 23	Dec 20 12:36:52 PM PST 23	223329139 ps
T9	/workspace/coverage/cover_reg_top/3.kmac_intr_test.1640411968			Dec 20 12:37:17 PM PST 23	Dec 20 12:38:14 PM PST 23	48209848 ps
T14	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2209716937			Dec 20 12:36:36 PM PST 23	Dec 20 12:36:48 PM PST 23	99129753 ps
T15	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3688506433			Dec 20 12:37:34 PM PST 23	Dec 20 12:38:51 PM PST 23	21098569 ps
T31	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.179000402			Dec 20 12:37:31 PM PST 23	Dec 20 12:38:49 PM PST 23	132565676 ps
T10	/workspace/coverage/cover_reg_top/42.kmac_intr_test.626336121			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:03 PM PST 23	32088359 ps
T16	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1763448253			Dec 20 12:36:40 PM PST 23	Dec 20 12:36:57 PM PST 23	40576741 ps
T36	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.196146253			Dec 20 12:36:32 PM PST 23	Dec 20 12:36:37 PM PST 23	24508456 ps
T77	/workspace/coverage/cover_reg_top/29.kmac_intr_test.3942706820			Dec 20 12:37:11 PM PST 23	Dec 20 12:37:55 PM PST 23	45211424 ps
T60	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1016631915			Dec 20 12:36:53 PM PST 23	Dec 20 12:37:29 PM PST 23	58259908 ps
T32	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2313462223			Dec 20 12:36:44 PM PST 23	Dec 20 12:37:11 PM PST 23	57405684 ps
T82	/workspace/coverage/cover_reg_top/37.kmac_intr_test.2834569913			Dec 20 12:37:11 PM PST 23	Dec 20 12:37:56 PM PST 23	115217870 ps
T61	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1833959966			Dec 20 12:36:55 PM PST 23	Dec 20 12:37:33 PM PST 23	73566497 ps
T33	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3881812746			Dec 20 12:37:24 PM PST 23	Dec 20 12:38:36 PM PST 23	367409601 ps
T37	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1128243924			Dec 20 12:36:44 PM PST 23	Dec 20 12:37:10 PM PST 23	167208850 ps
T83	/workspace/coverage/cover_reg_top/35.kmac_intr_test.3054514177			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:55 PM PST 23	18033737 ps
T78	/workspace/coverage/cover_reg_top/9.kmac_intr_test.2155151831			Dec 20 12:36:52 PM PST 23	Dec 20 12:37:26 PM PST 23	14180087 ps
T92	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.3361218067			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:26 PM PST 23	57737740 ps
T38	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3550132414			Dec 20 12:36:58 PM PST 23	Dec 20 12:37:38 PM PST 23	115501215 ps
T81	/workspace/coverage/cover_reg_top/6.kmac_intr_test.974161220			Dec 20 12:37:17 PM PST 23	Dec 20 12:38:13 PM PST 23	38630643 ps
T17	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2856400780			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:20 PM PST 23	375059054 ps
T18	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.3112066853			Dec 20 12:36:44 PM PST 23	Dec 20 12:37:11 PM PST 23	204567950 ps
T79	/workspace/coverage/cover_reg_top/13.kmac_intr_test.91059685			Dec 20 12:37:12 PM PST 23	Dec 20 12:38:02 PM PST 23	56682627 ps
T19	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3146144302			Dec 20 12:36:36 PM PST 23	Dec 20 12:36:47 PM PST 23	76445196 ps
T39	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.650697424			Dec 20 12:36:55 PM PST 23	Dec 20 12:37:32 PM PST 23	49326066 ps
T93	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1398067675			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:05 PM PST 23	61768411 ps
T94	/workspace/coverage/cover_reg_top/23.kmac_intr_test.4025028229			Dec 20 12:37:09 PM PST 23	Dec 20 12:37:52 PM PST 23	94097704 ps
T20	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2834845013			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:02 PM PST 23	56631218 ps
T64	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.453173350			Dec 20 12:36:51 PM PST 23	Dec 20 12:37:26 PM PST 23	137803165 ps
T65	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.16807468			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:07 PM PST 23	106529918 ps
T84	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2272370651			Dec 20 12:39:02 PM PST 23	Dec 20 12:40:08 PM PST 23	43509480 ps
T21	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3159748059			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:56 PM PST 23	100642570 ps
T22	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.3976085918			Dec 20 12:36:35 PM PST 23	Dec 20 12:36:46 PM PST 23	975948738 ps
T95	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3582598540			Dec 20 12:36:36 PM PST 23	Dec 20 12:36:48 PM PST 23	55036125 ps
T23	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.1666612318			Dec 20 12:36:43 PM PST 23	Dec 20 12:37:09 PM PST 23	105645678 ps
T96	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1821622028			Dec 20 12:36:55 PM PST 23	Dec 20 12:37:32 PM PST 23	25001892 ps
T97	/workspace/coverage/cover_reg_top/14.kmac_intr_test.1954137309			Dec 20 12:37:07 PM PST 23	Dec 20 12:37:49 PM PST 23	27100483 ps
T98	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2118638169			Dec 20 12:36:45 PM PST 23	Dec 20 12:37:13 PM PST 23	494463531 ps
T85	/workspace/coverage/cover_reg_top/16.kmac_intr_test.3789056820			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:18 PM PST 23	21248014 ps
T40	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.1934388564			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:18 PM PST 23	121329830 ps
T99	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.3365097630			Dec 20 12:37:04 PM PST 23	Dec 20 12:37:45 PM PST 23	31683239 ps
T100	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.458373533			Dec 20 12:36:31 PM PST 23	Dec 20 12:36:44 PM PST 23	163032629 ps
T101	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2794645703			Dec 20 12:36:27 PM PST 23	Dec 20 12:36:34 PM PST 23	89508716 ps
T41	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3548822686			Dec 20 12:36:32 PM PST 23	Dec 20 12:36:38 PM PST 23	20638504 ps
T43	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.495854609			Dec 20 12:36:49 PM PST 23	Dec 20 12:37:23 PM PST 23	40184094 ps
T29	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1245783504			Dec 20 12:36:54 PM PST 23	Dec 20 12:37:31 PM PST 23	54213633 ps
T102	/workspace/coverage/cover_reg_top/33.kmac_intr_test.2783379074			Dec 20 12:37:26 PM PST 23	Dec 20 12:38:39 PM PST 23	15488167 ps
T42	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2692705567			Dec 20 12:37:26 PM PST 23	Dec 20 12:38:40 PM PST 23	205494572 ps
T103	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2796369269			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:33 PM PST 23	15460955 ps
T104	/workspace/coverage/cover_reg_top/40.kmac_intr_test.1427281246			Dec 20 12:37:25 PM PST 23	Dec 20 12:38:37 PM PST 23	21593419 ps
T30	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2457814408			Dec 20 12:37:07 PM PST 23	Dec 20 12:37:53 PM PST 23	337485345 ps
T68	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2288738475			Dec 20 12:37:02 PM PST 23	Dec 20 12:37:42 PM PST 23	34157023 ps
T105	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.2323155710			Dec 20 12:36:50 PM PST 23	Dec 20 12:37:23 PM PST 23	20465354 ps
T106	/workspace/coverage/cover_reg_top/5.kmac_intr_test.1448387644			Dec 20 12:36:33 PM PST 23	Dec 20 12:36:39 PM PST 23	58260392 ps
T75	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2742982978			Dec 20 12:37:20 PM PST 23	Dec 20 12:38:24 PM PST 23	40219605 ps
T34	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3893621198			Dec 20 12:37:23 PM PST 23	Dec 20 12:38:30 PM PST 23	203119914 ps
T107	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.3233970818			Dec 20 12:37:08 PM PST 23	Dec 20 12:38:02 PM PST 23	48965399 ps
T108	/workspace/coverage/cover_reg_top/43.kmac_intr_test.2410528771			Dec 20 12:37:12 PM PST 23	Dec 20 12:37:59 PM PST 23	50076669 ps
T66	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.889354734			Dec 20 12:37:07 PM PST 23	Dec 20 12:37:50 PM PST 23	174342809 ps
T109	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.4193597987			Dec 20 12:36:38 PM PST 23	Dec 20 12:36:53 PM PST 23	42061432 ps
T110	/workspace/coverage/cover_reg_top/46.kmac_intr_test.1895096			Dec 20 12:39:00 PM PST 23	Dec 20 12:40:14 PM PST 23	30550847 ps
T111	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.4139474556			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:56 PM PST 23	65859491 ps
T69	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2453564713			Dec 20 12:36:42 PM PST 23	Dec 20 12:37:04 PM PST 23	36408840 ps
T35	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.1336868803			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:20 PM PST 23	38391654 ps
T76	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3749855448			Dec 20 12:37:29 PM PST 23	Dec 20 12:38:44 PM PST 23	21969496 ps
T112	/workspace/coverage/cover_reg_top/38.kmac_intr_test.3520912370			Dec 20 12:37:22 PM PST 23	Dec 20 12:38:29 PM PST 23	33259350 ps
T113	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.3734960721			Dec 20 12:37:15 PM PST 23	Dec 20 12:38:09 PM PST 23	21704780 ps
T114	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.267780924			Dec 20 12:36:47 PM PST 23	Dec 20 12:37:23 PM PST 23	2512910222 ps
T70	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.672066109			Dec 20 12:37:27 PM PST 23	Dec 20 12:38:39 PM PST 23	80911481 ps
T115	/workspace/coverage/cover_reg_top/17.kmac_intr_test.1281841484			Dec 20 12:36:47 PM PST 23	Dec 20 12:37:17 PM PST 23	11904323 ps
T116	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.416845053			Dec 20 12:36:58 PM PST 23	Dec 20 12:37:39 PM PST 23	137268244 ps
T67	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.491185856			Dec 20 12:37:08 PM PST 23	Dec 20 12:37:51 PM PST 23	85092614 ps
T117	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.933364193			Dec 20 12:37:27 PM PST 23	Dec 20 12:38:45 PM PST 23	23979334 ps
T118	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2999547464			Dec 20 12:36:56 PM PST 23	Dec 20 12:37:35 PM PST 23	109231516 ps
T88	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3264497616			Dec 20 12:36:31 PM PST 23	Dec 20 12:36:39 PM PST 23	635235698 ps
T119	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1648073673			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:02 PM PST 23	40659124 ps
T73	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.3838675414			Dec 20 12:37:15 PM PST 23	Dec 20 12:38:07 PM PST 23	35634919 ps
T120	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.2599101563			Dec 20 12:36:47 PM PST 23	Dec 20 12:37:19 PM PST 23	120548414 ps
T90	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1928753993			Dec 20 12:36:41 PM PST 23	Dec 20 12:37:03 PM PST 23	379329829 ps
T121	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2971766669			Dec 20 12:36:28 PM PST 23	Dec 20 12:36:41 PM PST 23	547743734 ps
T86	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.237800191			Dec 20 12:37:18 PM PST 23	Dec 20 12:38:20 PM PST 23	182175934 ps
T71	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3053801454			Dec 20 12:37:16 PM PST 23	Dec 20 12:38:12 PM PST 23	138313660 ps
T122	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.692480695			Dec 20 12:37:05 PM PST 23	Dec 20 12:37:45 PM PST 23	80497171 ps
T72	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1783738957			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:37 PM PST 23	407385981 ps
T91	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3787557977			Dec 20 12:36:50 PM PST 23	Dec 20 12:37:26 PM PST 23	235629794 ps
T123	/workspace/coverage/cover_reg_top/0.kmac_intr_test.1020498419			Dec 20 12:37:27 PM PST 23	Dec 20 12:38:40 PM PST 23	16840567 ps
T124	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.3859540957			Dec 20 12:37:25 PM PST 23	Dec 20 12:38:35 PM PST 23	49155875 ps
T125	/workspace/coverage/cover_reg_top/45.kmac_intr_test.4173067191			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:55 PM PST 23	38169489 ps
T126	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.1661934779			Dec 20 12:36:28 PM PST 23	Dec 20 12:36:32 PM PST 23	10330795 ps
T127	/workspace/coverage/cover_reg_top/27.kmac_intr_test.3776464737			Dec 20 12:37:20 PM PST 23	Dec 20 12:38:20 PM PST 23	53935881 ps
T128	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.4129025419			Dec 20 12:37:24 PM PST 23	Dec 20 12:38:38 PM PST 23	239085006 ps
T129	/workspace/coverage/cover_reg_top/11.kmac_intr_test.3268072000			Dec 20 12:36:47 PM PST 23	Dec 20 12:37:18 PM PST 23	25751394 ps
T130	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2521170374			Dec 20 12:36:50 PM PST 23	Dec 20 12:37:23 PM PST 23	44029858 ps
T131	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4083735626			Dec 20 12:37:20 PM PST 23	Dec 20 12:38:22 PM PST 23	21498964 ps
T132	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.689652615			Dec 20 12:36:47 PM PST 23	Dec 20 12:37:27 PM PST 23	56344390 ps
T133	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1642788688			Dec 20 12:37:27 PM PST 23	Dec 20 12:38:37 PM PST 23	47686778 ps
T134	/workspace/coverage/cover_reg_top/12.kmac_intr_test.3802794011			Dec 20 12:36:50 PM PST 23	Dec 20 12:37:23 PM PST 23	31890300 ps
T135	/workspace/coverage/cover_reg_top/39.kmac_intr_test.355922191			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:01 PM PST 23	14871235 ps
T136	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.698699719			Dec 20 12:36:38 PM PST 23	Dec 20 12:36:52 PM PST 23	63426139 ps
T44	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.679143449			Dec 20 12:37:22 PM PST 23	Dec 20 12:38:26 PM PST 23	28023160 ps
T45	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.305403379			Dec 20 12:36:45 PM PST 23	Dec 20 12:37:12 PM PST 23	56927660 ps
T46	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2941246883			Dec 20 12:36:58 PM PST 23	Dec 20 12:37:39 PM PST 23	277658398 ps
T47	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3508616576			Dec 20 12:36:50 PM PST 23	Dec 20 12:37:23 PM PST 23	140347492 ps
T48	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2400020600			Dec 20 12:36:39 PM PST 23	Dec 20 12:36:54 PM PST 23	29236581 ps
T49	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2259555106			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:28 PM PST 23	121796700 ps
T137	/workspace/coverage/cover_reg_top/31.kmac_intr_test.565543047			Dec 20 12:37:05 PM PST 23	Dec 20 12:37:46 PM PST 23	17624587 ps
T138	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1131896155			Dec 20 12:36:36 PM PST 23	Dec 20 12:36:59 PM PST 23	3110697144 ps
T139	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2563086004			Dec 20 12:36:40 PM PST 23	Dec 20 12:36:56 PM PST 23	61184423 ps
T140	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.692838790			Dec 20 12:36:49 PM PST 23	Dec 20 12:37:21 PM PST 23	39065911 ps
T141	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.3064083846			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:26 PM PST 23	11664041 ps
T142	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1546040749			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:35 PM PST 23	56214236 ps
T143	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.503371612			Dec 20 12:37:23 PM PST 23	Dec 20 12:38:33 PM PST 23	202327841 ps
T144	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1962378893			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:26 PM PST 23	50156142 ps
T145	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3571196805			Dec 20 12:37:02 PM PST 23	Dec 20 12:37:43 PM PST 23	124796493 ps
T146	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2824141632			Dec 20 12:36:47 PM PST 23	Dec 20 12:37:18 PM PST 23	47021109 ps
T147	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.507908003			Dec 20 12:36:55 PM PST 23	Dec 20 12:37:35 PM PST 23	396738145 ps
T148	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.1634786858			Dec 20 12:36:44 PM PST 23	Dec 20 12:37:11 PM PST 23	73195678 ps
T149	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.3917241715			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:35 PM PST 23	20522354 ps
T150	/workspace/coverage/cover_reg_top/15.kmac_intr_test.462475179			Dec 20 12:37:17 PM PST 23	Dec 20 12:38:14 PM PST 23	29010605 ps
T151	/workspace/coverage/cover_reg_top/8.kmac_intr_test.3550773682			Dec 20 12:36:55 PM PST 23	Dec 20 12:37:31 PM PST 23	16426865 ps
T89	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.26824210			Dec 20 12:37:03 PM PST 23	Dec 20 12:37:48 PM PST 23	210810007 ps
T152	/workspace/coverage/cover_reg_top/25.kmac_intr_test.3700582294			Dec 20 12:37:38 PM PST 23	Dec 20 12:38:54 PM PST 23	54814834 ps
T153	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.3995887015			Dec 20 12:36:51 PM PST 23	Dec 20 12:37:33 PM PST 23	93792062 ps
T80	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.312387907			Dec 20 12:37:33 PM PST 23	Dec 20 12:39:04 PM PST 23	101684646 ps
T154	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1357172400			Dec 20 12:36:32 PM PST 23	Dec 20 12:36:42 PM PST 23	310661601 ps
T155	/workspace/coverage/cover_reg_top/36.kmac_intr_test.2459421001			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:03 PM PST 23	56731229 ps
T156	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3959557147			Dec 20 12:37:25 PM PST 23	Dec 20 12:38:38 PM PST 23	70255989 ps
T157	/workspace/coverage/cover_reg_top/1.kmac_intr_test.3519920404			Dec 20 12:36:26 PM PST 23	Dec 20 12:36:27 PM PST 23	22825950 ps
T158	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2924970741			Dec 20 12:36:48 PM PST 23	Dec 20 12:37:20 PM PST 23	44639663 ps
T159	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.753915980			Dec 20 12:36:36 PM PST 23	Dec 20 12:36:47 PM PST 23	430132885 ps
T160	/workspace/coverage/cover_reg_top/7.kmac_intr_test.2455448968			Dec 20 12:37:23 PM PST 23	Dec 20 12:38:32 PM PST 23	16475742 ps
T161	/workspace/coverage/cover_reg_top/47.kmac_intr_test.1793592350			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:20 PM PST 23	31952485 ps
T162	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2062981863			Dec 20 12:36:34 PM PST 23	Dec 20 12:36:42 PM PST 23	57470527 ps
T163	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2465676772			Dec 20 12:36:58 PM PST 23	Dec 20 12:37:38 PM PST 23	189756626 ps
T164	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2255593831			Dec 20 12:37:28 PM PST 23	Dec 20 12:38:44 PM PST 23	51143084 ps
T165	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.2562892528			Dec 20 12:36:53 PM PST 23	Dec 20 12:37:29 PM PST 23	19037184 ps
T166	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.925445994			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:24 PM PST 23	42023726 ps
T50	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.4133396551			Dec 20 12:36:54 PM PST 23	Dec 20 12:37:30 PM PST 23	24443273 ps
T51	/workspace/coverage/cover_reg_top/18.kmac_intr_test.4164453807			Dec 20 12:36:58 PM PST 23	Dec 20 12:37:37 PM PST 23	20169273 ps
T54	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.43718923			Dec 20 12:37:03 PM PST 23	Dec 20 12:37:44 PM PST 23	77989085 ps
T55	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1703373698			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:28 PM PST 23	1427943701 ps
T56	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.248418060			Dec 20 12:37:05 PM PST 23	Dec 20 12:37:47 PM PST 23	764557115 ps
T57	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2188814973			Dec 20 12:36:59 PM PST 23	Dec 20 12:37:37 PM PST 23	183487381 ps
T58	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4202663802			Dec 20 12:37:26 PM PST 23	Dec 20 12:38:41 PM PST 23	85482551 ps
T59	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1704022576			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:36 PM PST 23	86823824 ps
T167	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.1702672249			Dec 20 12:36:48 PM PST 23	Dec 20 12:37:20 PM PST 23	20644339 ps
T52	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1517006304			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:02 PM PST 23	47786994 ps
T168	/workspace/coverage/cover_reg_top/22.kmac_intr_test.719111653			Dec 20 12:37:12 PM PST 23	Dec 20 12:38:02 PM PST 23	23283708 ps
T169	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2615067283			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:35 PM PST 23	154821707 ps
T74	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2877269280			Dec 20 12:37:16 PM PST 23	Dec 20 12:38:12 PM PST 23	42772737 ps
T170	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1415608004			Dec 20 12:37:22 PM PST 23	Dec 20 12:38:28 PM PST 23	63534879 ps
T171	/workspace/coverage/cover_reg_top/30.kmac_intr_test.3459180051			Dec 20 12:37:25 PM PST 23	Dec 20 12:38:37 PM PST 23	44314816 ps
T53	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2128658453			Dec 20 12:36:31 PM PST 23	Dec 20 12:36:37 PM PST 23	138707149 ps
T87	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.699946236			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:21 PM PST 23	283681697 ps
T172	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3514972330			Dec 20 12:37:27 PM PST 23	Dec 20 12:38:43 PM PST 23	193334314 ps
T62	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.4280633970			Dec 20 12:37:16 PM PST 23	Dec 20 12:38:11 PM PST 23	39622352 ps
T173	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.300295835			Dec 20 12:36:45 PM PST 23	Dec 20 12:37:11 PM PST 23	55294300 ps
T174	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.392085762			Dec 20 12:37:31 PM PST 23	Dec 20 12:38:46 PM PST 23	45768364 ps
T175	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.1187783248			Dec 20 12:37:34 PM PST 23	Dec 20 12:38:50 PM PST 23	21306387 ps
T176	/workspace/coverage/cover_reg_top/24.kmac_intr_test.2354481954			Dec 20 12:37:23 PM PST 23	Dec 20 12:38:34 PM PST 23	55507717 ps
T63	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1631824989			Dec 20 12:37:12 PM PST 23	Dec 20 12:38:04 PM PST 23	143201872 ps
T177	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.829862588			Dec 20 12:36:56 PM PST 23	Dec 20 12:37:38 PM PST 23	281947614 ps
T178	/workspace/coverage/cover_reg_top/2.kmac_intr_test.2049748361			Dec 20 12:36:47 PM PST 23	Dec 20 12:37:17 PM PST 23	19184310 ps
T179	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2140104279			Dec 20 12:37:03 PM PST 23	Dec 20 12:37:43 PM PST 23	189409573 ps
T180	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.527713428			Dec 20 12:36:58 PM PST 23	Dec 20 12:37:38 PM PST 23	36054009 ps
T181	/workspace/coverage/cover_reg_top/20.kmac_intr_test.2223768914			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:34 PM PST 23	50911570 ps
T182	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3162928209			Dec 20 12:37:18 PM PST 23	Dec 20 12:38:18 PM PST 23	221561417 ps
T183	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.63772997			Dec 20 12:36:51 PM PST 23	Dec 20 12:37:24 PM PST 23	18893182 ps
T184	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.920168156			Dec 20 12:37:26 PM PST 23	Dec 20 12:38:45 PM PST 23	32498773 ps
T185	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1623738606			Dec 20 12:37:15 PM PST 23	Dec 20 12:38:24 PM PST 23	2167229903 ps
T186	/workspace/coverage/cover_reg_top/28.kmac_intr_test.3428852473			Dec 20 12:37:31 PM PST 23	Dec 20 12:38:46 PM PST 23	15383507 ps
T187	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3820524205			Dec 20 12:37:17 PM PST 23	Dec 20 12:38:16 PM PST 23	704992551 ps
T188	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.626772389			Dec 20 12:36:43 PM PST 23	Dec 20 12:37:08 PM PST 23	20998134 ps
T189	/workspace/coverage/cover_reg_top/21.kmac_intr_test.1704026432			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:55 PM PST 23	47192628 ps
T190	/workspace/coverage/cover_reg_top/49.kmac_intr_test.1245043562			Dec 20 12:39:14 PM PST 23	Dec 20 12:40:23 PM PST 23	16912612 ps
T191	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.3330461981			Dec 20 12:37:06 PM PST 23	Dec 20 12:37:50 PM PST 23	55630850 ps
T192	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3817052872			Dec 20 12:36:41 PM PST 23	Dec 20 12:36:58 PM PST 23	180826574 ps
T193	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3956085689			Dec 20 12:36:28 PM PST 23	Dec 20 12:36:33 PM PST 23	66413979 ps
T194	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2207722560			Dec 20 12:36:39 PM PST 23	Dec 20 12:36:54 PM PST 23	79563437 ps
T195	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.948224082			Dec 20 12:37:46 PM PST 23	Dec 20 12:39:14 PM PST 23	651932090 ps
T196	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.3253357350			Dec 20 12:36:40 PM PST 23	Dec 20 12:36:55 PM PST 23	30525439 ps
T197	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.43855114			Dec 20 12:37:16 PM PST 23	Dec 20 12:38:10 PM PST 23	21832520 ps
T198	/workspace/coverage/cover_reg_top/19.kmac_intr_test.792291434			Dec 20 12:36:52 PM PST 23	Dec 20 12:37:26 PM PST 23	18479128 ps
T199	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3225706767			Dec 20 12:37:08 PM PST 23	Dec 20 12:37:55 PM PST 23	201263589 ps
T200	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1729104089			Dec 20 12:36:51 PM PST 23	Dec 20 12:37:26 PM PST 23	121334018 ps
T201	/workspace/coverage/cover_reg_top/10.kmac_intr_test.4179300714			Dec 20 12:37:12 PM PST 23	Dec 20 12:38:07 PM PST 23	23344932 ps
T202	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1807157616			Dec 20 12:36:48 PM PST 23	Dec 20 12:37:20 PM PST 23	84858242 ps
T203	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2494917217			Dec 20 12:36:27 PM PST 23	Dec 20 12:36:32 PM PST 23	593181296 ps
T204	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3823400174			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:06 PM PST 23	75562610 ps
T205	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3150505381			Dec 20 12:37:31 PM PST 23	Dec 20 12:38:47 PM PST 23	349683013 ps
T206	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3538196			Dec 20 12:37:02 PM PST 23	Dec 20 12:37:43 PM PST 23	158895097 ps
T207	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.840681483			Dec 20 12:36:44 PM PST 23	Dec 20 12:37:11 PM PST 23	662632435 ps
T208	/workspace/coverage/cover_reg_top/26.kmac_intr_test.1252584130			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:01 PM PST 23	12666927 ps
T209	/workspace/coverage/cover_reg_top/41.kmac_intr_test.3534921410			Dec 20 12:37:26 PM PST 23	Dec 20 12:38:39 PM PST 23	36524819 ps
T210	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.2147867524			Dec 20 12:37:25 PM PST 23	Dec 20 12:38:36 PM PST 23	266353152 ps
T211	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1730655309			Dec 20 12:37:36 PM PST 23	Dec 20 12:38:54 PM PST 23	218565594 ps
T212	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3449881214			Dec 20 12:37:52 PM PST 23	Dec 20 12:39:16 PM PST 23	208834835 ps
T213	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.3190800288			Dec 20 12:37:23 PM PST 23	Dec 20 12:38:36 PM PST 23	938024352 ps
T214	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3673084491			Dec 20 12:36:36 PM PST 23	Dec 20 12:36:45 PM PST 23	19220270 ps
T215	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1388010406			Dec 20 12:36:36 PM PST 23	Dec 20 12:36:49 PM PST 23	34160301 ps

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.3473698848
Short name	T5
Test name
Test status
Simulation time	460266857 ps
CPU time	2.47 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:53 PM PST 23
Peak memory	215408 kb
Host	smart-0cf84173-c69d-4d74-9ed5-b1639689e2a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473698848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.34736 98848 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.4058768743
Short name	T7
Test name
Test status
Simulation time	69267603 ps
CPU time	2.23 seconds
Started	Dec 20 12:37:27 PM PST 23
Finished	Dec 20 12:38:46 PM PST 23
Peak memory	215648 kb
Host	smart-ff10c923-4cd2-4fe3-94ce-e8f4ac5938fa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058768743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.4058768743 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.316085978
Short name	T27
Test name
Test status
Simulation time	148497585 ps
CPU time	2.09 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:23 PM PST 23
Peak memory	215908 kb
Host	smart-fb769fe8-ae08-49be-a3ae-dd714c97bd64
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316085978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac _shadow_reg_errors_with_csr_rw.316085978 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.3942706820
Short name	T77
Test name
Test status
Simulation time	45211424 ps
CPU time	0.73 seconds
Started	Dec 20 12:37:11 PM PST 23
Finished	Dec 20 12:37:55 PM PST 23
Peak memory	207156 kb
Host	smart-36b7860c-7521-4ad3-b9fc-1df07856cfb8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942706820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3942706820 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1555640202
Short name	T28
Test name
Test status
Simulation time	223329139 ps
CPU time	2.68 seconds
Started	Dec 20 12:36:37 PM PST 23
Finished	Dec 20 12:36:52 PM PST 23
Peak memory	223996 kb
Host	smart-3d26e6d7-3876-474b-a810-fdecc651b33e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555640202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.1555640202 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1517006304
Short name	T52
Test name
Test status
Simulation time	47786994 ps
CPU time	1.09 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:02 PM PST 23
Peak memory	215568 kb
Host	smart-7df23c5b-45ee-490b-98dd-769bb27782c1
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517006304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.1517006304 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.4025028229
Short name	T94
Test name
Test status
Simulation time	94097704 ps
CPU time	0.72 seconds
Started	Dec 20 12:37:09 PM PST 23
Finished	Dec 20 12:37:52 PM PST 23
Peak memory	207136 kb
Host	smart-d45a74db-aab0-436e-8760-702acccf812d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025028229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.4025028229 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.672066109
Short name	T70
Test name
Test status
Simulation time	80911481 ps
CPU time	3.05 seconds
Started	Dec 20 12:37:27 PM PST 23
Finished	Dec 20 12:38:39 PM PST 23
Peak memory	215624 kb
Host	smart-07d5c8d0-67e3-4727-9350-f8fa3970e1d7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672066109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.672066109 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.237800191
Short name	T86
Test name
Test status
Simulation time	182175934 ps
CPU time	4 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:20 PM PST 23
Peak memory	223644 kb
Host	smart-bcc51520-7b0e-4423-bc5f-00125ed059c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237800191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.237800 191 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.16807468
Short name	T65
Test name
Test status
Simulation time	106529918 ps
CPU time	1.34 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:07 PM PST 23
Peak memory	215880 kb
Host	smart-cff8faae-f051-4523-931a-309389afb34e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16807468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_er rors.16807468 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1601394830
Short name	T13
Test name
Test status
Simulation time	385939207 ps
CPU time	3.97 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:17 PM PST 23
Peak memory	215640 kb
Host	smart-58d86ddf-bf78-4753-97fa-f8219eaaa324
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601394830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1601 394830 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.3146144302
Short name	T19
Test name
Test status
Simulation time	76445196 ps
CPU time	1.41 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:47 PM PST 23
Peak memory	215520 kb
Host	smart-34b1032d-2503-466b-a957-5c5e3d73e693
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146144302 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.3146144302 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.1020498419
Short name	T123
Test name
Test status
Simulation time	16840567 ps
CPU time	0.79 seconds
Started	Dec 20 12:37:27 PM PST 23
Finished	Dec 20 12:38:40 PM PST 23
Peak memory	207148 kb
Host	smart-9a122f3e-213e-4c95-b6c6-4107ddf0d14b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020498419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1020498419 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.312387907
Short name	T80
Test name
Test status
Simulation time	101684646 ps
CPU time	1.72 seconds
Started	Dec 20 12:37:33 PM PST 23
Finished	Dec 20 12:39:04 PM PST 23
Peak memory	215464 kb
Host	smart-69b482cf-8755-4fe6-b2e5-9f697df60fa6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312387907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.312387907 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1703373698
Short name	T55
Test name
Test status
Simulation time	1427943701 ps
CPU time	3.05 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:28 PM PST 23
Peak memory	207412 kb
Host	smart-637ce434-9f9d-4f08-b0a5-af7127ecff08
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703373698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1703 373698 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.26824210
Short name	T89
Test name
Test status
Simulation time	210810007 ps
CPU time	4.98 seconds
Started	Dec 20 12:37:03 PM PST 23
Finished	Dec 20 12:37:48 PM PST 23
Peak memory	215612 kb
Host	smart-1cb02d11-2f7c-4d49-b5f4-bf543bb1996c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26824210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.2682421 0 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3053801454
Short name	T71
Test name
Test status
Simulation time	138313660 ps
CPU time	3.23 seconds
Started	Dec 20 12:37:16 PM PST 23
Finished	Dec 20 12:38:12 PM PST 23
Peak memory	215788 kb
Host	smart-26324aba-9646-4607-80d7-343ebd90c19d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053801454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3053801454 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2794645703
Short name	T101
Test name
Test status
Simulation time	89508716 ps
CPU time	4.51 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:34 PM PST 23
Peak memory	207360 kb
Host	smart-d921110d-4062-4333-a405-50e5a605849e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794645703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2794645 703 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2971766669
Short name	T121
Test name
Test status
Simulation time	547743734 ps
CPU time	10.36 seconds
Started	Dec 20 12:36:28 PM PST 23
Finished	Dec 20 12:36:41 PM PST 23
Peak memory	207320 kb
Host	smart-756b1f6a-6f4b-4442-86ed-a305a8da0844
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971766669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2971766 669 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.698699719
Short name	T136
Test name
Test status
Simulation time	63426139 ps
CPU time	1.09 seconds
Started	Dec 20 12:36:38 PM PST 23
Finished	Dec 20 12:36:52 PM PST 23
Peak memory	207368 kb
Host	smart-20996521-9000-4c78-8ec1-9680a04ea6e1
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698699719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.69869971 9 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2209716937
Short name	T14
Test name
Test status
Simulation time	99129753 ps
CPU time	2.23 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:48 PM PST 23
Peak memory	223784 kb
Host	smart-e0a7af0f-eb68-4258-b768-e7f7c51aaa45
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209716937 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2209716937 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.63772997
Short name	T183
Test name
Test status
Simulation time	18893182 ps
CPU time	1.05 seconds
Started	Dec 20 12:36:51 PM PST 23
Finished	Dec 20 12:37:24 PM PST 23
Peak memory	207256 kb
Host	smart-cee233b1-edaf-4bfc-9fe2-870fda93f642
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63772997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.63772997 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.3859540957
Short name	T124
Test name
Test status
Simulation time	49155875 ps
CPU time	0.68 seconds
Started	Dec 20 12:37:25 PM PST 23
Finished	Dec 20 12:38:35 PM PST 23
Peak memory	207148 kb
Host	smart-85017008-3ce0-43de-a2b8-fb7f125cab27
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859540957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3859540957 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.1821622028
Short name	T96
Test name
Test status
Simulation time	25001892 ps
CPU time	1.47 seconds
Started	Dec 20 12:36:55 PM PST 23
Finished	Dec 20 12:37:32 PM PST 23
Peak memory	215660 kb
Host	smart-5ab5dc4b-e82f-401d-871e-294188b6f34a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821622028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.1821622028 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3508616576
Short name	T47
Test name
Test status
Simulation time	140347492 ps
CPU time	1.04 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:23 PM PST 23
Peak memory	215760 kb
Host	smart-ab4f04df-a9cb-4d74-8c41-daafb07936ec
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508616576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.3508616576 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.3179570483
Short name	T4
Test name
Test status
Simulation time	70168306 ps
CPU time	2.61 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:21 PM PST 23
Peak memory	216100 kb
Host	smart-d9830af9-b5c3-4bf6-904b-5cd671a86b51
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179570483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac _shadow_reg_errors_with_csr_rw.3179570483 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.267780924
Short name	T114
Test name
Test status
Simulation time	2512910222 ps
CPU time	6.31 seconds
Started	Dec 20 12:36:47 PM PST 23
Finished	Dec 20 12:37:23 PM PST 23
Peak memory	215692 kb
Host	smart-997878c2-43e2-408a-909c-37420955ec46
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267780924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.26778092 4 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.1131896155
Short name	T138
Test name
Test status
Simulation time	3110697144 ps
CPU time	11.11 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:59 PM PST 23
Peak memory	207464 kb
Host	smart-d6d4de86-3bf9-40c5-8edf-a9337055dfe9
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131896155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.1131896 155 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.196146253
Short name	T36
Test name
Test status
Simulation time	24508456 ps
CPU time	0.96 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:37 PM PST 23
Peak memory	207204 kb
Host	smart-70d009bb-10d2-45ed-b662-4e98a0f33650
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196146253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.19614625 3 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.2062981863
Short name	T162
Test name
Test status
Simulation time	57470527 ps
CPU time	1.18 seconds
Started	Dec 20 12:36:34 PM PST 23
Finished	Dec 20 12:36:42 PM PST 23
Peak memory	215512 kb
Host	smart-4aecb3ab-0d90-4815-9d87-929810717f79
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062981863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2062981863 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.3519920404
Short name	T157
Test name
Test status
Simulation time	22825950 ps
CPU time	0.76 seconds
Started	Dec 20 12:36:26 PM PST 23
Finished	Dec 20 12:36:27 PM PST 23
Peak memory	207052 kb
Host	smart-bb45e335-d7f2-44fd-a3a8-e82c740624a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519920404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3519920404 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3548822686
Short name	T41
Test name
Test status
Simulation time	20638504 ps
CPU time	1.28 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:38 PM PST 23
Peak memory	215396 kb
Host	smart-ace06330-3912-4a25-861c-e0a3dadf04fa
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548822686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.3548822686 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.1661934779
Short name	T126
Test name
Test status
Simulation time	10330795 ps
CPU time	0.71 seconds
Started	Dec 20 12:36:28 PM PST 23
Finished	Dec 20 12:36:32 PM PST 23
Peak memory	207116 kb
Host	smart-8c8f5151-6e05-4de5-a4b6-3365f02baa62
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661934779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.1661934779 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.3582598540
Short name	T95
Test name
Test status
Simulation time	55036125 ps
CPU time	1.56 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:48 PM PST 23
Peak memory	215492 kb
Host	smart-f022ceea-71e0-436b-9eeb-73ce5060163f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582598540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr _outstanding.3582598540 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.753915980
Short name	T159
Test name
Test status
Simulation time	430132885 ps
CPU time	1.41 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:47 PM PST 23
Peak memory	215892 kb
Host	smart-5ffe85fd-bf00-4c9b-ba7c-6fe4043d40c0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753915980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_e rrors.753915980 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.4193597987
Short name	T109
Test name
Test status
Simulation time	42061432 ps
CPU time	1.67 seconds
Started	Dec 20 12:36:38 PM PST 23
Finished	Dec 20 12:36:53 PM PST 23
Peak memory	215956 kb
Host	smart-e2c4b74f-408f-4b52-bcdd-1a956cd09dfe
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193597987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac _shadow_reg_errors_with_csr_rw.4193597987 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.3976085918
Short name	T22
Test name
Test status
Simulation time	975948738 ps
CPU time	2.13 seconds
Started	Dec 20 12:36:35 PM PST 23
Finished	Dec 20 12:36:46 PM PST 23
Peak memory	215712 kb
Host	smart-4e676dac-0781-4578-bddc-048e28b3839e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976085918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3976085918 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.2941246883
Short name	T46
Test name
Test status
Simulation time	277658398 ps
CPU time	3.08 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	215652 kb
Host	smart-d189f1d4-4fcf-4864-905c-8782b5941430
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941246883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.29412 46883 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1776723439
Short name	T2
Test name
Test status
Simulation time	16075387 ps
CPU time	1.33 seconds
Started	Dec 20 12:37:00 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	215580 kb
Host	smart-4a574fec-e4bc-47c8-b7a5-77ebd1455670
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776723439 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1776723439 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.2562892528
Short name	T165
Test name
Test status
Simulation time	19037184 ps
CPU time	0.93 seconds
Started	Dec 20 12:36:53 PM PST 23
Finished	Dec 20 12:37:29 PM PST 23
Peak memory	207180 kb
Host	smart-f9e575ef-c5fd-4aa6-9277-ac2ecb79e383
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562892528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2562892528 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.4179300714
Short name	T201
Test name
Test status
Simulation time	23344932 ps
CPU time	0.79 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:38:07 PM PST 23
Peak memory	207140 kb
Host	smart-af375e5e-abc7-419f-84f6-b060807722bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179300714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.4179300714 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.1807157616
Short name	T202
Test name
Test status
Simulation time	84858242 ps
CPU time	1.45 seconds
Started	Dec 20 12:36:48 PM PST 23
Finished	Dec 20 12:37:20 PM PST 23
Peak memory	215620 kb
Host	smart-5b3db6c6-302c-4253-9074-13a513859092
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807157616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.1807157616 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.650697424
Short name	T39
Test name
Test status
Simulation time	49326066 ps
CPU time	1.11 seconds
Started	Dec 20 12:36:55 PM PST 23
Finished	Dec 20 12:37:32 PM PST 23
Peak memory	215660 kb
Host	smart-e4a71cc5-9e6c-4f0f-bcca-6174718a89e8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650697424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_ errors.650697424 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.1016631915
Short name	T60
Test name
Test status
Simulation time	58259908 ps
CPU time	2.55 seconds
Started	Dec 20 12:36:53 PM PST 23
Finished	Dec 20 12:37:29 PM PST 23
Peak memory	224052 kb
Host	smart-6a400197-c9f3-4822-94ba-83dc1fd8151f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016631915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.1016631915 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3749855448
Short name	T76
Test name
Test status
Simulation time	21969496 ps
CPU time	1.17 seconds
Started	Dec 20 12:37:29 PM PST 23
Finished	Dec 20 12:38:44 PM PST 23
Peak memory	215456 kb
Host	smart-e4f0e9cf-63d5-4d95-ab88-02d81342244c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749855448 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.3749855448 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2108645800
Short name	T3
Test name
Test status
Simulation time	27175026 ps
CPU time	1.1 seconds
Started	Dec 20 12:36:56 PM PST 23
Finished	Dec 20 12:37:33 PM PST 23
Peak memory	207336 kb
Host	smart-e6015fe3-cb03-410c-a772-754eeb0daa6b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108645800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2108645800 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.3268072000
Short name	T129
Test name
Test status
Simulation time	25751394 ps
CPU time	0.71 seconds
Started	Dec 20 12:36:47 PM PST 23
Finished	Dec 20 12:37:18 PM PST 23
Peak memory	207172 kb
Host	smart-e36f2c74-7ebe-48b3-9ed5-5e1e53a93c45
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268072000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.3268072000 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.840681483
Short name	T207
Test name
Test status
Simulation time	662632435 ps
CPU time	2.82 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:11 PM PST 23
Peak memory	215528 kb
Host	smart-0d5f8e82-9e68-4cf9-96bb-77016faa15bf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840681483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr _outstanding.840681483 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.300295835
Short name	T173
Test name
Test status
Simulation time	55294300 ps
CPU time	1.31 seconds
Started	Dec 20 12:36:45 PM PST 23
Finished	Dec 20 12:37:11 PM PST 23
Peak memory	215928 kb
Host	smart-f8bb0954-bec1-4ee4-a2fe-19407f77c53e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300295835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_ errors.300295835 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2615067283
Short name	T169
Test name
Test status
Simulation time	154821707 ps
CPU time	2.65 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:35 PM PST 23
Peak memory	223756 kb
Host	smart-1044e0e9-b91a-44d4-8dff-81d9975e0297
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615067283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2615067283 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.503371612
Short name	T143
Test name
Test status
Simulation time	202327841 ps
CPU time	2.76 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:33 PM PST 23
Peak memory	218176 kb
Host	smart-1b677403-c370-4aad-b7b4-c8eafe0137d3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503371612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.50337 1612 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1704022576
Short name	T59
Test name
Test status
Simulation time	86823824 ps
CPU time	1.4 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:36 PM PST 23
Peak memory	223060 kb
Host	smart-96e1b5c2-ba42-4226-b38e-0117701fb1c6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704022576 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1704022576 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.2924970741
Short name	T158
Test name
Test status
Simulation time	44639663 ps
CPU time	0.92 seconds
Started	Dec 20 12:36:48 PM PST 23
Finished	Dec 20 12:37:20 PM PST 23
Peak memory	215380 kb
Host	smart-53d64f1f-c02a-4fe3-985f-3017fbb439b3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924970741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2924970741 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.3802794011
Short name	T134
Test name
Test status
Simulation time	31890300 ps
CPU time	0.71 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:23 PM PST 23
Peak memory	207160 kb
Host	smart-4c6dec83-9a38-4919-9238-1b0dbf2b7786
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802794011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.3802794011 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3550132414
Short name	T38
Test name
Test status
Simulation time	115501215 ps
CPU time	2.5 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:38 PM PST 23
Peak memory	215648 kb
Host	smart-b389425a-8ee8-458f-b80f-82cbec050f3a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550132414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.3550132414 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.1962378893
Short name	T144
Test name
Test status
Simulation time	50156142 ps
CPU time	0.81 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:26 PM PST 23
Peak memory	207120 kb
Host	smart-5a1e70e4-d332-4eb7-b2b7-c52b5f1086a0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962378893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.1962378893 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.2255593831
Short name	T164
Test name
Test status
Simulation time	51143084 ps
CPU time	1.61 seconds
Started	Dec 20 12:37:28 PM PST 23
Finished	Dec 20 12:38:44 PM PST 23
Peak memory	215912 kb
Host	smart-f92c3c90-d07a-4669-9c11-5a87f2e3e43a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255593831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.2255593831 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.1634786858
Short name	T148
Test name
Test status
Simulation time	73195678 ps
CPU time	2.65 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:11 PM PST 23
Peak memory	215744 kb
Host	smart-e598ebdb-132f-4d4b-9d49-23bbad9b3f71
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634786858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1634786858 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2457814408
Short name	T30
Test name
Test status
Simulation time	337485345 ps
CPU time	5.15 seconds
Started	Dec 20 12:37:07 PM PST 23
Finished	Dec 20 12:37:53 PM PST 23
Peak memory	215528 kb
Host	smart-dc90ae4c-3a64-40aa-aa3c-c3fa356f7b28
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457814408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2457 814408 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3159748059
Short name	T21
Test name
Test status
Simulation time	100642570 ps
CPU time	1.7 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:56 PM PST 23
Peak memory	223756 kb
Host	smart-7b86c037-53c8-4c6d-940d-7ec2376b72f6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159748059 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3159748059 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2824141632
Short name	T146
Test name
Test status
Simulation time	47021109 ps
CPU time	1.12 seconds
Started	Dec 20 12:36:47 PM PST 23
Finished	Dec 20 12:37:18 PM PST 23
Peak memory	207436 kb
Host	smart-f0da281a-99f2-4a30-81b1-17af8375fa0a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824141632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2824141632 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.91059685
Short name	T79
Test name
Test status
Simulation time	56682627 ps
CPU time	0.79 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:38:02 PM PST 23
Peak memory	207160 kb
Host	smart-878c38d4-d694-4a96-b9cf-5595882dd8f2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91059685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.91059685 +enable_mas king=0 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.1128243924
Short name	T37
Test name
Test status
Simulation time	167208850 ps
CPU time	2.31 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:10 PM PST 23
Peak memory	215740 kb
Host	smart-afcd2235-c9d5-4445-bf82-53b77361a4d5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128243924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.1128243924 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1642788688
Short name	T133
Test name
Test status
Simulation time	47686778 ps
CPU time	1.09 seconds
Started	Dec 20 12:37:27 PM PST 23
Finished	Dec 20 12:38:37 PM PST 23
Peak memory	215860 kb
Host	smart-b2dce1b7-24ed-479b-9239-839fee7ae02a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642788688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.1642788688 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3089379119
Short name	T6
Test name
Test status
Simulation time	200277699 ps
CPU time	1.72 seconds
Started	Dec 20 12:36:46 PM PST 23
Finished	Dec 20 12:37:16 PM PST 23
Peak memory	215964 kb
Host	smart-8ea98b6c-9b69-40ab-a069-de4d950e67c3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089379119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.3089379119 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.1730655309
Short name	T211
Test name
Test status
Simulation time	218565594 ps
CPU time	3 seconds
Started	Dec 20 12:37:36 PM PST 23
Finished	Dec 20 12:38:54 PM PST 23
Peak memory	215736 kb
Host	smart-e14039c2-9690-4014-87d5-41524889d726
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730655309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1730655309 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.1928753993
Short name	T90
Test name
Test status
Simulation time	379329829 ps
CPU time	4.73 seconds
Started	Dec 20 12:36:41 PM PST 23
Finished	Dec 20 12:37:03 PM PST 23
Peak memory	215636 kb
Host	smart-51a9ec4e-e806-4de6-bc48-bd24071e3426
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928753993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.1928 753993 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3688506433
Short name	T15
Test name
Test status
Simulation time	21098569 ps
CPU time	1.46 seconds
Started	Dec 20 12:37:34 PM PST 23
Finished	Dec 20 12:38:51 PM PST 23
Peak memory	215632 kb
Host	smart-f7924818-8f1f-4681-8f20-39341c163c33
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688506433 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.3688506433 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.3361218067
Short name	T92
Test name
Test status
Simulation time	57737740 ps
CPU time	0.99 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:26 PM PST 23
Peak memory	206948 kb
Host	smart-4173dd59-edf0-4e20-b8ef-8fd598338941
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361218067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3361218067 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.1954137309
Short name	T97
Test name
Test status
Simulation time	27100483 ps
CPU time	0.77 seconds
Started	Dec 20 12:37:07 PM PST 23
Finished	Dec 20 12:37:49 PM PST 23
Peak memory	207212 kb
Host	smart-afebe116-1557-4383-99a2-90300fb9db4b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954137309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.1954137309 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3571196805
Short name	T145
Test name
Test status
Simulation time	124796493 ps
CPU time	2.1 seconds
Started	Dec 20 12:37:02 PM PST 23
Finished	Dec 20 12:37:43 PM PST 23
Peak memory	215356 kb
Host	smart-35ace6e5-d7c3-4ef9-8d7d-ab6795e855d1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571196805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs r_outstanding.3571196805 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.491185856
Short name	T67
Test name
Test status
Simulation time	85092614 ps
CPU time	0.89 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:51 PM PST 23
Peak memory	207220 kb
Host	smart-c49e69ff-d49e-4d1f-ad99-d27d8f48267f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491185856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_ errors.491185856 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1787349919
Short name	T25
Test name
Test status
Simulation time	133049195 ps
CPU time	2.21 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:38:01 PM PST 23
Peak memory	216008 kb
Host	smart-c4dd4259-5467-4d87-95cb-283bb1fb0702
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787349919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.1787349919 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.1336868803
Short name	T35
Test name
Test status
Simulation time	38391654 ps
CPU time	1.28 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:20 PM PST 23
Peak memory	215496 kb
Host	smart-a47ac68c-f855-467e-b7f3-90990b053592
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336868803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1336868803 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.2999547464
Short name	T118
Test name
Test status
Simulation time	109231516 ps
CPU time	2.59 seconds
Started	Dec 20 12:36:56 PM PST 23
Finished	Dec 20 12:37:35 PM PST 23
Peak memory	215332 kb
Host	smart-9481dfe0-9274-43e9-8e19-5af55dc612da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999547464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2999 547464 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.2856400780
Short name	T17
Test name
Test status
Simulation time	375059054 ps
CPU time	2.16 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:20 PM PST 23
Peak memory	223776 kb
Host	smart-a71f99cf-e16f-4f49-a9ab-df413d3f439c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856400780 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.2856400780 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.43855114
Short name	T197
Test name
Test status
Simulation time	21832520 ps
CPU time	0.95 seconds
Started	Dec 20 12:37:16 PM PST 23
Finished	Dec 20 12:38:10 PM PST 23
Peak memory	207016 kb
Host	smart-47535ffc-d6e0-4f69-8713-9a77b9cda5df
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43855114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.43855114 +enable_mas king=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.462475179
Short name	T150
Test name
Test status
Simulation time	29010605 ps
CPU time	0.72 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:14 PM PST 23
Peak memory	207044 kb
Host	smart-3282bbae-7eae-4b7f-a146-f6a370b345af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462475179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.462475179 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2259555106
Short name	T49
Test name
Test status
Simulation time	121796700 ps
CPU time	2.51 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:28 PM PST 23
Peak memory	215456 kb
Host	smart-e9844939-9110-4fd1-b2c0-b61d32e7a1aa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259555106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.2259555106 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.692480695
Short name	T122
Test name
Test status
Simulation time	80497171 ps
CPU time	1.12 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:45 PM PST 23
Peak memory	215836 kb
Host	smart-c13eadd4-cc2f-4aee-b798-42f15189d0aa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692480695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_ errors.692480695 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1631824989
Short name	T63
Test name
Test status
Simulation time	143201872 ps
CPU time	2.74 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:38:04 PM PST 23
Peak memory	223632 kb
Host	smart-04e5b0a3-73e2-46f7-be01-3ad02c62649f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631824989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.1631824989 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.2877269280
Short name	T74
Test name
Test status
Simulation time	42772737 ps
CPU time	2.66 seconds
Started	Dec 20 12:37:16 PM PST 23
Finished	Dec 20 12:38:12 PM PST 23
Peak memory	215560 kb
Host	smart-27ecb335-cd5b-4a00-bb76-48cc45f491b2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877269280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.2877269280 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3823400174
Short name	T204
Test name
Test status
Simulation time	75562610 ps
CPU time	1.27 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:06 PM PST 23
Peak memory	215604 kb
Host	smart-5e8516c3-4edd-430f-9716-aa1fa0cd588c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823400174 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3823400174 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1415608004
Short name	T170
Test name
Test status
Simulation time	63534879 ps
CPU time	0.86 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:28 PM PST 23
Peak memory	207204 kb
Host	smart-9853187e-0a10-4691-8019-1e51e8fee782
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415608004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1415608004 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.3789056820
Short name	T85
Test name
Test status
Simulation time	21248014 ps
CPU time	0.7 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:18 PM PST 23
Peak memory	206920 kb
Host	smart-9a0f7795-7488-466a-8e41-ee2029be4445
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789056820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.3789056820 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3548912924
Short name	T12
Test name
Test status
Simulation time	411214881 ps
CPU time	1.66 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:03 PM PST 23
Peak memory	207424 kb
Host	smart-c0ca2da0-ae20-43df-84b7-537d2e050c9e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548912924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.3548912924 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.1546040749
Short name	T142
Test name
Test status
Simulation time	56214236 ps
CPU time	1.41 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:35 PM PST 23
Peak memory	215924 kb
Host	smart-99f04c90-a87f-4b71-ac3b-8f2d15eedca2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546040749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg _errors.1546040749 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.925445994
Short name	T166
Test name
Test status
Simulation time	42023726 ps
CPU time	1.75 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:24 PM PST 23
Peak memory	215748 kb
Host	smart-c8734ae4-4493-4f02-aa4f-5f788cdbf5d7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925445994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac _shadow_reg_errors_with_csr_rw.925445994 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.2147867524
Short name	T210
Test name
Test status
Simulation time	266353152 ps
CPU time	1.81 seconds
Started	Dec 20 12:37:25 PM PST 23
Finished	Dec 20 12:38:36 PM PST 23
Peak memory	215428 kb
Host	smart-95f74ab4-82e4-4089-8ebb-83dbaf760b7d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147867524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2147867524 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.699946236
Short name	T87
Test name
Test status
Simulation time	283681697 ps
CPU time	2.84 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:21 PM PST 23
Peak memory	217644 kb
Host	smart-4c84a250-bfe1-46e8-a69d-32d8fbd83796
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699946236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.69994 6236 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.2834845013
Short name	T20
Test name
Test status
Simulation time	56631218 ps
CPU time	1.69 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:02 PM PST 23
Peak memory	223556 kb
Host	smart-3f14f25d-9d60-41b3-a4ad-08a38ba31e47
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834845013 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.2834845013 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.626772389
Short name	T188
Test name
Test status
Simulation time	20998134 ps
CPU time	0.94 seconds
Started	Dec 20 12:36:43 PM PST 23
Finished	Dec 20 12:37:08 PM PST 23
Peak memory	207132 kb
Host	smart-21f08f8c-1b47-443e-bb67-3e2edf48db0e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626772389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.626772389 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.1281841484
Short name	T115
Test name
Test status
Simulation time	11904323 ps
CPU time	0.73 seconds
Started	Dec 20 12:36:47 PM PST 23
Finished	Dec 20 12:37:17 PM PST 23
Peak memory	206992 kb
Host	smart-35eea758-e61c-47c5-9aaa-e15b278ab024
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281841484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1281841484 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3449881214
Short name	T212
Test name
Test status
Simulation time	208834835 ps
CPU time	2.17 seconds
Started	Dec 20 12:37:52 PM PST 23
Finished	Dec 20 12:39:16 PM PST 23
Peak memory	215392 kb
Host	smart-65bd8664-d898-4d0f-9398-84e846ae5501
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449881214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.3449881214 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.933364193
Short name	T117
Test name
Test status
Simulation time	23979334 ps
CPU time	0.92 seconds
Started	Dec 20 12:37:27 PM PST 23
Finished	Dec 20 12:38:45 PM PST 23
Peak memory	207468 kb
Host	smart-2bf8f820-4127-47cc-8631-7e281855a73c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933364193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_ errors.933364193 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.4139474556
Short name	T111
Test name
Test status
Simulation time	65859491 ps
CPU time	1.59 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:56 PM PST 23
Peak memory	207448 kb
Host	smart-746bfc07-7776-4f66-9e53-8b06ec61f1d1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139474556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma c_shadow_reg_errors_with_csr_rw.4139474556 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3893621198
Short name	T34
Test name
Test status
Simulation time	203119914 ps
CPU time	2 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:30 PM PST 23
Peak memory	215448 kb
Host	smart-fefa553f-5185-45ee-a982-557c890d0ab0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893621198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3893621198 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3514972330
Short name	T172
Test name
Test status
Simulation time	193334314 ps
CPU time	2.45 seconds
Started	Dec 20 12:37:27 PM PST 23
Finished	Dec 20 12:38:43 PM PST 23
Peak memory	207144 kb
Host	smart-ec7948eb-65a6-46dd-b4fc-06171346925c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514972330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3514 972330 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2188814973
Short name	T57
Test name
Test status
Simulation time	183487381 ps
CPU time	1.13 seconds
Started	Dec 20 12:36:59 PM PST 23
Finished	Dec 20 12:37:37 PM PST 23
Peak memory	215580 kb
Host	smart-c8b5cd10-badf-4074-970e-d72633c1dfd7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188814973 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2188814973 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.3253357350
Short name	T196
Test name
Test status
Simulation time	30525439 ps
CPU time	1.09 seconds
Started	Dec 20 12:36:40 PM PST 23
Finished	Dec 20 12:36:55 PM PST 23
Peak memory	207360 kb
Host	smart-d9149051-eee8-4397-b97f-2a094c3d599e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253357350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.3253357350 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.4164453807
Short name	T51
Test name
Test status
Simulation time	20169273 ps
CPU time	0.71 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:37 PM PST 23
Peak memory	207128 kb
Host	smart-14ef038b-eb71-4f71-9421-fa2157608d13
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164453807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.4164453807 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2465676772
Short name	T163
Test name
Test status
Simulation time	189756626 ps
CPU time	2.46 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:38 PM PST 23
Peak memory	215628 kb
Host	smart-e587177a-2521-420d-8645-1f95e13abd0b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465676772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.2465676772 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.4280633970
Short name	T62
Test name
Test status
Simulation time	39622352 ps
CPU time	1.08 seconds
Started	Dec 20 12:37:16 PM PST 23
Finished	Dec 20 12:38:11 PM PST 23
Peak memory	215856 kb
Host	smart-df5ac233-4d5a-4d68-b45e-3dda81b3a44e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280633970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.4280633970 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3817052872
Short name	T192
Test name
Test status
Simulation time	180826574 ps
CPU time	2.49 seconds
Started	Dec 20 12:36:41 PM PST 23
Finished	Dec 20 12:36:58 PM PST 23
Peak memory	216012 kb
Host	smart-a4b633fd-d628-404c-939d-c0f1c59cd79c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817052872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.3817052872 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.3995887015
Short name	T153
Test name
Test status
Simulation time	93792062 ps
CPU time	1.59 seconds
Started	Dec 20 12:36:51 PM PST 23
Finished	Dec 20 12:37:33 PM PST 23
Peak memory	215700 kb
Host	smart-154332dc-3a44-43ea-935b-061c9e307e88
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995887015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3995887015 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3881812746
Short name	T33
Test name
Test status
Simulation time	367409601 ps
CPU time	4.22 seconds
Started	Dec 20 12:37:24 PM PST 23
Finished	Dec 20 12:38:36 PM PST 23
Peak memory	207196 kb
Host	smart-8b8b1fb7-c786-4923-b3bd-ebc8d088e91d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881812746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3881 812746 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2742982978
Short name	T75
Test name
Test status
Simulation time	40219605 ps
CPU time	1.85 seconds
Started	Dec 20 12:37:20 PM PST 23
Finished	Dec 20 12:38:24 PM PST 23
Peak memory	223564 kb
Host	smart-a21147c3-c859-407d-90d0-06192f845688
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742982978 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2742982978 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.1934388564
Short name	T40
Test name
Test status
Simulation time	121329830 ps
CPU time	1.05 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:18 PM PST 23
Peak memory	215388 kb
Host	smart-ea25f9bc-d1b3-46a9-b88f-53622eb64f8c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934388564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1934388564 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.792291434
Short name	T198
Test name
Test status
Simulation time	18479128 ps
CPU time	0.7 seconds
Started	Dec 20 12:36:52 PM PST 23
Finished	Dec 20 12:37:26 PM PST 23
Peak memory	207240 kb
Host	smart-e54d3561-1d0f-47f9-abb5-ef48e4a648bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792291434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.792291434 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.495854609
Short name	T43
Test name
Test status
Simulation time	40184094 ps
CPU time	2.08 seconds
Started	Dec 20 12:36:49 PM PST 23
Finished	Dec 20 12:37:23 PM PST 23
Peak memory	215676 kb
Host	smart-ecc2ec25-5e40-464d-8987-08723b89485a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495854609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr _outstanding.495854609 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.689652615
Short name	T132
Test name
Test status
Simulation time	56344390 ps
CPU time	1.4 seconds
Started	Dec 20 12:36:47 PM PST 23
Finished	Dec 20 12:37:27 PM PST 23
Peak memory	215956 kb
Host	smart-1a513d9d-1705-4f69-ac38-9ca4b576ed65
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689652615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_ errors.689652615 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.416845053
Short name	T116
Test name
Test status
Simulation time	137268244 ps
CPU time	3.02 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	223904 kb
Host	smart-ad4146a1-50bd-4c24-9c2b-eb22c8ee93b2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416845053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac _shadow_reg_errors_with_csr_rw.416845053 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.507908003
Short name	T147
Test name
Test status
Simulation time	396738145 ps
CPU time	4.66 seconds
Started	Dec 20 12:36:55 PM PST 23
Finished	Dec 20 12:37:35 PM PST 23
Peak memory	215660 kb
Host	smart-c457c4d7-5802-49c5-86d9-b64e4857d49d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507908003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.50790 8003 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.829862588
Short name	T177
Test name
Test status
Simulation time	281947614 ps
CPU time	5.56 seconds
Started	Dec 20 12:36:56 PM PST 23
Finished	Dec 20 12:37:38 PM PST 23
Peak memory	207328 kb
Host	smart-57fe9538-e855-4341-8c8e-b9b147492409
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829862588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.82986258 8 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.948224082
Short name	T195
Test name
Test status
Simulation time	651932090 ps
CPU time	8.3 seconds
Started	Dec 20 12:37:46 PM PST 23
Finished	Dec 20 12:39:14 PM PST 23
Peak memory	207528 kb
Host	smart-92264fa7-f865-4c13-8830-033b321dca95
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948224082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.94822408 2 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.692838790
Short name	T140
Test name
Test status
Simulation time	39065911 ps
CPU time	0.92 seconds
Started	Dec 20 12:36:49 PM PST 23
Finished	Dec 20 12:37:21 PM PST 23
Peak memory	207152 kb
Host	smart-a56b5a5e-86e1-4a7d-954c-c835699a1b44
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692838790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.69283879 0 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.392085762
Short name	T174
Test name
Test status
Simulation time	45768364 ps
CPU time	1.63 seconds
Started	Dec 20 12:37:31 PM PST 23
Finished	Dec 20 12:38:46 PM PST 23
Peak memory	223752 kb
Host	smart-c88f5faa-c033-4418-888b-50cf14b5ac10
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392085762 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.392085762 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.2323155710
Short name	T105
Test name
Test status
Simulation time	20465354 ps
CPU time	1.08 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:23 PM PST 23
Peak memory	207392 kb
Host	smart-9306b491-a1ac-4f9a-ba4a-8e64bd6076a5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323155710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2323155710 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.2049748361
Short name	T178
Test name
Test status
Simulation time	19184310 ps
CPU time	0.75 seconds
Started	Dec 20 12:36:47 PM PST 23
Finished	Dec 20 12:37:17 PM PST 23
Peak memory	207136 kb
Host	smart-9492cc05-137b-4236-ace6-b723095a68a4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049748361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2049748361 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.679143449
Short name	T44
Test name
Test status
Simulation time	28023160 ps
CPU time	1.08 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:26 PM PST 23
Peak memory	215380 kb
Host	smart-351e10dd-f5da-4846-ad5c-aeea09651b84
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679143449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial _access.679143449 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.1702672249
Short name	T167
Test name
Test status
Simulation time	20644339 ps
CPU time	0.68 seconds
Started	Dec 20 12:36:48 PM PST 23
Finished	Dec 20 12:37:20 PM PST 23
Peak memory	207132 kb
Host	smart-6826352e-084f-45d1-a255-0126a972ba43
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702672249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1702672249 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2521170374
Short name	T130
Test name
Test status
Simulation time	44029858 ps
CPU time	1.42 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:23 PM PST 23
Peak memory	215248 kb
Host	smart-f973e989-ecff-417c-a94b-c8e9dd26c9de
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521170374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.2521170374 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2400020600
Short name	T48
Test name
Test status
Simulation time	29236581 ps
CPU time	1 seconds
Started	Dec 20 12:36:39 PM PST 23
Finished	Dec 20 12:36:54 PM PST 23
Peak memory	215676 kb
Host	smart-0bf36b47-04fb-4937-be98-a3235d81b348
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400020600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.2400020600 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.453173350
Short name	T64
Test name
Test status
Simulation time	137803165 ps
CPU time	1.72 seconds
Started	Dec 20 12:36:51 PM PST 23
Finished	Dec 20 12:37:26 PM PST 23
Peak memory	215900 kb
Host	smart-1ac593e4-1d96-4530-ab67-78ceb0177aad
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453173350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_ shadow_reg_errors_with_csr_rw.453173350 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.1783738957
Short name	T72
Test name
Test status
Simulation time	407385981 ps
CPU time	2.55 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:37 PM PST 23
Peak memory	215624 kb
Host	smart-c3dd04fc-88ff-4290-9881-9634ef9c3af3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783738957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1783738957 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.2223768914
Short name	T181
Test name
Test status
Simulation time	50911570 ps
CPU time	0.75 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:34 PM PST 23
Peak memory	206904 kb
Host	smart-5678e92f-dcb1-4a48-969f-a21183722898
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223768914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2223768914 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.1704026432
Short name	T189
Test name
Test status
Simulation time	47192628 ps
CPU time	0.73 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:55 PM PST 23
Peak memory	206984 kb
Host	smart-f92c4f5c-9edd-4eff-8585-988983d4943e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704026432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.1704026432 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.719111653
Short name	T168
Test name
Test status
Simulation time	23283708 ps
CPU time	0.75 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:38:02 PM PST 23
Peak memory	207140 kb
Host	smart-62241b83-6af4-402a-b937-db56964405fd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719111653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.719111653 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.2354481954
Short name	T176
Test name
Test status
Simulation time	55507717 ps
CPU time	0.75 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:34 PM PST 23
Peak memory	206764 kb
Host	smart-77728f27-9633-4706-a964-1ceca87729cc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354481954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2354481954 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.3700582294
Short name	T152
Test name
Test status
Simulation time	54814834 ps
CPU time	0.7 seconds
Started	Dec 20 12:37:38 PM PST 23
Finished	Dec 20 12:38:54 PM PST 23
Peak memory	206784 kb
Host	smart-0260e657-c494-41f9-9fc8-14eba192fb43
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700582294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3700582294 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.1252584130
Short name	T208
Test name
Test status
Simulation time	12666927 ps
CPU time	0.73 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:01 PM PST 23
Peak memory	206924 kb
Host	smart-cbb9ccaa-c770-444d-8b9c-d4c8bd09dd23
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252584130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1252584130 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.3776464737
Short name	T127
Test name
Test status
Simulation time	53935881 ps
CPU time	0.72 seconds
Started	Dec 20 12:37:20 PM PST 23
Finished	Dec 20 12:38:20 PM PST 23
Peak memory	207032 kb
Host	smart-05087466-432e-4047-a8f1-2e2880d87ab4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776464737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.3776464737 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.3428852473
Short name	T186
Test name
Test status
Simulation time	15383507 ps
CPU time	0.79 seconds
Started	Dec 20 12:37:31 PM PST 23
Finished	Dec 20 12:38:46 PM PST 23
Peak memory	207064 kb
Host	smart-3bbf42aa-4276-44b2-a15b-83bb9a8eec1f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428852473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3428852473 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1769083137
Short name	T26
Test name
Test status
Simulation time	307592594 ps
CPU time	8.42 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:35 PM PST 23
Peak memory	215284 kb
Host	smart-153db581-d8e5-4dda-a2a6-6c8aa06b30b7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769083137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1769083 137 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1623738606
Short name	T185
Test name
Test status
Simulation time	2167229903 ps
CPU time	18.09 seconds
Started	Dec 20 12:37:15 PM PST 23
Finished	Dec 20 12:38:24 PM PST 23
Peak memory	207236 kb
Host	smart-73b78708-023a-4053-852f-9ab4ddb54127
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623738606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1623738 606 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.2859288417
Short name	T11
Test name
Test status
Simulation time	21179689 ps
CPU time	1.07 seconds
Started	Dec 20 12:37:16 PM PST 23
Finished	Dec 20 12:38:10 PM PST 23
Peak memory	207304 kb
Host	smart-c3b5f2c4-e378-422c-8821-23803cb7f37a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859288417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.2859288 417 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2563086004
Short name	T139
Test name
Test status
Simulation time	61184423 ps
CPU time	1.48 seconds
Started	Dec 20 12:36:40 PM PST 23
Finished	Dec 20 12:36:56 PM PST 23
Peak memory	215476 kb
Host	smart-31500946-1d95-4da6-809f-dce8249a6267
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563086004 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2563086004 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1398067675
Short name	T93
Test name
Test status
Simulation time	61768411 ps
CPU time	0.88 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:05 PM PST 23
Peak memory	206940 kb
Host	smart-af148318-a2cb-404c-9a34-5ec7f62253eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398067675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1398067675 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.1640411968
Short name	T9
Test name
Test status
Simulation time	48209848 ps
CPU time	0.75 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:14 PM PST 23
Peak memory	206924 kb
Host	smart-6a95a20a-9dc8-4b81-9117-f6a514c6d34a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640411968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1640411968 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.4133396551
Short name	T50
Test name
Test status
Simulation time	24443273 ps
CPU time	1.15 seconds
Started	Dec 20 12:36:54 PM PST 23
Finished	Dec 20 12:37:30 PM PST 23
Peak memory	215240 kb
Host	smart-4bfcf6c7-0c0f-4560-8fbc-da99f00a1dcd
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133396551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.4133396551 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.3365097630
Short name	T99
Test name
Test status
Simulation time	31683239 ps
CPU time	0.66 seconds
Started	Dec 20 12:37:04 PM PST 23
Finished	Dec 20 12:37:45 PM PST 23
Peak memory	207196 kb
Host	smart-0b0c53a0-a571-49fa-b772-9663e5086522
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365097630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.3365097630 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3959557147
Short name	T156
Test name
Test status
Simulation time	70255989 ps
CPU time	2.13 seconds
Started	Dec 20 12:37:25 PM PST 23
Finished	Dec 20 12:38:38 PM PST 23
Peak memory	215752 kb
Host	smart-598b7f8a-fd94-4d22-a636-9fe9283d80ff
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959557147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.3959557147 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.4083735626
Short name	T131
Test name
Test status
Simulation time	21498964 ps
CPU time	1.03 seconds
Started	Dec 20 12:37:20 PM PST 23
Finished	Dec 20 12:38:22 PM PST 23
Peak memory	215872 kb
Host	smart-96ba96a6-78d9-4602-a76a-a1233f023189
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083735626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.4083735626 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1648073673
Short name	T119
Test name
Test status
Simulation time	40659124 ps
CPU time	1.67 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:02 PM PST 23
Peak memory	215980 kb
Host	smart-524ce4a4-7761-42d9-b5ed-18edcb1a18ba
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648073673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.1648073673 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.3190800288
Short name	T213
Test name
Test status
Simulation time	938024352 ps
CPU time	2.39 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:36 PM PST 23
Peak memory	215548 kb
Host	smart-57cab454-b82d-4542-a682-a598f1713b14
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190800288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3190800288 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.3459180051
Short name	T171
Test name
Test status
Simulation time	44314816 ps
CPU time	0.73 seconds
Started	Dec 20 12:37:25 PM PST 23
Finished	Dec 20 12:38:37 PM PST 23
Peak memory	207300 kb
Host	smart-3e025309-34eb-433d-99b1-f50102604e77
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459180051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3459180051 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.565543047
Short name	T137
Test name
Test status
Simulation time	17624587 ps
CPU time	0.74 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:46 PM PST 23
Peak memory	207156 kb
Host	smart-7503007b-47f5-47af-b9c4-69925974c6df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565543047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.565543047 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2796369269
Short name	T103
Test name
Test status
Simulation time	15460955 ps
CPU time	0.78 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:33 PM PST 23
Peak memory	207116 kb
Host	smart-752fe5c9-2de2-4f4b-8ab6-a9081c7eb812
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796369269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2796369269 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.2783379074
Short name	T102
Test name
Test status
Simulation time	15488167 ps
CPU time	0.77 seconds
Started	Dec 20 12:37:26 PM PST 23
Finished	Dec 20 12:38:39 PM PST 23
Peak memory	207236 kb
Host	smart-b8d0c504-53a3-492d-8f3a-09e9d8febc52
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783379074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2783379074 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.3439359844
Short name	T1
Test name
Test status
Simulation time	30811334 ps
CPU time	0.73 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:25 PM PST 23
Peak memory	207232 kb
Host	smart-010a2efd-afed-49bd-8a3a-cb7aaf37084d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439359844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3439359844 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.3054514177
Short name	T83
Test name
Test status
Simulation time	18033737 ps
CPU time	0.7 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:55 PM PST 23
Peak memory	207160 kb
Host	smart-dc555b3c-2d62-4897-a43b-e5b618c4e211
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054514177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3054514177 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.2459421001
Short name	T155
Test name
Test status
Simulation time	56731229 ps
CPU time	0.72 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:03 PM PST 23
Peak memory	207232 kb
Host	smart-115cc475-efe9-4190-9c94-a64f8edc5e29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459421001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.2459421001 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.2834569913
Short name	T82
Test name
Test status
Simulation time	115217870 ps
CPU time	0.76 seconds
Started	Dec 20 12:37:11 PM PST 23
Finished	Dec 20 12:37:56 PM PST 23
Peak memory	207048 kb
Host	smart-1c9611cf-22f8-4e9c-ac78-355e30285321
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834569913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.2834569913 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.3520912370
Short name	T112
Test name
Test status
Simulation time	33259350 ps
CPU time	0.73 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:29 PM PST 23
Peak memory	207080 kb
Host	smart-66784a83-40b9-4e78-8871-5072c406c7d9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520912370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3520912370 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.355922191
Short name	T135
Test name
Test status
Simulation time	14871235 ps
CPU time	0.73 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:01 PM PST 23
Peak memory	206992 kb
Host	smart-61b2f0ed-da9b-4315-b2f8-31ac883e78a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355922191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.355922191 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1357172400
Short name	T154
Test name
Test status
Simulation time	310661601 ps
CPU time	4.85 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:42 PM PST 23
Peak memory	207240 kb
Host	smart-9cfd380b-5ad6-46cf-9ce4-387a1504f2be
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357172400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1357172 400 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.458373533
Short name	T100
Test name
Test status
Simulation time	163032629 ps
CPU time	8.2 seconds
Started	Dec 20 12:36:31 PM PST 23
Finished	Dec 20 12:36:44 PM PST 23
Peak memory	207320 kb
Host	smart-41e5a1e6-9915-4b84-8df1-9b0538e13380
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458373533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.45837353 3 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3956085689
Short name	T193
Test name
Test status
Simulation time	66413979 ps
CPU time	1.02 seconds
Started	Dec 20 12:36:28 PM PST 23
Finished	Dec 20 12:36:33 PM PST 23
Peak memory	207384 kb
Host	smart-1c27f85f-594c-4780-b823-1e3b8bd533f0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956085689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3956085 689 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1763448253
Short name	T16
Test name
Test status
Simulation time	40576741 ps
CPU time	1.87 seconds
Started	Dec 20 12:36:40 PM PST 23
Finished	Dec 20 12:36:57 PM PST 23
Peak memory	223728 kb
Host	smart-dc5d2218-502c-47aa-bf4d-f214a24a716b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763448253 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.1763448253 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.1187783248
Short name	T175
Test name
Test status
Simulation time	21306387 ps
CPU time	0.91 seconds
Started	Dec 20 12:37:34 PM PST 23
Finished	Dec 20 12:38:50 PM PST 23
Peak memory	207144 kb
Host	smart-7e19ff05-01ff-4f79-a40d-251766b87927
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187783248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1187783248 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3673084491
Short name	T214
Test name
Test status
Simulation time	19220270 ps
CPU time	0.73 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:45 PM PST 23
Peak memory	207120 kb
Host	smart-ee404e22-ed8d-4709-a399-fea301179210
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673084491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3673084491 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2128658453
Short name	T53
Test name
Test status
Simulation time	138707149 ps
CPU time	1.44 seconds
Started	Dec 20 12:36:31 PM PST 23
Finished	Dec 20 12:36:37 PM PST 23
Peak memory	215524 kb
Host	smart-db724efe-6e38-4d28-9b0e-f92cf66fdffa
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128658453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.2128658453 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.3064083846
Short name	T141
Test name
Test status
Simulation time	11664041 ps
CPU time	0.7 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:26 PM PST 23
Peak memory	207052 kb
Host	smart-8399b09b-c23c-443e-b71b-256caa93e8c8
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064083846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3064083846 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2494917217
Short name	T203
Test name
Test status
Simulation time	593181296 ps
CPU time	2.5 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:32 PM PST 23
Peak memory	215736 kb
Host	smart-56ce1933-5667-4253-a44d-01f46cd74e26
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494917217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.2494917217 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.889354734
Short name	T66
Test name
Test status
Simulation time	174342809 ps
CPU time	1.39 seconds
Started	Dec 20 12:37:07 PM PST 23
Finished	Dec 20 12:37:50 PM PST 23
Peak memory	215656 kb
Host	smart-7e17b383-0375-401b-acad-98991af428b3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889354734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_e rrors.889354734 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2733108280
Short name	T24
Test name
Test status
Simulation time	153928362 ps
CPU time	1.82 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:21 PM PST 23
Peak memory	223392 kb
Host	smart-b3a8d09d-caa3-4e46-bb5b-223dda1150fa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733108280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.2733108280 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3820524205
Short name	T187
Test name
Test status
Simulation time	704992551 ps
CPU time	3.01 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:16 PM PST 23
Peak memory	215608 kb
Host	smart-e50c49d2-01a6-460c-b977-33e4b121e768
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820524205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3820524205 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.248418060
Short name	T56
Test name
Test status
Simulation time	764557115 ps
CPU time	2.96 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:47 PM PST 23
Peak memory	215504 kb
Host	smart-f1dac2c0-c543-46da-b25e-cc27471d5e9a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248418060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.248418 060 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.1427281246
Short name	T104
Test name
Test status
Simulation time	21593419 ps
CPU time	0.73 seconds
Started	Dec 20 12:37:25 PM PST 23
Finished	Dec 20 12:38:37 PM PST 23
Peak memory	207148 kb
Host	smart-7acb3f98-e1fc-432c-89e7-95d2a9a4a182
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427281246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1427281246 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.3534921410
Short name	T209
Test name
Test status
Simulation time	36524819 ps
CPU time	0.76 seconds
Started	Dec 20 12:37:26 PM PST 23
Finished	Dec 20 12:38:39 PM PST 23
Peak memory	206916 kb
Host	smart-7dc7a209-101a-411e-9941-827d3aa78f2d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534921410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3534921410 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.626336121
Short name	T10
Test name
Test status
Simulation time	32088359 ps
CPU time	0.73 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:03 PM PST 23
Peak memory	207200 kb
Host	smart-a0ef9528-663d-4aa0-a503-e19025d32537
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626336121 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.626336121 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.2410528771
Short name	T108
Test name
Test status
Simulation time	50076669 ps
CPU time	0.72 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:37:59 PM PST 23
Peak memory	207168 kb
Host	smart-b704d311-e332-4cbd-ba2c-9ef9c9c04a1d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410528771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2410528771 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.2951564529
Short name	T8
Test name
Test status
Simulation time	12696897 ps
CPU time	0.72 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:01 PM PST 23
Peak memory	207204 kb
Host	smart-24c804c7-2613-4b56-bd10-c0833d9ecc07
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951564529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2951564529 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.4173067191
Short name	T125
Test name
Test status
Simulation time	38169489 ps
CPU time	0.74 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:55 PM PST 23
Peak memory	207192 kb
Host	smart-7f35333d-95c0-4781-a768-51b3580d7c6a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173067191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.4173067191 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.1895096
Short name	T110
Test name
Test status
Simulation time	30550847 ps
CPU time	0.75 seconds
Started	Dec 20 12:39:00 PM PST 23
Finished	Dec 20 12:40:14 PM PST 23
Peak memory	206736 kb
Host	smart-35776570-f245-4f3a-a133-42121e5188d7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1895096 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.1793592350
Short name	T161
Test name
Test status
Simulation time	31952485 ps
CPU time	0.71 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:20 PM PST 23
Peak memory	206928 kb
Host	smart-b856cb61-1a93-4d3f-b28d-89f081e35873
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793592350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1793592350 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2272370651
Short name	T84
Test name
Test status
Simulation time	43509480 ps
CPU time	0.74 seconds
Started	Dec 20 12:39:02 PM PST 23
Finished	Dec 20 12:40:08 PM PST 23
Peak memory	206744 kb
Host	smart-59c7842f-d04e-4940-bf89-99ce3cee86f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272370651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2272370651 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.1245043562
Short name	T190
Test name
Test status
Simulation time	16912612 ps
CPU time	0.74 seconds
Started	Dec 20 12:39:14 PM PST 23
Finished	Dec 20 12:40:23 PM PST 23
Peak memory	206668 kb
Host	smart-c78bcb09-4e72-4ceb-8f30-5c15637b2004
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245043562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1245043562 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.527713428
Short name	T180
Test name
Test status
Simulation time	36054009 ps
CPU time	2.28 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:38 PM PST 23
Peak memory	223892 kb
Host	smart-370f3189-426a-4ed0-b3a2-528bd3129d2a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527713428 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.527713428 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.3917241715
Short name	T149
Test name
Test status
Simulation time	20522354 ps
CPU time	0.96 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:35 PM PST 23
Peak memory	207364 kb
Host	smart-5bb36506-dd89-463f-b309-e7f151e78d23
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917241715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3917241715 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.1448387644
Short name	T106
Test name
Test status
Simulation time	58260392 ps
CPU time	0.82 seconds
Started	Dec 20 12:36:33 PM PST 23
Finished	Dec 20 12:36:39 PM PST 23
Peak memory	207152 kb
Host	smart-afcbd4db-3d5a-4cee-811b-658d754f60b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448387644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.1448387644 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2207722560
Short name	T194
Test name
Test status
Simulation time	79563437 ps
CPU time	2.22 seconds
Started	Dec 20 12:36:39 PM PST 23
Finished	Dec 20 12:36:54 PM PST 23
Peak memory	215436 kb
Host	smart-75d01809-ee21-4217-9741-d8d51371c56b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207722560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.2207722560 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1729104089
Short name	T200
Test name
Test status
Simulation time	121334018 ps
CPU time	1.04 seconds
Started	Dec 20 12:36:51 PM PST 23
Finished	Dec 20 12:37:26 PM PST 23
Peak memory	215924 kb
Host	smart-931b826a-e1de-48d8-a89e-138320a333c9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729104089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.1729104089 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.3330461981
Short name	T191
Test name
Test status
Simulation time	55630850 ps
CPU time	1.62 seconds
Started	Dec 20 12:37:06 PM PST 23
Finished	Dec 20 12:37:50 PM PST 23
Peak memory	218268 kb
Host	smart-21f27169-7508-4a4c-ba51-3bbe74b11c52
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330461981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3330461981 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.3264497616
Short name	T88
Test name
Test status
Simulation time	635235698 ps
CPU time	2.94 seconds
Started	Dec 20 12:36:31 PM PST 23
Finished	Dec 20 12:36:39 PM PST 23
Peak memory	215656 kb
Host	smart-4ef49138-f6eb-45d9-9e04-5c1c5c54e6d7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264497616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.32644 97616 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.43718923
Short name	T54
Test name
Test status
Simulation time	77989085 ps
CPU time	1.42 seconds
Started	Dec 20 12:37:03 PM PST 23
Finished	Dec 20 12:37:44 PM PST 23
Peak memory	215560 kb
Host	smart-573200de-0e55-4990-9ed5-748ef8c91012
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43718923 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.43718923 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.920168156
Short name	T184
Test name
Test status
Simulation time	32498773 ps
CPU time	0.99 seconds
Started	Dec 20 12:37:26 PM PST 23
Finished	Dec 20 12:38:45 PM PST 23
Peak memory	207380 kb
Host	smart-90fae89c-bc3d-405f-a7fc-5cabaf6a76f3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920168156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.920168156 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.974161220
Short name	T81
Test name
Test status
Simulation time	38630643 ps
CPU time	0.75 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:13 PM PST 23
Peak memory	206952 kb
Host	smart-a421f872-fbb3-4fc8-8a12-90046542c0e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974161220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.974161220 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.4202663802
Short name	T58
Test name
Test status
Simulation time	85482551 ps
CPU time	2.31 seconds
Started	Dec 20 12:37:26 PM PST 23
Finished	Dec 20 12:38:41 PM PST 23
Peak memory	215548 kb
Host	smart-13a6f86f-b121-47da-968c-cfa3e397c6d4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202663802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.4202663802 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2288738475
Short name	T68
Test name
Test status
Simulation time	34157023 ps
CPU time	1.05 seconds
Started	Dec 20 12:37:02 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	215820 kb
Host	smart-997ecea7-d8ab-48f1-8a2c-8cb90fa87fd7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288738475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.2288738475 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3538196
Short name	T206
Test name
Test status
Simulation time	158895097 ps
CPU time	3.02 seconds
Started	Dec 20 12:37:02 PM PST 23
Finished	Dec 20 12:37:43 PM PST 23
Peak memory	223092 kb
Host	smart-565c9b00-4863-42a5-88bb-6ef2605a33ba
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ =kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_sh adow_reg_errors_with_csr_rw.3538196 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.1666612318
Short name	T23
Test name
Test status
Simulation time	105645678 ps
CPU time	1.74 seconds
Started	Dec 20 12:36:43 PM PST 23
Finished	Dec 20 12:37:09 PM PST 23
Peak memory	215580 kb
Host	smart-bb965c00-ba91-45fb-a04f-7bb982ff13f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666612318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1666612318 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.3787557977
Short name	T91
Test name
Test status
Simulation time	235629794 ps
CPU time	3.91 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:26 PM PST 23
Peak memory	215516 kb
Host	smart-87c3e166-4cff-4f65-82b7-705d2e6b587e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787557977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.37875 57977 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1388010406
Short name	T215
Test name
Test status
Simulation time	34160301 ps
CPU time	1.19 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:49 PM PST 23
Peak memory	215572 kb
Host	smart-78e651b7-8c39-4d9f-b94d-727b7ddab9ab
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388010406 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.1388010406 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.3233970818
Short name	T107
Test name
Test status
Simulation time	48965399 ps
CPU time	0.92 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:38:02 PM PST 23
Peak memory	206900 kb
Host	smart-8e67fb40-adf3-4b69-97b0-6db44b2bb04d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233970818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.3233970818 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.2455448968
Short name	T160
Test name
Test status
Simulation time	16475742 ps
CPU time	0.74 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:32 PM PST 23
Peak memory	207148 kb
Host	smart-e3d0593a-b3f7-4ae9-8319-4097a3e0b4f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455448968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.2455448968 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.1833959966
Short name	T61
Test name
Test status
Simulation time	73566497 ps
CPU time	2.24 seconds
Started	Dec 20 12:36:55 PM PST 23
Finished	Dec 20 12:37:33 PM PST 23
Peak memory	215404 kb
Host	smart-e5f5ab24-b58b-4902-8fcc-ef14b8bef987
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833959966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr _outstanding.1833959966 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2140104279
Short name	T179
Test name
Test status
Simulation time	189409573 ps
CPU time	1.33 seconds
Started	Dec 20 12:37:03 PM PST 23
Finished	Dec 20 12:37:43 PM PST 23
Peak memory	215880 kb
Host	smart-02cd777c-2aa6-457c-854d-19756c9918eb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140104279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.2140104279 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3150505381
Short name	T205
Test name
Test status
Simulation time	349683013 ps
CPU time	1.91 seconds
Started	Dec 20 12:37:31 PM PST 23
Finished	Dec 20 12:38:47 PM PST 23
Peak memory	215852 kb
Host	smart-18168fe7-5553-400f-9210-4b524f2d6a29
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150505381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.3150505381 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.3838675414
Short name	T73
Test name
Test status
Simulation time	35634919 ps
CPU time	1.19 seconds
Started	Dec 20 12:37:15 PM PST 23
Finished	Dec 20 12:38:07 PM PST 23
Peak memory	215440 kb
Host	smart-64b3af77-c2a9-4117-add8-7837fa7087d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838675414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3838675414 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.179000402
Short name	T31
Test name
Test status
Simulation time	132565676 ps
CPU time	2.92 seconds
Started	Dec 20 12:37:31 PM PST 23
Finished	Dec 20 12:38:49 PM PST 23
Peak memory	207076 kb
Host	smart-0310db11-c1a6-4a63-b269-48ec83ae7de8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179000402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.179000 402 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1245783504
Short name	T29
Test name
Test status
Simulation time	54213633 ps
CPU time	2.26 seconds
Started	Dec 20 12:36:54 PM PST 23
Finished	Dec 20 12:37:31 PM PST 23
Peak memory	223712 kb
Host	smart-a6c5e8d3-c7dd-4cf2-aabf-b76287150dc0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245783504 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.1245783504 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.2599101563
Short name	T120
Test name
Test status
Simulation time	120548414 ps
CPU time	1.17 seconds
Started	Dec 20 12:36:47 PM PST 23
Finished	Dec 20 12:37:19 PM PST 23
Peak memory	207380 kb
Host	smart-7bc3c34a-059b-44fe-a6de-c88e0a917175
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599101563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2599101563 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.3550773682
Short name	T151
Test name
Test status
Simulation time	16426865 ps
CPU time	0.72 seconds
Started	Dec 20 12:36:55 PM PST 23
Finished	Dec 20 12:37:31 PM PST 23
Peak memory	207148 kb
Host	smart-945da3f6-2f28-45a7-90fc-e36b9d71a20a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550773682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3550773682 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.2692705567
Short name	T42
Test name
Test status
Simulation time	205494572 ps
CPU time	2.43 seconds
Started	Dec 20 12:37:26 PM PST 23
Finished	Dec 20 12:38:40 PM PST 23
Peak memory	215428 kb
Host	smart-81f528af-46db-4d1a-b939-61c3faf777ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692705567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr _outstanding.2692705567 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2118638169
Short name	T98
Test name
Test status
Simulation time	494463531 ps
CPU time	2.91 seconds
Started	Dec 20 12:36:45 PM PST 23
Finished	Dec 20 12:37:13 PM PST 23
Peak memory	223236 kb
Host	smart-de81782d-9b6f-4f93-b503-b708257beb8c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118638169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.2118638169 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3225706767
Short name	T199
Test name
Test status
Simulation time	201263589 ps
CPU time	3.9 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:55 PM PST 23
Peak memory	215524 kb
Host	smart-0d792084-2736-481c-8ba7-f8c0fc1d11c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225706767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.32257 06767 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.305403379
Short name	T45
Test name
Test status
Simulation time	56927660 ps
CPU time	1.24 seconds
Started	Dec 20 12:36:45 PM PST 23
Finished	Dec 20 12:37:12 PM PST 23
Peak memory	215584 kb
Host	smart-79274999-46a3-4cb8-97b5-d0482054693a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305403379 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.305403379 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.3734960721
Short name	T113
Test name
Test status
Simulation time	21704780 ps
CPU time	0.96 seconds
Started	Dec 20 12:37:15 PM PST 23
Finished	Dec 20 12:38:09 PM PST 23
Peak memory	207380 kb
Host	smart-d048c443-4d13-4dc1-93d7-27db4498b223
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734960721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3734960721 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.2155151831
Short name	T78
Test name
Test status
Simulation time	14180087 ps
CPU time	0.78 seconds
Started	Dec 20 12:36:52 PM PST 23
Finished	Dec 20 12:37:26 PM PST 23
Peak memory	207144 kb
Host	smart-a92849fd-a791-4019-80a1-f697b4794ab9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155151831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.2155151831 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.4129025419
Short name	T128
Test name
Test status
Simulation time	239085006 ps
CPU time	1.74 seconds
Started	Dec 20 12:37:24 PM PST 23
Finished	Dec 20 12:38:38 PM PST 23
Peak memory	215704 kb
Host	smart-7807646c-d9e5-43d4-8e84-337395e9945e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129025419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.4129025419 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.2453564713
Short name	T69
Test name
Test status
Simulation time	36408840 ps
CPU time	1.18 seconds
Started	Dec 20 12:36:42 PM PST 23
Finished	Dec 20 12:37:04 PM PST 23
Peak memory	215920 kb
Host	smart-57d450c1-87de-467c-bf5b-fdaa508f3abf
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453564713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.2453564713 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3162928209
Short name	T182
Test name
Test status
Simulation time	221561417 ps
CPU time	2.87 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:18 PM PST 23
Peak memory	223760 kb
Host	smart-f59ea9bc-ce0e-4387-a33c-b6b7ab82836b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162928209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.3162928209 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.3112066853
Short name	T18
Test name
Test status
Simulation time	204567950 ps
CPU time	2.55 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:11 PM PST 23
Peak memory	218592 kb
Host	smart-a97049c1-0468-49ae-bf8a-532355628e5b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112066853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3112066853 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.2313462223
Short name	T32
Test name
Test status
Simulation time	57405684 ps
CPU time	2.41 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:11 PM PST 23
Peak memory	215604 kb
Host	smart-71f472c7-745a-422b-93d2-9f740ac508bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313462223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.23134 62223 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest