Unified Coverage Report :: Group :: kmac_env_pkg::config_unmasked_cg

Group : kmac_env_pkg::config_unmasked_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::config_unmasked_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	23	23	0	0.00
Crosses	4	4	0	0.00

Variables for Group kmac_env_pkg::config_unmasked_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
key_len	5	5	0	0.00	100	1	1	0
kmac_en	2	2	0	0.00	100	1	1	2
mode	3	3	0	0.00	100	1	1	0
msg_endian	2	2	0	0.00	100	1	1	2
sideload	2	2	0	0.00	100	1	1	2
state_endian	2	2	0	0.00	100	1	1	2
strength	5	5	0	0.00	100	1	1	0
xof_en	2	2	0	0.00	100	1	1	2

Crosses for Group kmac_env_pkg::config_unmasked_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
kmac_cross	1	1	0	0.00	100	1	1	0
cshake_cross	1	1	0	0.00	100	1	1	0
shake_cross	1	1	0	0.00	100	1	1	0
sha3_cross	1	1	0	0.00	100	1	1	0

Summary for Variable key_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	5	0	0.00

Automatically Generated Bins for key_len

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[Key128]	0	1	1
auto[Key192]	0	1	1
auto[Key256]	0	1	1
auto[Key384]	0	1	1
auto[Key512]	0	1	1

---

Summary for Variable kmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for kmac_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	3	0	0.00

Automatically Generated Bins for mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[Sha3]	0	1	1
auto[Shake]	0	1	1
auto[CShake]	0	1	1

---

Summary for Variable msg_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for msg_endian

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable sideload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for sideload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for state_endian

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	5	0	0.00

Automatically Generated Bins for strength

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[L128]	0	1	1
auto[L224]	0	1	1
auto[L256]	0	1	1
auto[L384]	0	1	1
auto[L512]	0	1	1

---

Summary for Variable xof_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for xof_en

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross kmac_cross

Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	1	0	0.00

User Defined Cross Bins for kmac_cross

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valid	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

---

Summary for Cross cshake_cross

Samples crossed: mode strength msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	1	0	0.00

User Defined Cross Bins for cshake_cross

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valid	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

---

Summary for Cross shake_cross

Samples crossed: mode strength msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	1	0	0.00

User Defined Cross Bins for shake_cross

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valid	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

---

Summary for Cross sha3_cross

Samples crossed: mode strength msg_endian state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	1	0	0.00

User Defined Cross Bins for sha3_cross

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
valid	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded