Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 284 1 T1 7 T8 4 T9 7
all_values[1] 284 1 T1 7 T8 4 T9 7
all_values[2] 284 1 T1 7 T8 4 T9 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 449 1 T1 12 T8 3 T9 8
auto[1] 403 1 T1 9 T8 9 T9 13


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 345 1 T1 8 T8 4 T9 3
auto[1] 507 1 T1 13 T8 8 T9 18


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 498 1 T1 11 T8 6 T9 8
auto[1] 354 1 T1 10 T8 6 T9 13


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 54 1 T1 2 T82 6 T78 1
all_values[0] auto[0] auto[0] auto[1] 17 1 T10 1 T77 1 T81 1
all_values[0] auto[0] auto[1] auto[0] 56 1 T1 1 T8 2 T10 2
all_values[0] auto[0] auto[1] auto[1] 29 1 T9 1 T77 3 T83 1
all_values[0] auto[1] auto[0] auto[1] 67 1 T1 4 T9 2 T10 1
all_values[0] auto[1] auto[1] auto[1] 61 1 T8 2 T9 4 T10 3
all_values[1] auto[0] auto[0] auto[0] 53 1 T10 2 T77 2 T83 3
all_values[1] auto[0] auto[0] auto[1] 21 1 T81 1 T84 1 T85 2
all_values[1] auto[0] auto[1] auto[0] 57 1 T1 3 T77 2 T82 1
all_values[1] auto[0] auto[1] auto[1] 33 1 T1 1 T8 1 T9 1
all_values[1] auto[1] auto[0] auto[1] 69 1 T1 2 T9 2 T10 4
all_values[1] auto[1] auto[1] auto[1] 51 1 T1 1 T8 3 T9 4
all_values[2] auto[0] auto[0] auto[0] 70 1 T1 1 T8 1 T9 2
all_values[2] auto[0] auto[0] auto[1] 29 1 T8 1 T9 2 T82 1
all_values[2] auto[0] auto[1] auto[0] 55 1 T1 1 T8 1 T9 1
all_values[2] auto[0] auto[1] auto[1] 24 1 T1 2 T9 1 T77 1
all_values[2] auto[1] auto[0] auto[1] 69 1 T1 3 T8 1 T82 1
all_values[2] auto[1] auto[1] auto[1] 37 1 T9 1 T10 2 T77 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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