Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	255657206	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

203156429

1

T1

65

T2

493

T3

91

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	241555525	1			T1	142		T2	355		T3	76
values[0x0]	104226099	1			T1	6		T2	145		T3	26
values[0x1]	113032011	1			T1	3		T2	131		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199054166	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

259759469

1

T1

85

T2

526

T3

106

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1401645	1			T3	5		T52	1		T58	13
valid_sources[0x01]	2257714	1			T3	1		T52	1		T55	1
valid_sources[0x02]	1382018	1			T57	5		T58	5		T81	2
valid_sources[0x03]	1377459	1			T55	1		T81	5		T90	3
valid_sources[0x04]	1381016	1			T57	3		T58	2		T81	20
valid_sources[0x05]	1843777	1			T57	4		T58	1		T55	4
valid_sources[0x06]	1375885	1			T57	1		T58	7		T55	1
valid_sources[0x07]	1372187	1			T57	2		T58	10		T55	1
valid_sources[0x08]	1426475	1			T3	1		T52	1		T57	1
valid_sources[0x09]	2411525	1			T52	3		T57	5		T58	5
valid_sources[0x0a]	5268819	1			T57	3		T58	10		T90	2
valid_sources[0x0b]	1380265	1			T3	7		T57	2		T58	2
valid_sources[0x0c]	1373232	1			T53	2		T57	1		T58	3
valid_sources[0x0d]	1378189	1			T3	1		T52	3		T57	3
valid_sources[0x0e]	1376152	1			T58	7		T90	1		T56	3
valid_sources[0x0f]	1866397	1			T57	2		T58	4		T55	1
valid_sources[0x10]	1372150	1			T3	4		T57	1		T58	7
valid_sources[0x11]	1385528	1			T52	7		T53	2		T57	2
valid_sources[0x12]	1398731	1			T57	2		T58	2		T61	11
valid_sources[0x13]	1381977	1			T58	3		T55	1		T81	2
valid_sources[0x14]	1380318	1			T52	1		T57	7		T58	7
valid_sources[0x15]	1382570	1			T52	1		T58	12		T81	6
valid_sources[0x16]	1461231	1			T52	4		T57	5		T55	1
valid_sources[0x17]	1375882	1			T1	37		T3	2		T57	2
valid_sources[0x18]	2290791	1			T57	4		T58	4		T55	1
valid_sources[0x19]	3488102	1			T53	1		T58	3		T55	2
valid_sources[0x1a]	1379928	1			T53	1		T57	2		T55	1
valid_sources[0x1b]	1381469	1			T3	1		T58	3		T81	1
valid_sources[0x1c]	1383375	1			T3	6		T58	7		T55	1
valid_sources[0x1d]	2171457	1			T57	4		T58	4		T80	2
valid_sources[0x1e]	1383925	1			T53	1		T58	9		T97	1
valid_sources[0x1f]	1375784	1			T57	3		T58	8		T55	1
valid_sources[0x20]	1375227	1			T58	9		T81	10		T90	8
valid_sources[0x21]	1846463	1			T3	6		T52	8		T57	1
valid_sources[0x22]	1424767	1			T57	5		T139	2		T97	7
valid_sources[0x23]	1377978	1			T52	1		T53	2		T57	2
valid_sources[0x24]	1374732	1			T57	4		T58	7		T55	3
valid_sources[0x25]	1388356	1			T53	1		T58	2		T55	1
valid_sources[0x26]	3792814	1			T57	3		T58	11		T90	1
valid_sources[0x27]	1405559	1			T57	2		T58	1		T55	2
valid_sources[0x28]	2989904	1			T55	1		T80	4		T81	8
valid_sources[0x29]	1379767	1			T52	2		T57	3		T58	4
valid_sources[0x2a]	2719627	1			T3	2		T53	1		T57	7
valid_sources[0x2b]	1755222	1			T53	1		T57	2		T58	1
valid_sources[0x2c]	1388337	1			T53	1		T55	1		T80	2
valid_sources[0x2d]	2073516	1			T52	4		T57	4		T58	4
valid_sources[0x2e]	1386839	1			T58	16		T55	2		T81	7
valid_sources[0x2f]	1478469	1			T57	7		T58	4		T55	1
valid_sources[0x30]	1381595	1			T57	1		T58	1		T55	1
valid_sources[0x31]	1508157	1			T57	4		T58	13		T55	3
valid_sources[0x32]	1376948	1			T3	2		T52	3		T57	1
valid_sources[0x33]	1377301	1			T52	4		T53	1		T58	7
valid_sources[0x34]	1593622	1			T3	4		T58	11		T55	1
valid_sources[0x35]	3441754	1			T57	2		T58	11		T55	1
valid_sources[0x36]	1518839	1			T58	3		T55	1		T80	1
valid_sources[0x37]	1987108	1			T3	1		T58	6		T55	3
valid_sources[0x38]	1375459	1			T3	2		T58	1		T80	1
valid_sources[0x39]	2076896	1			T57	2		T58	6		T55	1
valid_sources[0x3a]	1502551	1			T52	2		T58	3		T81	22
valid_sources[0x3b]	2353354	1			T52	4		T57	4		T58	9
valid_sources[0x3c]	3412352	1			T52	1		T57	17		T58	6
valid_sources[0x3d]	1412022	1			T3	1		T57	2		T58	5
valid_sources[0x3e]	1389821	1			T58	1		T55	2		T56	1
valid_sources[0x3f]	1384929	1			T58	5		T55	1		T81	3
valid_sources[0x40]	4362296	1			T58	4		T80	1		T81	16
valid_sources[0x41]	2285483	1			T52	1		T58	2		T55	3
valid_sources[0x42]	1378897	1			T57	6		T58	1		T55	3
valid_sources[0x43]	1371580	1			T53	1		T58	2		T91	2
valid_sources[0x44]	1384475	1			T3	1		T53	1		T57	3
valid_sources[0x45]	1377569	1			T52	4		T53	3		T58	1
valid_sources[0x46]	2053405	1			T52	1		T57	1		T58	3
valid_sources[0x47]	1377941	1			T58	12		T61	2		T97	8
valid_sources[0x48]	1834579	1			T52	1		T58	8		T55	1
valid_sources[0x49]	1935071	1			T58	6		T55	1		T81	6
valid_sources[0x4a]	1480846	1			T57	1		T58	1		T55	1
valid_sources[0x4b]	1382644	1			T3	1		T52	2		T57	2
valid_sources[0x4c]	1854898	1			T3	2		T52	4		T57	3
valid_sources[0x4d]	1382649	1			T3	2		T57	3		T58	7
valid_sources[0x4e]	1455894	1			T3	1		T52	1		T57	1
valid_sources[0x4f]	1446207	1			T52	1		T58	3		T80	1
valid_sources[0x50]	1377355	1			T3	2		T52	3		T57	4
valid_sources[0x51]	2323334	1			T3	1		T57	3		T58	8
valid_sources[0x52]	2257999	1			T52	1		T57	1		T58	1
valid_sources[0x53]	2210787	1			T57	2		T58	9		T55	3
valid_sources[0x54]	1377489	1			T57	3		T58	11		T55	1
valid_sources[0x55]	1458517	1			T52	3		T57	2		T58	5
valid_sources[0x56]	1381850	1			T57	8		T58	11		T55	2
valid_sources[0x57]	1380992	1			T97	6		T113	4		T83	2
valid_sources[0x58]	1878300	1			T52	2		T58	6		T81	7
valid_sources[0x59]	1377444	1			T52	1		T53	1		T58	11
valid_sources[0x5a]	1379409	1			T3	1		T52	2		T55	1
valid_sources[0x5b]	1383287	1			T58	3		T55	1		T61	4
valid_sources[0x5c]	1374277	1			T58	5		T55	2		T80	3
valid_sources[0x5d]	1382633	1			T57	5		T58	7		T55	1
valid_sources[0x5e]	1480038	1			T52	3		T57	4		T58	8
valid_sources[0x5f]	1849454	1			T52	1		T58	4		T81	7
valid_sources[0x60]	3773942	1			T52	1		T57	3		T55	1
valid_sources[0x61]	1391021	1			T3	1		T57	3		T58	11
valid_sources[0x62]	1371891	1			T2	31		T3	1		T57	4
valid_sources[0x63]	1390805	1			T52	1		T57	1		T58	18
valid_sources[0x64]	1374797	1			T2	53		T52	4		T57	2
valid_sources[0x65]	1374455	1			T58	1		T55	2		T90	8
valid_sources[0x66]	1375336	1			T3	3		T57	1		T58	6
valid_sources[0x67]	3097141	1			T3	1		T53	1		T90	11
valid_sources[0x68]	2850602	1			T57	1		T58	8		T91	1
valid_sources[0x69]	3139401	1			T52	2		T57	1		T58	11
valid_sources[0x6a]	1383865	1			T3	4		T57	8		T58	1
valid_sources[0x6b]	1417659	1			T57	5		T58	3		T55	1
valid_sources[0x6c]	1385860	1			T3	3		T52	2		T57	2
valid_sources[0x6d]	1401866	1			T57	4		T58	2		T55	2
valid_sources[0x6e]	1370739	1			T3	2		T52	1		T58	9
valid_sources[0x6f]	1375982	1			T52	1		T57	4		T58	2
valid_sources[0x70]	2230393	1			T52	3		T58	3		T55	1
valid_sources[0x71]	1481885	1			T57	6		T58	3		T55	1
valid_sources[0x72]	1486539	1			T3	1		T52	1		T58	5
valid_sources[0x73]	1526065	1			T57	5		T58	12		T55	1
valid_sources[0x74]	1372524	1			T2	62		T58	9		T55	1
valid_sources[0x75]	1382676	1			T57	2		T58	4		T55	1
valid_sources[0x76]	1378167	1			T57	2		T58	7		T55	1
valid_sources[0x77]	2125672	1			T57	2		T58	4		T80	1
valid_sources[0x78]	1401263	1			T52	3		T57	4		T58	12
valid_sources[0x79]	2224834	1			T58	3		T90	7		T97	2
valid_sources[0x7a]	1599906	1			T52	1		T53	1		T58	2
valid_sources[0x7b]	1675411	1			T52	1		T57	8		T58	8
valid_sources[0x7c]	1374790	1			T58	2		T55	1		T92	30
valid_sources[0x7d]	1387493	1			T57	3		T58	1		T81	1
valid_sources[0x7e]	3807207	1			T58	2		T55	2		T139	1
valid_sources[0x7f]	1580146	1			T52	1		T57	13		T58	1
valid_sources[0x80]	1377951	1			T1	76		T58	2		T80	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88468424

1

T1

61

T2

224

T3

36

values[0x0]

all_enables

biggest_size

61637540

1

T1

2

T2

140

T3

25

values[0x1]

all_enables

biggest_size

53050465

1

T1

2

T2

129

T3

30