Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262847714

1

T1

86

T2

138

T3

45

full_word

203604409

1

T1

65

T2

493

T3

91

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	466451833	1			T1	151		T2	631		T3	136
auto[TlIntgErrCmd]	112	1			T112	10		T113	3		T114	6
auto[TlIntgErrData]	84	1			T112	4		T113	3		T114	9
auto[TlIntgErrBoth]	94	1			T112	6		T113	4		T114	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242929938

1

T1

142

T2

355

T3

76

auto[1]

223522185

1

T1

9

T2

276

T3

60

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154348870	1			T1	81		T2	131		T3	40
auto[TlIntgErrNone]	partial	auto[1]	108498584	1			T1	5		T2	7		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	88580940	1			T1	61		T2	224		T3	36
auto[TlIntgErrNone]	full_word	auto[1]	115023439	1			T1	4		T2	269		T3	55
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T112	4		T113	1		T117	3
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T112	5		T113	2		T114	5
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T114	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T112	1		T155	1		T156	2
auto[TlIntgErrData]	partial	auto[0]	43	1			T112	2		T113	1		T114	5
auto[TlIntgErrData]	partial	auto[1]	32	1			T112	2		T113	2		T114	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T157	2		T158	1		T154	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T114	1		T142	1		T153	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T113	3		T114	3		T142	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T112	6		T113	1		T114	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T117	1		T142	1		T159	2
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T117	2		T155	1		T160	1