Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	115344139	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1269	1269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115344139	0	0
T52	2016	113	0	0
T53	1217	0	0	0
T54	1189	0	0	0
T55	10484	577	0	0
T56	0	239	0	0
T57	5930	0	0	0
T58	13053	0	0	0
T61	1319	0	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T82	0	77	0	0
T83	0	405	0	0
T84	0	639	0	0
T85	0	309	0	0
T86	0	208	0	0
T87	0	316	0	0
T90	2067	0	0	0
T93	0	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269	1269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	199318202	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1269	1269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	199318202	0	0
T52	2016	103	0	0
T53	1217	0	0	0
T54	1189	0	0	0
T55	10484	562	0	0
T56	0	1011	0	0
T57	5930	0	0	0
T58	13053	0	0	0
T61	1319	0	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T82	0	71	0	0
T83	0	397	0	0
T84	0	322	0	0
T85	0	299	0	0
T86	0	161	0	0
T87	0	234	0	0
T90	2067	0	0	0
T93	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269	1269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	317873986	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1269	1269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	317873986	0	0
T1	2135	269	0	0
T2	3298	1328	0	0
T3	1965	149	0	0
T52	2016	81	0	0
T53	1217	40	0	0
T54	1189	22	0	0
T55	10484	803	0	0
T57	5930	1302	0	0
T58	13053	3922	0	0
T80	1774	233	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269	1269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	567499799	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1269	1269	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	567499799	0	0
T1	2135	151	0	0
T2	3298	631	0	0
T3	1965	136	0	0
T52	2016	77	0	0
T53	1217	40	0	0
T54	1189	57	0	0
T55	10484	776	0	0
T57	5930	2893	0	0
T58	13053	7023	0	0
T80	1774	372	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2135	1793	0	0
T2	3298	3161	0	0
T3	1965	1895	0	0
T52	2016	1917	0	0
T53	1217	1158	0	0
T54	1189	1108	0	0
T55	10484	10430	0	0
T57	5930	5840	0	0
T58	13053	12647	0	0
T80	1774	1687	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1269	1269	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T52	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T80	1	1	0	0