Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.54	96.32	91.89	100.00	92.31	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1622611	0	0
entropy_period_rd_A	2147483647	2590	0	0
intr_enable_rd_A	2147483647	3279	0	0
prefix_0_rd_A	2147483647	2140	0	0
prefix_10_rd_A	2147483647	2205	0	0
prefix_1_rd_A	2147483647	2082	0	0
prefix_2_rd_A	2147483647	2036	0	0
prefix_3_rd_A	2147483647	2123	0	0
prefix_4_rd_A	2147483647	2105	0	0
prefix_5_rd_A	2147483647	2203	0	0
prefix_6_rd_A	2147483647	2120	0	0
prefix_7_rd_A	2147483647	2221	0	0
prefix_8_rd_A	2147483647	2129	0	0
prefix_9_rd_A	2147483647	2045	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1622611	0	0
T52	2016	1	0	0
T53	1217	0	0	0
T54	1189	0	0	0
T55	10484	290	0	0
T56	0	228	0	0
T57	5930	0	0	0
T58	13053	0	0	0
T61	1319	0	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T82	0	1	0	0
T83	0	335	0	0
T84	0	1	0	0
T85	0	93	0	0
T90	2067	0	0	0
T112	0	3	0	0
T113	0	2	0	0
T114	0	7	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2590	0	0
T55	10484	0	0	0
T56	13003	1	0	0
T57	5930	5	0	0
T58	13053	71	0	0
T61	1319	0	0	0
T80	1774	4	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T93	0	3	0	0
T98	0	12	0	0
T114	0	113	0	0
T118	0	2	0	0
T119	0	9	0	0
T121	0	257	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3279	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T58	13053	90	0	0
T61	1319	31	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	7	0	0
T92	1562	0	0	0
T93	1448	1	0	0
T94	0	9	0	0
T98	0	14	0	0
T114	0	214	0	0
T118	0	1	0	0
T119	0	6	0	0
T140	0	15	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2140	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	34	0	0
T58	13053	44	0	0
T61	1319	0	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T93	0	3	0	0
T98	0	2	0	0
T100	0	6	0	0
T114	0	83	0	0
T117	0	37	0	0
T118	0	2	0	0
T119	0	11	0	0
T121	0	288	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2205	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	25	0	0
T58	13053	60	0	0
T61	1319	0	0	0
T80	1774	7	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T93	0	3	0	0
T98	0	7	0	0
T114	0	87	0	0
T117	0	31	0	0
T118	0	1	0	0
T119	0	10	0	0
T121	0	267	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2082	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	16	0	0
T58	13053	42	0	0
T61	1319	0	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T93	0	2	0	0
T98	0	5	0	0
T100	0	5	0	0
T114	0	59	0	0
T117	0	25	0	0
T118	0	4	0	0
T119	0	8	0	0
T121	0	261	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2036	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	10	0	0
T58	13053	68	0	0
T61	1319	0	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T98	0	12	0	0
T114	0	87	0	0
T117	0	35	0	0
T118	0	5	0	0
T119	0	2	0	0
T121	0	205	0	0
T141	0	8	0	0
T142	0	22	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2123	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	25	0	0
T58	13053	52	0	0
T61	1319	0	0	0
T80	1774	3	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T93	0	3	0	0
T98	0	9	0	0
T114	0	93	0	0
T117	0	41	0	0
T118	0	9	0	0
T119	0	2	0	0
T121	0	277	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2105	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	3	0	0
T58	13053	67	0	0
T61	1319	0	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T93	0	1	0	0
T98	0	10	0	0
T100	0	18	0	0
T114	0	81	0	0
T117	0	43	0	0
T118	0	3	0	0
T119	0	4	0	0
T121	0	255	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2203	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	34	0	0
T58	13053	71	0	0
T61	1319	0	0	0
T80	1774	5	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T93	0	2	0	0
T98	0	10	0	0
T114	0	69	0	0
T117	0	39	0	0
T118	0	8	0	0
T119	0	13	0	0
T121	0	196	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2120	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	18	0	0
T58	13053	64	0	0
T61	1319	0	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T98	0	9	0	0
T100	0	7	0	0
T114	0	71	0	0
T117	0	25	0	0
T118	0	8	0	0
T119	0	7	0	0
T121	0	227	0	0
T141	0	2	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2221	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	4	0	0
T58	13053	63	0	0
T61	1319	0	0	0
T80	1774	1	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T93	0	6	0	0
T98	0	10	0	0
T100	0	4	0	0
T114	0	57	0	0
T117	0	49	0	0
T118	0	7	0	0
T121	0	226	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2129	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	5	0	0
T58	13053	60	0	0
T61	1319	0	0	0
T80	1774	2	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T93	0	3	0	0
T98	0	3	0	0
T114	0	91	0	0
T117	0	32	0	0
T118	0	3	0	0
T119	0	9	0	0
T121	0	262	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2045	0	0
T55	10484	0	0	0
T56	13003	0	0	0
T57	5930	18	0	0
T58	13053	50	0	0
T61	1319	0	0	0
T80	1774	0	0	0
T81	4989	0	0	0
T90	2067	0	0	0
T91	1440	0	0	0
T92	1562	0	0	0
T98	0	12	0	0
T100	0	9	0	0
T102	0	7	0	0
T114	0	74	0	0
T117	0	38	0	0
T121	0	243	0	0
T141	0	6	0	0
T142	0	15	0	0