Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	260670891	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

208106910

1

T1

467

T2

5

T3

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	246176371	1			T1	349		T2	11		T3	26
values[0x0]	106743339	1			T1	126		T2	3		T3	42
values[0x1]	115858091	1			T1	146		T2	8		T3	114

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202857449	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

265920352

1

T1

505

T2

8

T3

137

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3298999	1			T51	8		T82	8		T83	7
valid_sources[0x01]	1405276	1			T51	12		T82	1		T83	4
valid_sources[0x02]	1410732	1			T1	10		T51	16		T82	1
valid_sources[0x03]	2290230	1			T51	8		T83	3		T85	12
valid_sources[0x04]	1428512	1			T1	9		T81	11		T51	9
valid_sources[0x05]	1421854	1			T1	2		T51	6		T83	1
valid_sources[0x06]	1527278	1			T1	1		T51	4		T83	3
valid_sources[0x07]	2571485	1			T51	13		T83	1		T85	15
valid_sources[0x08]	1413869	1			T51	9		T82	6		T83	2
valid_sources[0x09]	1548240	1			T3	4		T51	7		T82	2
valid_sources[0x0a]	3838113	1			T1	5		T51	12		T82	1
valid_sources[0x0b]	1400259	1			T1	12		T51	18		T83	4
valid_sources[0x0c]	3872859	1			T51	13		T83	1		T85	18
valid_sources[0x0d]	3429882	1			T2	1		T51	5		T83	6
valid_sources[0x0e]	6189899	1			T51	9		T82	3		T83	4
valid_sources[0x0f]	2290174	1			T1	5		T51	2		T82	3
valid_sources[0x10]	1402484	1			T3	2		T81	5		T51	13
valid_sources[0x11]	1403056	1			T3	11		T81	9		T51	9
valid_sources[0x12]	1403796	1			T51	6		T82	5		T83	4
valid_sources[0x13]	1483536	1			T55	1		T51	9		T82	2
valid_sources[0x14]	1398209	1			T51	14		T82	6		T83	4
valid_sources[0x15]	1444293	1			T2	1		T81	1		T51	12
valid_sources[0x16]	1412107	1			T1	1		T2	1		T51	5
valid_sources[0x17]	1578809	1			T1	1		T51	1		T83	2
valid_sources[0x18]	1523482	1			T51	10		T82	4		T83	4
valid_sources[0x19]	2314850	1			T51	7		T82	3		T83	2
valid_sources[0x1a]	1416811	1			T51	18		T82	5		T83	2
valid_sources[0x1b]	1940886	1			T51	18		T82	1		T83	6
valid_sources[0x1c]	2951671	1			T1	6		T2	1		T3	7
valid_sources[0x1d]	2309752	1			T81	5		T51	8		T82	3
valid_sources[0x1e]	4313900	1			T2	1		T51	9		T82	1
valid_sources[0x1f]	1518554	1			T51	24		T82	1		T83	2
valid_sources[0x20]	3826628	1			T81	4		T51	5		T82	1
valid_sources[0x21]	1414523	1			T51	4		T82	2		T83	3
valid_sources[0x22]	1404339	1			T1	4		T51	2		T82	2
valid_sources[0x23]	1408591	1			T1	7		T51	17		T82	4
valid_sources[0x24]	1975388	1			T51	3		T82	2		T83	2
valid_sources[0x25]	2314224	1			T1	12		T2	1		T51	7
valid_sources[0x26]	1400111	1			T51	9		T83	3		T85	8
valid_sources[0x27]	1425974	1			T51	19		T83	6		T85	19
valid_sources[0x28]	1413045	1			T1	9		T51	2		T83	4
valid_sources[0x29]	2464388	1			T1	7		T52	70		T55	1
valid_sources[0x2a]	1906028	1			T51	13		T82	3		T83	5
valid_sources[0x2b]	1416357	1			T3	15		T51	5		T83	4
valid_sources[0x2c]	1417036	1			T51	13		T82	3		T85	20
valid_sources[0x2d]	1420660	1			T3	10		T51	5		T82	4
valid_sources[0x2e]	1550986	1			T51	32		T82	6		T83	2
valid_sources[0x2f]	1404539	1			T50	56		T51	9		T83	6
valid_sources[0x30]	1407449	1			T51	4		T82	1		T83	6
valid_sources[0x31]	2382875	1			T1	4		T51	7		T82	2
valid_sources[0x32]	1406971	1			T82	5		T83	3		T85	18
valid_sources[0x33]	1410168	1			T51	7		T82	1		T83	2
valid_sources[0x34]	1404093	1			T1	1		T2	1		T51	8
valid_sources[0x35]	1415542	1			T2	2		T3	2		T51	12
valid_sources[0x36]	1404138	1			T1	3		T55	1		T51	13
valid_sources[0x37]	1423846	1			T51	13		T82	1		T85	10
valid_sources[0x38]	1485034	1			T82	1		T83	2		T85	14
valid_sources[0x39]	1548280	1			T1	9		T51	20		T82	1
valid_sources[0x3a]	1408444	1			T51	12		T82	2		T83	2
valid_sources[0x3b]	1405564	1			T1	11		T51	13		T82	2
valid_sources[0x3c]	1481238	1			T2	1		T52	31		T51	10
valid_sources[0x3d]	1421973	1			T51	14		T82	1		T83	1
valid_sources[0x3e]	1405633	1			T55	1		T51	15		T82	5
valid_sources[0x3f]	1409443	1			T51	21		T82	5		T83	5
valid_sources[0x40]	1406920	1			T1	2		T51	12		T82	9
valid_sources[0x41]	1397987	1			T51	13		T83	2		T85	8
valid_sources[0x42]	1435777	1			T51	5		T82	1		T85	12
valid_sources[0x43]	1403343	1			T3	2		T51	12		T83	1
valid_sources[0x44]	1394283	1			T51	8		T82	1		T83	1
valid_sources[0x45]	2312575	1			T51	15		T82	1		T85	19
valid_sources[0x46]	2335352	1			T1	4		T81	2		T51	9
valid_sources[0x47]	2518811	1			T51	13		T82	3		T83	2
valid_sources[0x48]	1456325	1			T51	3		T82	5		T83	1
valid_sources[0x49]	1439868	1			T1	6		T51	10		T82	3
valid_sources[0x4a]	1405624	1			T3	1		T51	12		T82	3
valid_sources[0x4b]	2263526	1			T51	6		T83	1		T85	11
valid_sources[0x4c]	3003894	1			T1	9		T51	18		T82	4
valid_sources[0x4d]	1408018	1			T81	4		T51	3		T82	7
valid_sources[0x4e]	1399004	1			T51	17		T82	2		T83	2
valid_sources[0x4f]	1417653	1			T3	3		T51	9		T83	1
valid_sources[0x50]	3452524	1			T1	1		T51	16		T82	1
valid_sources[0x51]	2327807	1			T51	6		T82	1		T83	1
valid_sources[0x52]	1397331	1			T81	1		T51	17		T83	2
valid_sources[0x53]	1408143	1			T1	4		T51	5		T83	2
valid_sources[0x54]	4434058	1			T51	17		T82	2		T83	2
valid_sources[0x55]	4239684	1			T1	11		T51	8		T82	1
valid_sources[0x56]	1476210	1			T3	1		T51	17		T82	2
valid_sources[0x57]	1870377	1			T1	8		T51	4		T83	3
valid_sources[0x58]	1397538	1			T51	6		T82	1		T83	1
valid_sources[0x59]	1398825	1			T1	2		T51	4		T82	2
valid_sources[0x5a]	1475575	1			T1	2		T52	104		T51	10
valid_sources[0x5b]	1416566	1			T1	18		T51	6		T82	1
valid_sources[0x5c]	3257611	1			T2	2		T51	7		T83	2
valid_sources[0x5d]	1405919	1			T51	12		T83	4		T85	13
valid_sources[0x5e]	1407068	1			T1	6		T51	9		T82	1
valid_sources[0x5f]	1404801	1			T2	1		T51	5		T83	1
valid_sources[0x60]	4464163	1			T51	19		T83	2		T85	11
valid_sources[0x61]	1415292	1			T51	9		T83	1		T85	13
valid_sources[0x62]	1419866	1			T51	8		T83	1		T85	18
valid_sources[0x63]	4325733	1			T51	5		T82	1		T83	1
valid_sources[0x64]	1414226	1			T1	5		T81	4		T51	17
valid_sources[0x65]	1581858	1			T51	4		T82	7		T83	1
valid_sources[0x66]	3438037	1			T51	18		T82	2		T83	1
valid_sources[0x67]	2275352	1			T51	13		T82	2		T83	7
valid_sources[0x68]	1412201	1			T1	2		T51	22		T83	3
valid_sources[0x69]	1449577	1			T2	1		T51	11		T82	4
valid_sources[0x6a]	1414504	1			T1	9		T81	2		T51	12
valid_sources[0x6b]	1451398	1			T1	10		T51	7		T82	3
valid_sources[0x6c]	3853724	1			T81	3		T51	13		T82	2
valid_sources[0x6d]	1407912	1			T3	1		T50	56		T81	1
valid_sources[0x6e]	2334919	1			T1	12		T51	11		T83	1
valid_sources[0x6f]	1415217	1			T3	5		T51	9		T83	3
valid_sources[0x70]	1884803	1			T51	12		T83	1		T85	11
valid_sources[0x71]	1410956	1			T1	7		T51	6		T82	6
valid_sources[0x72]	1404520	1			T1	1		T55	1		T51	9
valid_sources[0x73]	1424141	1			T51	1		T82	2		T83	1
valid_sources[0x74]	1404271	1			T3	1		T52	18		T51	13
valid_sources[0x75]	3861707	1			T51	23		T82	2		T83	3
valid_sources[0x76]	2268897	1			T51	9		T83	4		T85	17
valid_sources[0x77]	2111970	1			T51	22		T85	11		T110	11
valid_sources[0x78]	1406660	1			T51	23		T82	3		T85	14
valid_sources[0x79]	1403956	1			T1	2		T3	2		T51	11
valid_sources[0x7a]	1418019	1			T51	8		T82	2		T83	1
valid_sources[0x7b]	1412149	1			T3	14		T51	6		T83	2
valid_sources[0x7c]	1499425	1			T2	1		T55	1		T51	17
valid_sources[0x7d]	2452677	1			T51	3		T83	2		T85	21
valid_sources[0x7e]	1923415	1			T55	2		T51	23		T82	3
valid_sources[0x7f]	1405078	1			T1	1		T3	1		T51	15
valid_sources[0x80]	1433853	1			T51	1		T82	6		T83	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

90146420

1

T1

207

T2

3

T3

14

values[0x0]

all_enables

biggest_size

63352287

1

T1

121

T2

1

T3

32

values[0x1]

all_enables

biggest_size

54608203

1

T1

139

T2

1

T3

29