Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

269655270

1

T1

154

T2

17

T3

1028

full_word

208664030

1

T1

467

T2

5

T3

122

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	478318970	1			T1	621		T2	22		T3	1150
auto[TlIntgErrCmd]	109	1			T51	6		T110	10		T111	6
auto[TlIntgErrData]	115	1			T51	6		T110	4		T111	6
auto[TlIntgErrBoth]	106	1			T51	8		T110	6		T111	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

247886669

1

T1

349

T2

11

T3

139

auto[1]

230432631

1

T1

272

T2

11

T3

1011

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	157601042	1			T1	142		T2	8		T3	118
auto[TlIntgErrNone]	partial	auto[1]	112053923	1			T1	12		T2	9		T3	910
auto[TlIntgErrNone]	full_word	auto[0]	90285486	1			T1	207		T2	3		T3	21
auto[TlIntgErrNone]	full_word	auto[1]	118378519	1			T1	260		T2	2		T3	101
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T51	2		T110	4		T111	1
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T51	3		T110	6		T111	5
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T51	1		T113	1		T142	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T51	4		T110	3		T111	3
auto[TlIntgErrData]	partial	auto[1]	56	1			T51	1		T110	1		T111	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T142	1		T143	1		T144	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T51	1		T113	1		T145	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T51	5		T110	4		T111	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T51	3		T110	2		T111	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T112	1		T142	3		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T114	1		T146	1		T147	1