Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	119871687	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119871687	0	0
T3	3300	198	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	0	0	0
T53	0	29	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T84	0	235	0	0
T85	28028	0	0	0
T86	0	295	0	0
T87	0	115	0	0
T89	1269	0	0	0
T90	0	437	0	0
T91	0	133	0	0
T92	0	143	0	0
T93	0	68	0	0
T94	0	219	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T55	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	225462511	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	225462511	0	0
T3	3300	163	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	0	0	0
T53	0	28	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T84	0	191	0	0
T85	28028	0	0	0
T86	0	172	0	0
T87	0	115	0	0
T89	1269	0	0	0
T90	0	219	0	0
T91	0	277	0	0
T92	0	133	0	0
T93	0	61	0	0
T94	0	206	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T55	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	326096468	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	326096468	0	0
T1	2604	1357	0	0
T2	1027	22	0	0
T3	3300	855	0	0
T50	5390	700	0	0
T51	14011	5265	0	0
T52	3248	539	0	0
T55	711	22	0	0
T81	1745	251	0	0
T82	2348	1236	0	0
T83	3184	1294	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T55	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	635319198	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	635319198	0	0
T1	2604	621	0	0
T2	1027	98	0	0
T3	3300	577	0	0
T50	5390	645	0	0
T51	14011	2711	0	0
T52	3248	1170	0	0
T55	711	22	0	0
T81	1745	132	0	0
T82	2348	633	0	0
T83	3184	629	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2604	2499	0	0
T2	1027	934	0	0
T3	3300	3241	0	0
T50	5390	5237	0	0
T51	14011	12444	0	0
T52	3248	3177	0	0
T55	711	655	0	0
T81	1745	1656	0	0
T82	2348	2211	0	0
T83	3184	3016	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T52	1	1	0	0
T55	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0