Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	2036337	0	0
entropy_period_rd_A	2147483647	3244	0	0
intr_enable_rd_A	2147483647	3690	0	0
prefix_0_rd_A	2147483647	3107	0	0
prefix_10_rd_A	2147483647	2918	0	0
prefix_1_rd_A	2147483647	3281	0	0
prefix_2_rd_A	2147483647	2977	0	0
prefix_3_rd_A	2147483647	3187	0	0
prefix_4_rd_A	2147483647	2946	0	0
prefix_5_rd_A	2147483647	2942	0	0
prefix_6_rd_A	2147483647	2884	0	0
prefix_7_rd_A	2147483647	3247	0	0
prefix_8_rd_A	2147483647	3015	0	0
prefix_9_rd_A	2147483647	3168	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2036337	0	0
T3	3300	142	0	0
T50	5390	0	0	0
T51	14011	2	0	0
T52	3248	0	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T84	0	60	0	0
T85	28028	0	0	0
T86	0	2	0	0
T87	0	70	0	0
T89	1269	0	0	0
T91	0	1	0	0
T110	0	2	0	0
T111	0	6	0	0
T112	0	1	0	0
T113	0	4	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3244	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	20	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	249	0	0
T89	1269	0	0	0
T91	0	2	0	0
T98	15979	0	0	0
T99	0	4	0	0
T101	0	58	0	0
T110	0	115	0	0
T126	0	45	0	0
T127	0	15	0	0
T128	0	22	0	0
T129	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3690	0	0
T2	1027	4	0	0
T3	3300	0	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	8	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	245	0	0
T89	0	1	0	0
T91	0	5	0	0
T99	0	14	0	0
T110	0	186	0	0
T126	0	40	0	0
T127	0	26	0	0
T130	0	33	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3107	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	11	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	240	0	0
T89	1269	0	0	0
T91	0	3	0	0
T98	15979	0	0	0
T99	0	15	0	0
T101	0	24	0	0
T110	0	85	0	0
T126	0	6	0	0
T127	0	28	0	0
T128	0	34	0	0
T131	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2918	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	7	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	243	0	0
T89	1269	0	0	0
T98	15979	0	0	0
T99	0	2	0	0
T101	0	25	0	0
T110	0	60	0	0
T126	0	39	0	0
T127	0	17	0	0
T128	0	55	0	0
T129	0	4	0	0
T131	0	8	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3281	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	8	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	251	0	0
T89	1269	0	0	0
T91	0	2	0	0
T98	15979	0	0	0
T99	0	6	0	0
T101	0	22	0	0
T110	0	69	0	0
T126	0	8	0	0
T127	0	6	0	0
T128	0	78	0	0
T129	0	11	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2977	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	3	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	234	0	0
T89	1269	0	0	0
T98	15979	0	0	0
T99	0	8	0	0
T101	0	21	0	0
T110	0	84	0	0
T126	0	2	0	0
T127	0	26	0	0
T128	0	53	0	0
T129	0	14	0	0
T131	0	7	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3187	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	5	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	230	0	0
T89	1269	0	0	0
T91	0	6	0	0
T98	15979	0	0	0
T101	0	24	0	0
T110	0	60	0	0
T126	0	68	0	0
T127	0	8	0	0
T128	0	92	0	0
T129	0	16	0	0
T131	0	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2946	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	14	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	211	0	0
T89	1269	0	0	0
T98	15979	0	0	0
T99	0	17	0	0
T101	0	20	0	0
T110	0	71	0	0
T126	0	34	0	0
T127	0	24	0	0
T128	0	55	0	0
T129	0	15	0	0
T131	0	1	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2942	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	5	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	253	0	0
T89	1269	0	0	0
T91	0	4	0	0
T98	15979	0	0	0
T99	0	18	0	0
T101	0	22	0	0
T110	0	64	0	0
T126	0	19	0	0
T127	0	11	0	0
T128	0	34	0	0
T131	0	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2884	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	11	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	229	0	0
T89	1269	0	0	0
T91	0	7	0	0
T98	15979	0	0	0
T99	0	12	0	0
T101	0	34	0	0
T110	0	82	0	0
T126	0	20	0	0
T127	0	18	0	0
T128	0	36	0	0
T129	0	13	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3247	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	3	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	229	0	0
T89	1269	0	0	0
T91	0	2	0	0
T98	15979	0	0	0
T99	0	9	0	0
T101	0	30	0	0
T110	0	87	0	0
T126	0	57	0	0
T127	0	13	0	0
T128	0	70	0	0
T131	0	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3015	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	13	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	248	0	0
T89	1269	0	0	0
T91	0	1	0	0
T98	15979	0	0	0
T99	0	1	0	0
T101	0	20	0	0
T110	0	70	0	0
T126	0	19	0	0
T127	0	54	0	0
T128	0	56	0	0
T131	0	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3168	0	0
T50	5390	0	0	0
T51	14011	0	0	0
T52	3248	10	0	0
T55	711	0	0	0
T81	1745	0	0	0
T82	2348	0	0	0
T83	3184	0	0	0
T85	28028	218	0	0
T89	1269	0	0	0
T91	0	8	0	0
T98	15979	0	0	0
T99	0	1	0	0
T101	0	14	0	0
T110	0	105	0	0
T126	0	55	0	0
T127	0	10	0	0
T128	0	43	0	0
T131	0	2	0	0