Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	256401867	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

205055388

1

T1

16

T2

72

T55

67

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	243004628	1			T1	20		T2	168		T3	14
values[0x0]	104850043	1			T1	9		T2	7		T3	2
values[0x1]	113602584	1			T1	11		T2	13		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	199695533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

261761722

1

T1

19

T2

109

T3

34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1309793	1			T56	36		T87	19		T88	2
valid_sources[0x01]	1311971	1			T87	6		T97	4		T104	6
valid_sources[0x02]	1309327	1			T3	1		T87	17		T88	4
valid_sources[0x03]	1771791	1			T55	1		T87	8		T97	10
valid_sources[0x04]	1323477	1			T2	1		T57	3		T87	19
valid_sources[0x05]	1317541	1			T3	1		T55	2		T56	43
valid_sources[0x06]	1307601	1			T55	1		T56	65		T87	16
valid_sources[0x07]	1311401	1			T57	2		T87	24		T97	7
valid_sources[0x08]	1392176	1			T2	1		T55	1		T56	34
valid_sources[0x09]	1316243	1			T2	2		T3	2		T87	12
valid_sources[0x0a]	1312823	1			T3	1		T55	1		T87	7
valid_sources[0x0b]	1315307	1			T55	1		T57	20		T87	12
valid_sources[0x0c]	1318567	1			T2	2		T56	106		T87	17
valid_sources[0x0d]	1344589	1			T2	2		T55	1		T87	8
valid_sources[0x0e]	3750451	1			T2	2		T56	21		T87	5
valid_sources[0x0f]	1307093	1			T2	1		T57	2		T60	17
valid_sources[0x10]	1315047	1			T57	3		T87	20		T97	4
valid_sources[0x11]	1312391	1			T56	15		T87	21		T97	7
valid_sources[0x12]	2699502	1			T2	1		T55	2		T57	9
valid_sources[0x13]	3727345	1			T57	3		T87	10		T97	4
valid_sources[0x14]	1308430	1			T87	14		T58	1		T104	4
valid_sources[0x15]	1312115	1			T55	1		T87	15		T97	4
valid_sources[0x16]	2166381	1			T2	2		T87	9		T58	1
valid_sources[0x17]	2189180	1			T2	1		T55	1		T87	4
valid_sources[0x18]	1308668	1			T2	1		T56	24		T87	6
valid_sources[0x19]	1315069	1			T2	2		T3	1		T55	1
valid_sources[0x1a]	1309782	1			T55	1		T56	41		T87	10
valid_sources[0x1b]	1405796	1			T2	3		T57	2		T87	22
valid_sources[0x1c]	1306056	1			T2	2		T87	15		T63	4
valid_sources[0x1d]	1316568	1			T87	16		T88	1		T97	4
valid_sources[0x1e]	1351964	1			T87	6		T88	2		T97	8
valid_sources[0x1f]	1312611	1			T2	1		T55	2		T57	4
valid_sources[0x20]	1425073	1			T2	1		T3	1		T55	1
valid_sources[0x21]	1310129	1			T55	2		T57	10		T87	14
valid_sources[0x22]	1310738	1			T3	1		T55	1		T57	9
valid_sources[0x23]	1310305	1			T2	2		T3	1		T87	22
valid_sources[0x24]	1355785	1			T87	18		T88	2		T97	7
valid_sources[0x25]	1319112	1			T56	31		T87	10		T97	3
valid_sources[0x26]	1314291	1			T57	3		T87	3		T88	4
valid_sources[0x27]	1312036	1			T2	1		T55	1		T87	17
valid_sources[0x28]	1317131	1			T2	1		T56	264		T57	9
valid_sources[0x29]	1558008	1			T3	1		T57	7		T87	15
valid_sources[0x2a]	3494602	1			T3	1		T55	1		T87	26
valid_sources[0x2b]	1506476	1			T87	10		T88	16		T104	3
valid_sources[0x2c]	1339786	1			T87	26		T88	4		T97	7
valid_sources[0x2d]	2914054	1			T2	1		T57	14		T87	24
valid_sources[0x2e]	3787165	1			T2	1		T57	5		T87	8
valid_sources[0x2f]	1313479	1			T59	26		T57	4		T87	12
valid_sources[0x30]	1313705	1			T2	1		T55	1		T56	30
valid_sources[0x31]	2410124	1			T2	2		T55	1		T56	71
valid_sources[0x32]	2186406	1			T87	12		T88	1		T97	7
valid_sources[0x33]	1306508	1			T2	1		T3	1		T59	31
valid_sources[0x34]	1339017	1			T55	1		T57	12		T87	10
valid_sources[0x35]	3732142	1			T2	1		T55	2		T56	39
valid_sources[0x36]	1310776	1			T55	1		T57	15		T87	13
valid_sources[0x37]	1463662	1			T2	3		T55	1		T56	1
valid_sources[0x38]	4527734	1			T55	1		T56	9		T87	7
valid_sources[0x39]	2223498	1			T2	1		T55	3		T87	14
valid_sources[0x3a]	1969054	1			T2	2		T3	1		T57	23
valid_sources[0x3b]	1316321	1			T55	1		T87	7		T88	6
valid_sources[0x3c]	1804089	1			T3	1		T87	16		T88	2
valid_sources[0x3d]	1317559	1			T2	1		T3	1		T55	1
valid_sources[0x3e]	1311496	1			T2	2		T55	2		T87	11
valid_sources[0x3f]	4265588	1			T55	1		T87	22		T97	1
valid_sources[0x40]	1317656	1			T2	1		T3	1		T57	31
valid_sources[0x41]	1315357	1			T2	1		T87	13		T88	2
valid_sources[0x42]	1351045	1			T2	1		T57	4		T87	9
valid_sources[0x43]	1336178	1			T2	1		T3	1		T56	4
valid_sources[0x44]	1434592	1			T87	11		T97	2		T104	11
valid_sources[0x45]	2242605	1			T2	1		T87	6		T88	3
valid_sources[0x46]	3404760	1			T57	13		T87	21		T97	15
valid_sources[0x47]	1315597	1			T87	9		T88	9		T97	18
valid_sources[0x48]	1322774	1			T2	1		T87	6		T97	2
valid_sources[0x49]	1437469	1			T2	1		T55	1		T87	17
valid_sources[0x4a]	5841528	1			T57	3		T87	15		T88	3
valid_sources[0x4b]	2240831	1			T55	2		T56	20		T57	2
valid_sources[0x4c]	2334409	1			T2	1		T87	14		T88	4
valid_sources[0x4d]	1311463	1			T2	1		T55	2		T87	8
valid_sources[0x4e]	3363428	1			T87	18		T88	3		T97	1
valid_sources[0x4f]	1401320	1			T55	1		T87	13		T88	1
valid_sources[0x50]	1375256	1			T55	1		T56	30		T87	10
valid_sources[0x51]	3372697	1			T55	1		T57	3		T87	9
valid_sources[0x52]	3873024	1			T57	7		T87	15		T88	4
valid_sources[0x53]	3376356	1			T2	1		T87	14		T88	4
valid_sources[0x54]	1314023	1			T2	2		T55	1		T87	8
valid_sources[0x55]	1313747	1			T87	13		T88	1		T97	3
valid_sources[0x56]	1311535	1			T2	1		T55	2		T56	5
valid_sources[0x57]	1318968	1			T2	2		T55	4		T87	18
valid_sources[0x58]	1344284	1			T2	1		T56	93		T57	2
valid_sources[0x59]	1776085	1			T56	102		T57	11		T87	23
valid_sources[0x5a]	1435762	1			T2	1		T55	2		T56	58
valid_sources[0x5b]	1313079	1			T57	2		T87	10		T97	7
valid_sources[0x5c]	1702273	1			T2	1		T87	14		T88	7
valid_sources[0x5d]	1448491	1			T3	1		T57	1		T87	8
valid_sources[0x5e]	1445043	1			T2	2		T55	1		T87	21
valid_sources[0x5f]	2742139	1			T2	2		T87	20		T88	4
valid_sources[0x60]	1310706	1			T2	1		T87	7		T88	5
valid_sources[0x61]	1309013	1			T2	1		T57	5		T87	17
valid_sources[0x62]	1316108	1			T2	3		T87	12		T97	3
valid_sources[0x63]	4725602	1			T2	3		T3	1		T87	12
valid_sources[0x64]	3682319	1			T2	1		T3	1		T87	14
valid_sources[0x65]	1317533	1			T3	1		T87	20		T97	5
valid_sources[0x66]	3488148	1			T87	9		T88	2		T97	5
valid_sources[0x67]	2188735	1			T3	1		T57	1		T87	8
valid_sources[0x68]	1305964	1			T2	2		T55	1		T57	9
valid_sources[0x69]	1359769	1			T2	1		T56	9		T57	10
valid_sources[0x6a]	1308975	1			T55	1		T57	5		T87	19
valid_sources[0x6b]	1304121	1			T2	2		T3	2		T55	1
valid_sources[0x6c]	1308714	1			T57	10		T87	15		T88	3
valid_sources[0x6d]	3704413	1			T2	2		T3	1		T59	8
valid_sources[0x6e]	1306561	1			T87	11		T88	3		T97	7
valid_sources[0x6f]	1310573	1			T2	1		T55	2		T56	224
valid_sources[0x70]	2178769	1			T87	16		T88	1		T97	5
valid_sources[0x71]	1772497	1			T2	1		T57	11		T87	21
valid_sources[0x72]	1321330	1			T2	2		T57	3		T87	6
valid_sources[0x73]	1758450	1			T55	1		T56	157		T87	14
valid_sources[0x74]	1309604	1			T55	3		T57	4		T87	11
valid_sources[0x75]	1330413	1			T2	3		T55	2		T56	21
valid_sources[0x76]	1467274	1			T2	2		T55	1		T57	3
valid_sources[0x77]	1313143	1			T57	10		T87	13		T88	6
valid_sources[0x78]	1311980	1			T3	1		T56	15		T87	15
valid_sources[0x79]	3400582	1			T2	1		T87	7		T88	2
valid_sources[0x7a]	3379570	1			T2	2		T57	3		T87	12
valid_sources[0x7b]	1319731	1			T57	5		T87	20		T58	1
valid_sources[0x7c]	1310800	1			T1	40		T2	1		T55	2
valid_sources[0x7d]	1317854	1			T55	3		T87	13		T88	2
valid_sources[0x7e]	1317533	1			T55	1		T56	30		T57	3
valid_sources[0x7f]	1307844	1			T55	1		T57	3		T87	14
valid_sources[0x80]	3758369	1			T57	14		T87	10		T97	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89344741

1

T1

8

T2

65

T55

58

values[0x0]

all_enables

biggest_size

62168802

1

T1

5

T2

3

T55

4

values[0x1]

all_enables

biggest_size

53541845

1

T1

3

T2

4

T55

5