Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

262704718

1

T1

24

T2

116

T3

626

full_word

205447670

1

T1

16

T2

72

T3

23

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	468152098	1			T1	40		T2	188		T3	649
auto[TlIntgErrCmd]	91	1			T56	7		T119	3		T120	4
auto[TlIntgErrData]	88	1			T56	7		T118	6		T119	3
auto[TlIntgErrBoth]	111	1			T56	6		T118	4		T119	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244207885

1

T1

20

T2

168

T3

152

auto[1]

223944503

1

T1

20

T2

20

T3

497

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	154765284	1			T1	12		T2	103		T3	146
auto[TlIntgErrNone]	partial	auto[1]	107939166	1			T1	12		T2	13		T3	480
auto[TlIntgErrNone]	full_word	auto[0]	89442458	1			T1	8		T2	65		T3	6
auto[TlIntgErrNone]	full_word	auto[1]	116005190	1			T1	8		T2	7		T3	17
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T56	3		T119	2		T120	3
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T56	4		T119	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T156	1		T158	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T157	1		T134	1		T159	1
auto[TlIntgErrData]	partial	auto[0]	38	1			T56	1		T118	3		T119	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T56	3		T118	3		T119	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T56	1		T158	2		T160	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T56	2		T157	2		T160	1
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T56	4		T118	3		T119	2
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T56	1		T118	1		T119	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T156	1		T161	1		T158	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T56	1		-	-		-	-