Unified Coverage Report :: Module :: prim_packer

Module : prim_packer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_msgfifo.u_packer	97.50	100.00	100.00			90.00	100.00

---

Module Instance : tb.dut.u_msgfifo.u_packer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.50	100.00	100.00			90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00			100.00	91.67	100.00	u_msgfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
ALWAYS	65	3	3	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	78	6	6	100.00
ALWAYS	90	5	5	100.00
ALWAYS	156	4	4	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	165	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	179	1	1	100.00
ALWAYS	184	9	9	100.00
ALWAYS	213	8	8	100.00
ALWAYS	234	3	3	100.00
ALWAYS	242	14	14	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	282	1	1	100.00
CONT_ASSIGN	290	0	0
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	298	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
66	1	1
67	1	1
72	1	1
78	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
90	1	1
91	1	1
92	1	1
93	1	1
95	1	1
156	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
164	1	1
165	1	1
169	1	1
170	1	1
173	1	1
174	1	1
177	1	1
179	1	1
184	1	1
186	1	1
187	1	1
191	1	1
192	1	1
196	1	1
197	1	1
201	1	1
202	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
234	1	1
235	1	1
237	1	1
242	1	1
244	1	1
245	1	1
247	1	1
249	1	1
250	1	1
252	1	1
257	1	1
258	1	1
260	1	1
261	1	1
263	1	1
265	1	1
266	1	1
278	1	1
282	1	1
290		unreachable
293	1	1
294	1	1
295	1	1
298		unreachable

---

Cond Coverage for Module : prim_packer

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       82
 EXPRESSION ((int'(pos_q) <= OutW) ? '0 : ((pos_q - 8'(OutW))))
             ----------1----------

-1-	Status	Tests
0	Unreachable	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       84
 EXPRESSION ((int'(pos_with_input) <= OutW) ? '0 : ((pos_with_input - 8'(OutW))))
             ---------------1--------------

-1-	Status	Tests
0	Unreachable	T4,T14,T18
1	Covered	T18,T116,T39

 LINE       158
 EXPRESSION (mask_i[i] == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       164
 EXPRESSION (valid_i & ready_o)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable	T4,T18,T31
1	1	Covered	T4,T5,T6

 LINE       165
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T18,T34,T51
1	1	Covered	T4,T5,T6

 LINE       169
 EXPRESSION (valid_i ? ((data_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       170
 EXPRESSION (valid_i ? ((mask_i >> lod_idx)) : '0)
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       257
 EXPRESSION (pos_q == '0)
            ------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       282
 EXPRESSION ((int'(pos_q) >= OutW) ? 1'b1 : flush_valid)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Unreachable	T4,T5,T6

---

Branch Coverage for Module : prim_packer

	Line No.	Total	Covered	Percent
Branches		30	27	90.00
TERNARY	169	2	2	100.00
TERNARY	170	2	2	100.00
TERNARY	282	1	1	100.00
IF	158	2	2	100.00
CASE	184	5	4	80.00
IF	213	3	3	100.00
IF	234	2	2	100.00
CASE	247	5	4	80.00
CASE	80	5	4	80.00
IF	90	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	169	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	170	(valid_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	282	((int'(pos_q) >= OutW)) ? 

Branches:

-1-	Status	Tests
1	Unreachable	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	158	if ((mask_i[i] == 1'b1))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	184	case ({ack_in, ack_out})

Branches:

-1-	Status	Tests
2'b00	Covered	T4,T5,T6
2'b01	Covered	T4,T5,T6
2'b10	Covered	T4,T5,T6
2'b11	Covered	T4,T14,T18
default	Not Covered

	LineNo.	Expression
-1-:	213	if ((!rst_ni))
-2-:	216	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	234	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	247	case (flush_st)
-2-:	249	if (flush_i)
-3-:	257	if ((pos_q == '0))

Branches:

-1-	-2-	-3-	Status	Tests
FlushIdle	1	-	Covered	T4,T5,T6
FlushIdle	0	-	Covered	T4,T5,T6
FlushSend	-	1	Covered	T4,T5,T6
FlushSend	-	0	Covered	T4,T5,T6
default	-	-	Not Covered

	LineNo.	Expression
-1-:	80	case ({ack_in, ack_out})
-2-:	82	((int'(pos_q) <= OutW)) ? 
-3-:	84	((int'(pos_with_input) <= OutW)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
2'b00	-	-	Covered	T4,T5,T6
2'b01	1	-	Covered	T4,T5,T6
2'b01	0	-	Unreachable	T4,T5,T6
2'b10	-	-	Covered	T4,T5,T6
2'b11	-	1	Covered	T18,T116,T39
2'b11	-	0	Unreachable	T4,T14,T18
default	-	-	Not Covered

	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (flush_done)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_packer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	28	28	100.00	28	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	28	28	100.00	28	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataIStable_M	2147483647	150235	0	1048
DataOStableWhenPending_A	2147483647	129251	0	1048
ExFlushValid_M	2147483647	352908	0	0
ExcessiveDataStored_A	2147483647	67327	0	0
ExcessiveMaskStored_A	2147483647	67327	0	0
FlushFollowedByDone_A	2147483647	352908	0	1048
ValidIDeassertedOnFlush_M	2147483647	559533	0	0
ValidOAssertedForStoredDataGTEOutW_A	2147483647	48498842	0	0
ValidOPairedWidthReadyI_A	2147483647	129251	0	0
g_byte_assert.InputDividedBy8_A	1048	1048	0	0
g_byte_assert.OutputDividedBy8_A	1048	1048	0	0
g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A	2147483647	110669935	0	0
g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A	2147483647	110669935	0	0
g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A	2147483647	110669935	0	0
g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A	2147483647	110669935	0	0
g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A	2147483647	110669935	0	0
g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A	2147483647	110669935	0	0
g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A	2147483647	110669935	0	0
g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A	2147483647	110669935	0	0
g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A	2147483647	48703057	0	0
g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A	2147483647	48703057	0	0
g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A	2147483647	48703057	0	0
g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A	2147483647	48703057	0	0
g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A	2147483647	48703057	0	0
g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A	2147483647	48703057	0	0
g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A	2147483647	48703057	0	0
g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A	2147483647	48703057	0	0
gen_mask_assert.ContiguousOnesMask_M	2147483647	110669935	0	0

DataIStable_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	150235	0	1048
T18	575732	4212	0	1
T19	25209	0	0	1
T27	0	2	0	0
T28	0	4	0	0
T31	979054	10	0	1
T32	0	3	0	0
T34	0	745	0	0
T38	0	1	0	0
T44	254389	0	0	1
T45	1178	0	0	1
T46	125404	0	0	1
T47	213511	0	0	1
T48	749148	0	0	1
T49	6549	0	0	1
T50	230685	0	0	1
T51	0	954	0	0
T74	0	11	0	0
T116	0	455	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	129251	0	1048
T8	0	76	0	0
T18	575732	3933	0	1
T19	25209	0	0	1
T29	0	64	0	0
T30	0	193	0	0
T31	979054	0	0	1
T34	0	771	0	0
T39	0	97	0	0
T40	0	76	0	0
T44	254389	0	0	1
T45	1178	0	0	1
T46	125404	0	0	1
T47	213511	0	0	1
T48	749148	0	0	1
T49	6549	0	0	1
T50	230685	0	0	1
T51	0	1006	0	0
T116	0	71	0	0
T117	0	115	0	0

ExFlushValid_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352908	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

ExcessiveDataStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67327	0	0
T14	225816	4	0	0
T15	471188	0	0	0
T16	323942	0	0	0
T17	362842	0	0	0
T18	575732	2039	0	0
T19	25209	0	0	0
T20	1547	0	0	0
T27	0	3	0	0
T31	979054	3	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	499	0	0
T36	0	29	0	0
T44	254389	0	0	0
T45	1178	0	0	0
T51	0	633	0	0
T74	0	4	0	0

ExcessiveMaskStored_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	67327	0	0
T14	225816	4	0	0
T15	471188	0	0	0
T16	323942	0	0	0
T17	362842	0	0	0
T18	575732	2039	0	0
T19	25209	0	0	0
T20	1547	0	0	0
T27	0	3	0	0
T31	979054	3	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	499	0	0
T36	0	29	0	0
T44	254389	0	0	0
T45	1178	0	0	0
T51	0	633	0	0
T74	0	4	0	0

FlushFollowedByDone_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352908	0	1048
T4	166780	29	0	1
T5	916801	374	0	1
T6	181564	390	0	1
T7	1485	0	0	1
T13	908005	69	0	1
T14	225816	27	0	1
T15	471188	310	0	1
T16	323942	141	0	1
T17	362842	80	0	1
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	1

ValidIDeassertedOnFlush_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	559533	0	0
T4	166780	56	0	0
T5	916801	700	0	0
T6	181564	730	0	0
T7	1485	0	0	0
T13	908005	132	0	0
T14	225816	49	0	0
T15	471188	580	0	0
T16	323942	259	0	0
T17	362842	151	0	0
T18	0	598	0	0
T19	0	18	0	0
T20	1547	0	0	0

ValidOAssertedForStoredDataGTEOutW_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48498842	0	0
T4	166780	3641	0	0
T5	916801	90348	0	0
T6	181564	95772	0	0
T7	1485	0	0	0
T13	908005	46315	0	0
T14	225816	1654	0	0
T15	471188	68812	0	0
T16	323942	8758	0	0
T17	362842	56361	0	0
T18	0	56593	0	0
T19	0	100	0	0
T20	1547	0	0	0

ValidOPairedWidthReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	129251	0	0
T8	0	76	0	0
T18	575732	3933	0	0
T19	25209	0	0	0
T29	0	64	0	0
T30	0	193	0	0
T31	979054	0	0	0
T34	0	771	0	0
T39	0	97	0	0
T40	0	76	0	0
T44	254389	0	0	0
T45	1178	0	0	0
T46	125404	0	0	0
T47	213511	0	0	0
T48	749148	0	0	0
T49	6549	0	0	0
T50	230685	0	0	0
T51	0	1006	0	0
T116	0	71	0	0
T117	0	115	0	0

g_byte_assert.InputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

g_byte_assert.OutputDividedBy8_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

g_byte_assert.g_byte_input_masking[0].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110669935	0	0
T4	166780	7970	0	0
T5	916801	210471	0	0
T6	181564	214895	0	0
T7	1485	1	0	0
T13	908005	92863	0	0
T14	225816	3265	0	0
T15	471188	161017	0	0
T16	323942	20700	0	0
T17	362842	112965	0	0
T18	0	110496	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_input_masking[1].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110669935	0	0
T4	166780	7970	0	0
T5	916801	210471	0	0
T6	181564	214895	0	0
T7	1485	1	0	0
T13	908005	92863	0	0
T14	225816	3265	0	0
T15	471188	161017	0	0
T16	323942	20700	0	0
T17	362842	112965	0	0
T18	0	110496	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_input_masking[2].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110669935	0	0
T4	166780	7970	0	0
T5	916801	210471	0	0
T6	181564	214895	0	0
T7	1485	1	0	0
T13	908005	92863	0	0
T14	225816	3265	0	0
T15	471188	161017	0	0
T16	323942	20700	0	0
T17	362842	112965	0	0
T18	0	110496	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_input_masking[3].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110669935	0	0
T4	166780	7970	0	0
T5	916801	210471	0	0
T6	181564	214895	0	0
T7	1485	1	0	0
T13	908005	92863	0	0
T14	225816	3265	0	0
T15	471188	161017	0	0
T16	323942	20700	0	0
T17	362842	112965	0	0
T18	0	110496	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_input_masking[4].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110669935	0	0
T4	166780	7970	0	0
T5	916801	210471	0	0
T6	181564	214895	0	0
T7	1485	1	0	0
T13	908005	92863	0	0
T14	225816	3265	0	0
T15	471188	161017	0	0
T16	323942	20700	0	0
T17	362842	112965	0	0
T18	0	110496	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_input_masking[5].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110669935	0	0
T4	166780	7970	0	0
T5	916801	210471	0	0
T6	181564	214895	0	0
T7	1485	1	0	0
T13	908005	92863	0	0
T14	225816	3265	0	0
T15	471188	161017	0	0
T16	323942	20700	0	0
T17	362842	112965	0	0
T18	0	110496	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_input_masking[6].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110669935	0	0
T4	166780	7970	0	0
T5	916801	210471	0	0
T6	181564	214895	0	0
T7	1485	1	0	0
T13	908005	92863	0	0
T14	225816	3265	0	0
T15	471188	161017	0	0
T16	323942	20700	0	0
T17	362842	112965	0	0
T18	0	110496	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_input_masking[7].InputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110669935	0	0
T4	166780	7970	0	0
T5	916801	210471	0	0
T6	181564	214895	0	0
T7	1485	1	0	0
T13	908005	92863	0	0
T14	225816	3265	0	0
T15	471188	161017	0	0
T16	323942	20700	0	0
T17	362842	112965	0	0
T18	0	110496	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_output_masking[0].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48703057	0	0
T4	166780	3668	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	46378	0	0
T14	225816	1676	0	0
T15	471188	69082	0	0
T16	323942	8876	0	0
T17	362842	56432	0	0
T18	0	56806	0	0
T19	0	109	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_output_masking[1].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48703057	0	0
T4	166780	3668	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	46378	0	0
T14	225816	1676	0	0
T15	471188	69082	0	0
T16	323942	8876	0	0
T17	362842	56432	0	0
T18	0	56806	0	0
T19	0	109	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_output_masking[2].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48703057	0	0
T4	166780	3668	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	46378	0	0
T14	225816	1676	0	0
T15	471188	69082	0	0
T16	323942	8876	0	0
T17	362842	56432	0	0
T18	0	56806	0	0
T19	0	109	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_output_masking[3].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48703057	0	0
T4	166780	3668	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	46378	0	0
T14	225816	1676	0	0
T15	471188	69082	0	0
T16	323942	8876	0	0
T17	362842	56432	0	0
T18	0	56806	0	0
T19	0	109	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_output_masking[4].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48703057	0	0
T4	166780	3668	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	46378	0	0
T14	225816	1676	0	0
T15	471188	69082	0	0
T16	323942	8876	0	0
T17	362842	56432	0	0
T18	0	56806	0	0
T19	0	109	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_output_masking[5].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48703057	0	0
T4	166780	3668	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	46378	0	0
T14	225816	1676	0	0
T15	471188	69082	0	0
T16	323942	8876	0	0
T17	362842	56432	0	0
T18	0	56806	0	0
T19	0	109	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_output_masking[6].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48703057	0	0
T4	166780	3668	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	46378	0	0
T14	225816	1676	0	0
T15	471188	69082	0	0
T16	323942	8876	0	0
T17	362842	56432	0	0
T18	0	56806	0	0
T19	0	109	0	0
T20	1547	0	0	0

g_byte_assert.g_byte_output_masking[7].OutputMaskContiguous_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48703057	0	0
T4	166780	3668	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	46378	0	0
T14	225816	1676	0	0
T15	471188	69082	0	0
T16	323942	8876	0	0
T17	362842	56432	0	0
T18	0	56806	0	0
T19	0	109	0	0
T20	1547	0	0	0

gen_mask_assert.ContiguousOnesMask_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	110669935	0	0
T4	166780	7970	0	0
T5	916801	210471	0	0
T6	181564	214895	0	0
T7	1485	1	0	0
T13	908005	92863	0	0
T14	225816	3265	0	0
T15	471188	161017	0	0
T16	323942	20700	0	0
T17	362842	112965	0	0
T18	0	110496	0	0
T20	1547	0	0	0