Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	116533249	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1263	1263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	116533249	0	0
T3	2076	167	0	0
T55	1596	0	0	0
T56	20674	0	0	0
T57	6293	0	0	0
T58	0	306	0	0
T59	2423	0	0	0
T60	942	0	0	0
T63	955	0	0	0
T87	21952	0	0	0
T88	5427	0	0	0
T89	0	45	0	0
T90	0	512	0	0
T91	0	322	0	0
T92	0	51	0	0
T97	11721	0	0	0
T98	0	721	0	0
T99	0	55	0	0
T100	0	257	0	0
T101	0	130	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263	1263	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T63	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	208762018	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1263	1263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	208762018	0	0
T3	2076	155	0	0
T55	1596	0	0	0
T56	20674	0	0	0
T57	6293	0	0	0
T58	0	297	0	0
T59	2423	0	0	0
T60	942	0	0	0
T63	955	0	0	0
T87	21952	0	0	0
T88	5427	0	0	0
T89	0	44	0	0
T90	0	369	0	0
T91	0	318	0	0
T92	0	47	0	0
T97	11721	0	0	0
T98	0	361	0	0
T99	0	185	0	0
T100	0	137	0	0
T101	0	353	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263	1263	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T63	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	318230745	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1263	1263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	318230745	0	0
T1	1956	40	0	0
T2	2505	200	0	0
T3	2076	596	0	0
T55	1596	269	0	0
T56	20674	3008	0	0
T57	6293	897	0	0
T59	2423	270	0	0
T60	942	22	0	0
T63	955	22	0	0
T87	21952	3828	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263	1263	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T63	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	579219077	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1263	1263	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	579219077	0	0
T1	1956	120	0	0
T2	2505	188	0	0
T3	2076	382	0	0
T55	1596	151	0	0
T56	20674	2775	0	0
T57	6293	807	0	0
T59	2423	246	0	0
T60	942	22	0	0
T63	955	22	0	0
T87	21952	3483	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1956	1893	0	0
T2	2505	2174	0	0
T3	2076	2008	0	0
T55	1596	1336	0	0
T56	20674	19172	0	0
T57	6293	5821	0	0
T59	2423	2352	0	0
T60	942	865	0	0
T63	955	899	0	0
T87	21952	21883	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1263	1263	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T63	1	1	0	0
T87	1	1	0	0