Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1425776	0	0
entropy_period_rd_A	2147483647	3454	0	0
intr_enable_rd_A	2147483647	3503	0	0
prefix_0_rd_A	2147483647	2773	0	0
prefix_10_rd_A	2147483647	2632	0	0
prefix_1_rd_A	2147483647	2928	0	0
prefix_2_rd_A	2147483647	2763	0	0
prefix_3_rd_A	2147483647	3088	0	0
prefix_4_rd_A	2147483647	2903	0	0
prefix_5_rd_A	2147483647	2761	0	0
prefix_6_rd_A	2147483647	2935	0	0
prefix_7_rd_A	2147483647	2963	0	0
prefix_8_rd_A	2147483647	2871	0	0
prefix_9_rd_A	2147483647	3030	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1425776	0	0
T3	2076	159	0	0
T55	1596	0	0	0
T56	20674	1	0	0
T57	6293	0	0	0
T58	0	127	0	0
T59	2423	0	0	0
T60	942	0	0	0
T63	955	0	0	0
T87	21952	0	0	0
T88	5427	0	0	0
T90	0	118	0	0
T91	0	154	0	0
T97	11721	0	0	0
T99	0	1	0	0
T118	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3454	0	0
T58	5401	0	0	0
T97	11721	90	0	0
T98	1430	0	0	0
T99	0	7	0	0
T101	0	8	0	0
T104	12879	90	0	0
T105	11891	62	0	0
T106	0	62	0	0
T110	13832	85	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	1	0	0
T123	6289	33	0	0
T124	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3503	0	0
T1	1956	9	0	0
T2	2505	0	0	0
T3	2076	0	0	0
T55	1596	0	0	0
T56	20674	0	0	0
T57	6293	0	0	0
T59	2423	0	0	0
T60	942	0	0	0
T63	955	0	0	0
T87	21952	0	0	0
T97	0	32	0	0
T99	0	13	0	0
T104	0	99	0	0
T105	0	91	0	0
T110	0	98	0	0
T122	0	11	0	0
T123	0	25	0	0
T124	0	3	0	0
T140	0	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2773	0	0
T58	5401	0	0	0
T97	11721	43	0	0
T98	1430	0	0	0
T99	0	1	0	0
T101	0	8	0	0
T104	12879	61	0	0
T105	11891	55	0	0
T106	0	9	0	0
T110	13832	65	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	4	0	0
T123	6289	33	0	0
T124	0	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2632	0	0
T58	5401	0	0	0
T97	11721	11	0	0
T98	1430	0	0	0
T99	0	2	0	0
T101	0	4	0	0
T104	12879	55	0	0
T105	11891	52	0	0
T106	0	28	0	0
T110	13832	74	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	3	0	0
T123	6289	35	0	0
T124	0	11	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2928	0	0
T58	5401	0	0	0
T97	11721	49	0	0
T98	1430	0	0	0
T99	0	3	0	0
T101	0	12	0	0
T104	12879	52	0	0
T105	11891	25	0	0
T106	0	20	0	0
T110	13832	66	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	0	0	0
T123	6289	13	0	0
T124	0	3	0	0
T141	0	481	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2763	0	0
T58	5401	0	0	0
T97	11721	43	0	0
T98	1430	0	0	0
T99	0	6	0	0
T101	0	2	0	0
T104	12879	59	0	0
T105	11891	46	0	0
T106	0	34	0	0
T110	13832	72	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	0	0	0
T123	6289	2	0	0
T124	0	4	0	0
T141	0	470	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3088	0	0
T58	5401	0	0	0
T97	11721	74	0	0
T98	1430	0	0	0
T99	0	16	0	0
T101	0	11	0	0
T104	12879	44	0	0
T105	11891	58	0	0
T106	0	43	0	0
T110	13832	55	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	0	0	0
T123	6289	12	0	0
T124	0	5	0	0
T141	0	484	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2903	0	0
T58	5401	0	0	0
T97	11721	58	0	0
T98	1430	0	0	0
T99	0	12	0	0
T101	0	10	0	0
T104	12879	59	0	0
T105	11891	54	0	0
T106	0	43	0	0
T110	13832	46	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	7	0	0
T123	6289	10	0	0
T124	0	10	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2761	0	0
T58	5401	0	0	0
T97	11721	9	0	0
T98	1430	0	0	0
T99	0	4	0	0
T101	0	6	0	0
T104	12879	44	0	0
T105	11891	38	0	0
T106	0	38	0	0
T110	13832	42	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	11	0	0
T123	6289	23	0	0
T124	0	6	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2935	0	0
T58	5401	0	0	0
T97	11721	29	0	0
T98	1430	0	0	0
T99	0	5	0	0
T101	0	6	0	0
T104	12879	49	0	0
T105	11891	38	0	0
T106	0	37	0	0
T110	13832	75	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	5	0	0
T123	6289	40	0	0
T124	0	9	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2963	0	0
T58	5401	0	0	0
T97	11721	45	0	0
T98	1430	0	0	0
T99	0	12	0	0
T101	0	3	0	0
T104	12879	74	0	0
T105	11891	42	0	0
T106	0	32	0	0
T110	13832	70	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	2	0	0
T123	6289	6	0	0
T124	0	6	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2871	0	0
T58	5401	0	0	0
T97	11721	43	0	0
T98	1430	0	0	0
T99	0	13	0	0
T101	0	4	0	0
T104	12879	71	0	0
T105	11891	42	0	0
T106	0	35	0	0
T110	13832	68	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	0	0	0
T123	6289	30	0	0
T124	0	3	0	0
T141	0	442	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3030	0	0
T58	5401	0	0	0
T97	11721	48	0	0
T98	1430	0	0	0
T99	0	2	0	0
T101	0	3	0	0
T104	12879	82	0	0
T105	11891	45	0	0
T106	0	10	0	0
T110	13832	51	0	0
T111	4298	0	0	0
T118	9848	0	0	0
T122	2840	2	0	0
T123	6289	11	0	0
T124	0	10	0	0