Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	99.38	88.37		90.48	95.70	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	96.69	99.38	88.37		100.00	95.70	100.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.69	99.38	88.37		100.00	95.70	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.26	99.42	88.37	100.00	100.00	95.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.09	97.30	81.25		100.00	91.89	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	100.00	100.00					100.00
u_sentmsg_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		162	161	99.38
ALWAYS	157	6	6	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
ALWAYS	266	6	6	100.00
ALWAYS	278	3	3	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	292	3	3	100.00
ALWAYS	297	76	75	98.68
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
ALWAYS	557	4	4	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	590	5	5	100.00
ALWAYS	602	5	5	100.00
ALWAYS	614	5	5	100.00
ALWAYS	663	10	10	100.00
ALWAYS	718	9	9	100.00
ALWAYS	778	6	6	100.00
ALWAYS	787	6	6	100.00
ALWAYS	797	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
208	1	1
212	1	1
235	1	1
241	1	1
246	1	1
256	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
			MISSING_ELSE
278	3	3
285	1	1
292	2	2
293	1	1
297	1	1
300	1	1
301	1	1
303	1	1
305	1	1
306	1	1
308	1	1
309	1	1
311	1	1
313	1	1
315	1	1
324	1	1
326	1	1
327	1	1
329	1	1
332	1	1
344	1	1
346	1	1
347	1	1
349	1	1
350	1	1
351	1	1
353	1	1
355	1	1
360	1	1
362	1	1
363	1	1
365	1	1
374	1	1
376	1	1
377	1	1
379	1	1
380	1	1
382	1	1
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
391	1	1
393	1	1
399	1	1
401	1	1
402	1	1
404	1	1
413	1	1
415	1	1
417	1	1
420	1	1
423	1	1
424	1	1
425	1	1
426	1	1
427	1	1
429	0	1
434	1	1
436	1	1
437	1	1
446	1	1
450	1	1
451	1	1
453	1	1
454	1	1
455	1	1
457	1	1
459	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
473	1	1
479	1	1
480	1	1
493	1	1
494	1	1
			MISSING_ELSE
508	1	1
519	1	1
540	1	1
557	1	1
558	1	1
559	1	1
560	1	1
580	1	1
587	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
614	1	1
615	1	1
616	1	1
617	1	1
618	1	1
663	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
672	1	1
673	1	1
			MISSING_ELSE
718	1	1
719	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
778	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
787	1	1
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
			MISSING_ELSE
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
			MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       212
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       235
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T7,T13

 LINE       235
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T7,T13

 LINE       241
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       241
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       246
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       256
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       376
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       387
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T16

 LINE       417
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T13

 LINE       587
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       603
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T18,T34,T51
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       615
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Not Covered

 LINE       615
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	21	19	90.48
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	329	Covered	T1
StMessageWait	382	Covered	T1
StPad	388	Covered	T1
StPad01	426	Covered	T1
StPadFlush	434	Covered	T1
StPadIdle	332	Covered	T1
StPadRun	420	Covered	T1
StPrefix	327	Covered	T1
StPrefixWait	347	Covered	T1
StTerminalError	494	Covered	T1

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	382	Covered	T1
StMessage->StPad	388	Covered	T1
StMessage->StTerminalError	494	Covered	T1
StMessageWait->StMessage	402	Covered	T1
StMessageWait->StTerminalError	494	Covered	T1
StPad->StPad01	426	Covered	T1
StPad->StPadRun	420	Covered	T1
StPad->StTerminalError	494	Not Covered
StPad01->StPadFlush	451	Covered	T1
StPad01->StTerminalError	494	Covered	T1
StPadFlush->StPadIdle	469	Covered	T1
StPadFlush->StTerminalError	494	Covered	T1
StPadIdle->StMessage	329	Covered	T1
StPadIdle->StPrefix	327	Covered	T1
StPadIdle->StTerminalError	494	Covered	T1
StPadRun->StPadFlush	434	Covered	T1
StPadRun->StTerminalError	494	Not Covered
StPrefix->StPrefixWait	347	Covered	T1
StPrefix->StTerminalError	494	Covered	T1
StPrefixWait->StMessage	363	Covered	T1
StPrefixWait->StTerminalError	494	Covered	T1

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	212	2	2	100.00
TERNARY	235	2	2	100.00
TERNARY	241	2	2	100.00
TERNARY	285	2	2	100.00
TERNARY	587	2	2	100.00
CASE	157	6	5	83.33
IF	266	4	4	100.00
IF	278	2	2	100.00
IF	292	2	2	100.00
CASE	315	23	22	95.65
IF	493	2	2	100.00
CASE	557	4	3	75.00
CASE	590	5	5	100.00
CASE	602	5	5	100.00
CASE	614	5	5	100.00
IF	663	4	4	100.00
IF	778	4	4	100.00
IF	787	4	4	100.00
IF	797	4	4	100.00
CASE	718	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	235	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	285	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	587	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T6,T18,T102
L256	Covered	T4,T5,T6
L384	Covered	T4,T14,T15
L512	Covered	T13,T17,T18
default	Not Covered

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if (process_i)
-3-:	270	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	case (st)
-2-:	324	if (start_i)
-3-:	326	if (mode_eq_cshake)
-4-:	346	if (sent_blocksize)
-5-:	362	if (keccak_complete_i)
-6-:	376	if ((msg_valid_i && msg_partial))
-7-:	380	if (sent_blocksize)
-8-:	387	if ((process_latched || process_i))
-9-:	401	if (keccak_complete_i)
-10-:	417	if ((keccak_ack && end_of_block))
-11-:	425	if (keccak_ack)
-12-:	450	if (sent_blocksize)
-13-:	468	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T13
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T13,T14
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T13
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T13,T14
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T13,T14
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T5,T6
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T5,T6,T13
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T4,T5,T6
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T13
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T5,T6
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T5,T6
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	493	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	557	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T4,T5,T6
Shake	Covered	T4,T13,T14
CShake	Covered	T4,T7,T13
default	Not Covered

	LineNo.	Expression
-1-:	590	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T7,T13
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	602	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T7,T13
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	614	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T7,T13
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	663	if ((!rst_ni))
-2-:	666	if (en_msgbuf)
-3-:	671	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	778	if ((!rst_ni))
-2-:	780	if (start_i)
-3-:	782	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	787	if ((!rst_ni))
-2-:	789	if (start_i)
-3-:	791	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	797	if ((!rst_ni))
-2-:	799	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	801	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	718	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T4,T5,T6
7'b0000001	Covered	T4,T5,T6
7'b0000011	Covered	T4,T5,T6
7'b0000111	Covered	T4,T5,T6
7'b0001111	Covered	T4,T5,T6
7'b0011111	Covered	T4,T5,T6
7'b0111111	Covered	T4,T5,T6
7'b1111111	Covered	T4,T5,T6
default	Not Covered

---

Assert Coverage for Module : sha3pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	352906	0	0
AlwaysPartialMsgBuf_M	2147483647	203175	0	0
CompleteBlockWhenProcess_A	2147483647	341214	0	0
DoneCondition_M	2147483647	352890	0	0
DonePulse_A	2147483647	352890	0	0
KeccakAddrInRange_A	2147483647	54169847	0	0
KeccakRunPulse_A	2147483647	3135335	0	0
MessageCondition_M	2147483647	49300848	0	0
ModeStableDuringOp_M	2147483647	36606	0	0
MsgReadyCondition_A	2147483647	2147483647	0	0
MsgWidthidth_A	1048	1048	0	0
NoPartialMsgFifo_M	2147483647	49097673	0	0
Pad01NotAttheEndOfBlock_A	2147483647	342043	0	0
PartialEndOfMsg_M	2147483647	203175	0	0
PrefixLessThanBlock_A	1048	1048	0	0
ProcessCondition_M	2147483647	352908	0	0
ProcessPulse_A	2147483647	352908	0	0
StartCondition_M	2147483647	353018	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	353018	0	0
StrengthStableDuringOp_M	2147483647	43858	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352906	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	203175	0	0
T4	166780	27	0	0
T5	916801	326	0	0
T6	181564	340	0	0
T7	1485	0	0	0
T13	908005	63	0	0
T14	225816	22	0	0
T15	471188	270	0	0
T16	323942	118	0	0
T17	362842	71	0	0
T18	0	213	0	0
T19	0	9	0	0
T20	1547	0	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	341214	0	0
T4	166780	28	0	0
T5	916801	358	0	0
T6	181564	372	0	0
T7	1485	0	0	0
T13	908005	65	0	0
T14	225816	23	0	0
T15	471188	289	0	0
T16	323942	135	0	0
T17	362842	76	0	0
T18	0	248	0	0
T19	0	9	0	0
T20	1547	0	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352890	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352890	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	54169847	0	0
T4	166780	4891	0	0
T5	916801	93942	0	0
T6	181564	99756	0	0
T7	1485	15	0	0
T13	908005	49076	0	0
T14	225816	2507	0	0
T15	471188	71006	0	0
T16	323942	14236	0	0
T17	362842	59441	0	0
T18	0	62824	0	0
T20	1547	0	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3135335	0	0
T4	166780	265	0	0
T5	916801	5526	0	0
T6	181564	5542	0	0
T7	1485	0	0	0
T13	908005	2596	0	0
T14	225816	135	0	0
T15	471188	5462	0	0
T16	323942	752	0	0
T17	362842	3209	0	0
T18	0	3349	0	0
T19	0	31	0	0
T20	1547	0	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49300848	0	0
T4	166780	4090	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	47399	0	0
T14	225816	1925	0	0
T15	471188	69082	0	0
T16	323942	10918	0	0
T17	362842	57521	0	0
T18	0	56250	0	0
T19	0	286	0	0
T20	1547	0	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36606	0	0
T4	166780	16	0	0
T5	916801	0	0	0
T6	181564	0	0	0
T7	1485	1	0	0
T13	908005	29	0	0
T14	225816	26	0	0
T15	471188	0	0	0
T16	323942	64	0	0
T17	362842	39	0	0
T18	0	163	0	0
T19	0	1	0	0
T20	1547	0	0	0
T31	0	136	0	0
T44	0	1	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	166780	455870	0	0
T5	916801	871854	0	0
T6	181564	158914	0	0
T7	1485	0	0	0
T13	908005	598467	0	0
T14	225816	119671	0	0
T15	471188	438759	0	0
T16	323942	153436	0	0
T17	362842	192645	0	0
T18	0	267884	0	0
T19	0	10878	0	0
T20	1547	0	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49097673	0	0
T4	166780	4063	0	0
T5	916801	90348	0	0
T6	181564	95772	0	0
T7	1485	0	0	0
T13	908005	47336	0	0
T14	225816	1903	0	0
T15	471188	68812	0	0
T16	323942	10800	0	0
T17	362842	57450	0	0
T18	0	56037	0	0
T19	0	277	0	0
T20	1547	0	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	342043	0	0
T4	166780	29	0	0
T5	916801	358	0	0
T6	181564	374	0	0
T7	1485	0	0	0
T13	908005	65	0	0
T14	225816	23	0	0
T15	471188	289	0	0
T16	323942	136	0	0
T17	362842	79	0	0
T18	0	252	0	0
T19	0	9	0	0
T20	1547	0	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	203175	0	0
T4	166780	27	0	0
T5	916801	326	0	0
T6	181564	340	0	0
T7	1485	0	0	0
T13	908005	63	0	0
T14	225816	22	0	0
T15	471188	270	0	0
T16	323942	118	0	0
T17	362842	71	0	0
T18	0	213	0	0
T19	0	9	0	0
T20	1547	0	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352908	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352908	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	353018	0	0
T4	166780	32	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	1	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T20	1547	0	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	166780	166772	0	0
T5	916801	916791	0	0
T6	181564	181558	0	0
T7	1485	1323	0	0
T13	908005	907913	0	0
T14	225816	225756	0	0
T15	471188	471179	0	0
T16	323942	323879	0	0
T17	362842	362752	0	0
T20	1547	1449	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	353018	0	0
T4	166780	32	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	1	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T20	1547	0	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43858	0	0
T4	166780	23	0	0
T5	916801	2	0	0
T6	181564	2	0	0
T7	1485	3	0	0
T13	908005	31	0	0
T14	225816	27	0	0
T15	471188	2	0	0
T16	323942	79	0	0
T17	362842	44	0	0
T20	1547	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	166780	166772	0	0
T5	916801	916791	0	0
T6	181564	181558	0	0
T7	1485	1323	0	0
T13	908005	907913	0	0
T14	225816	225756	0	0
T15	471188	471179	0	0
T16	323942	323879	0	0
T17	362842	362752	0	0
T20	1547	1449	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	8822653	0
StMessageFeed_C	2147483647	2147483647	0
StPadSendMsg_C	2147483647	3924512	0
StPad_C	2147483647	342042	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	8822653	0
T4	166780	725	0
T5	916801	9350	0
T6	181564	9750	0
T7	1485	0	0
T13	908005	1725	0
T14	225816	675	0
T15	471188	7750	0
T16	323942	3525	0
T17	362842	2000	0
T18	0	6450	0
T19	0	225	0
T20	1547	0	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2147483647	0
T4	166780	456111	0
T5	916801	872406	0
T6	181564	159468	0
T7	1485	0	0
T13	908005	601010	0
T14	225816	119789	0
T15	471188	439305	0
T16	323942	154082	0
T17	362842	195797	0
T18	0	271038	0
T19	0	10900	0
T20	1547	0	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3924512	0
T4	166780	339	0
T5	916801	3220	0
T6	181564	3594	0
T7	1485	0	0
T13	908005	650	0
T14	225816	252	0
T15	471188	1884	0
T16	323942	1253	0
T17	362842	822	0
T18	0	2822	0
T19	0	144	0
T20	1547	0	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	342042	0
T4	166780	29	0
T5	916801	358	0
T6	181564	374	0
T7	1485	0	0
T13	908005	65	0
T14	225816	23	0
T15	471188	289	0
T16	323942	136	0
T17	362842	79	0
T18	0	252	0
T19	0	9	0
T20	1547	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		162	161	99.38
ALWAYS	157	6	6	100.00
CONT_ASSIGN	208	1	1	100.00
CONT_ASSIGN	212	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	246	1	1	100.00
CONT_ASSIGN	256	1	1	100.00
ALWAYS	266	6	6	100.00
ALWAYS	278	3	3	100.00
CONT_ASSIGN	285	1	1	100.00
ALWAYS	292	3	3	100.00
ALWAYS	297	76	75	98.68
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
ALWAYS	557	4	4	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	587	1	1	100.00
ALWAYS	590	5	5	100.00
ALWAYS	602	5	5	100.00
ALWAYS	614	5	5	100.00
ALWAYS	663	10	10	100.00
ALWAYS	718	9	9	100.00
ALWAYS	778	6	6	100.00
ALWAYS	787	6	6	100.00
ALWAYS	797	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	1	1
158	1	1
159	1	1
160	1	1
161	1	1
162	1	1
208	1	1
212	1	1
235	1	1
241	1	1
246	1	1
256	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
271	1	1
			MISSING_ELSE
278	3	3
285	1	1
292	2	2
293	1	1
297	1	1
300	1	1
301	1	1
303	1	1
305	1	1
306	1	1
308	1	1
309	1	1
311	1	1
313	1	1
315	1	1
324	1	1
326	1	1
327	1	1
329	1	1
332	1	1
344	1	1
346	1	1
347	1	1
349	1	1
350	1	1
351	1	1
353	1	1
355	1	1
360	1	1
362	1	1
363	1	1
365	1	1
374	1	1
376	1	1
377	1	1
379	1	1
380	1	1
382	1	1
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
391	1	1
393	1	1
399	1	1
401	1	1
402	1	1
404	1	1
413	1	1
415	1	1
417	1	1
420	1	1
423	1	1
424	1	1
425	1	1
426	1	1
427	1	1
429	0	1
434	1	1
436	1	1
437	1	1
446	1	1
450	1	1
451	1	1
453	1	1
454	1	1
455	1	1
457	1	1
459	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
473	1	1
479	1	1
480	1	1
493	1	1
494	1	1
			MISSING_ELSE
508	1	1
519	1	1
540	1	1
557	1	1
558	1	1
559	1	1
560	1	1
580	1	1
587	1	1
590	1	1
591	1	1
592	1	1
593	1	1
594	1	1
602	1	1
603	1	1
604	1	1
605	1	1
606	1	1
614	1	1
615	1	1
616	1	1
617	1	1
618	1	1
663	1	1
664	1	1
665	1	1
666	1	1
667	1	1
668	1	1
670	1	1
671	1	1
672	1	1
673	1	1
			MISSING_ELSE
718	1	1
719	1	1
720	1	1
721	1	1
722	1	1
723	1	1
724	1	1
725	1	1
726	1	1
778	1	1
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
			MISSING_ELSE
787	1	1
788	1	1
789	1	1
790	1	1
791	1	1
792	1	1
			MISSING_ELSE
797	1	1
798	1	1
799	1	1
800	1	1
801	1	1
802	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	38	88.37
Logical	43	38	88.37
Non-Logical	0	0
Event	0	0

 LINE       208
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       212
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       235
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T7,T13

 LINE       235
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T7,T13

 LINE       241
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       241
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       246
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       256
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       285
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       376
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       387
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T16

 LINE       417
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T6,T13

 LINE       587
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       603
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T18,T34,T51
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       615
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Not Covered

 LINE       615
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	17	17	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	329	Covered	T1
StMessageWait	382	Covered	T1
StPad	388	Covered	T1
StPad01	426	Covered	T1
StPadFlush	434	Covered	T1
StPadIdle	332	Covered	T1
StPadRun	420	Covered	T1
StPrefix	327	Covered	T1
StPrefixWait	347	Covered	T1
StTerminalError	494	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	382	Covered	T1
StMessage->StPad	388	Covered	T1
StMessage->StTerminalError	494	Covered	T1
StMessageWait->StMessage	402	Covered	T1
StMessageWait->StTerminalError	494	Covered	T1
StPad->StPad01	426	Covered	T1
StPad->StPadRun	420	Covered	T1
StPad->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	451	Covered	T1
StPad01->StTerminalError	494	Covered	T1
StPadFlush->StPadIdle	469	Covered	T1
StPadFlush->StTerminalError	494	Excluded	T1	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadIdle->StMessage	329	Covered	T1
StPadIdle->StPrefix	327	Covered	T1
StPadIdle->StTerminalError	494	Covered	T1
StPadRun->StPadFlush	434	Covered	T1
StPadRun->StTerminalError	494	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	347	Covered	T1
StPrefix->StTerminalError	494	Excluded	T1	[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefixWait->StMessage	363	Covered	T1
StPrefixWait->StTerminalError	494	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	89	95.70
TERNARY	212	2	2	100.00
TERNARY	235	2	2	100.00
TERNARY	241	2	2	100.00
TERNARY	285	2	2	100.00
TERNARY	587	2	2	100.00
CASE	157	6	5	83.33
IF	266	4	4	100.00
IF	278	2	2	100.00
IF	292	2	2	100.00
CASE	315	23	22	95.65
IF	493	2	2	100.00
CASE	557	4	3	75.00
CASE	590	5	5	100.00
CASE	602	5	5	100.00
CASE	614	5	5	100.00
IF	663	4	4	100.00
IF	778	4	4	100.00
IF	787	4	4	100.00
IF	797	4	4	100.00
CASE	718	9	8	88.89

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	212	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	235	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	241	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	285	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	587	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Covered	T4,T5,T6
L224	Covered	T6,T18,T102
L256	Covered	T4,T5,T6
L384	Covered	T4,T14,T15
L512	Covered	T13,T17,T18
default	Not Covered

	LineNo.	Expression
-1-:	266	if ((!rst_ni))
-2-:	268	if (process_i)
-3-:	270	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	278	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	292	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	315	case (st)
-2-:	324	if (start_i)
-3-:	326	if (mode_eq_cshake)
-4-:	346	if (sent_blocksize)
-5-:	362	if (keccak_complete_i)
-6-:	376	if ((msg_valid_i && msg_partial))
-7-:	380	if (sent_blocksize)
-8-:	387	if ((process_latched || process_i))
-9-:	401	if (keccak_complete_i)
-10-:	417	if ((keccak_ack && end_of_block))
-11-:	425	if (keccak_ack)
-12-:	450	if (sent_blocksize)
-13-:	468	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T13
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T4,T13,T14
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T13
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T13,T14
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T4,T13,T14
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Covered	T4,T5,T6
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T5,T6
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T4,T5,T6
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T5,T6,T13
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T4,T5,T6
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T13
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T4,T5,T6
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T4,T5,T6
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	493	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	557	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Covered	T4,T5,T6
Shake	Covered	T4,T13,T14
CShake	Covered	T4,T7,T13
default	Not Covered

	LineNo.	Expression
-1-:	590	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T7,T13
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	602	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T7,T13
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	614	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Covered	T4,T5,T6
MuxPrefix	Covered	T4,T7,T13
MuxFuncPad	Covered	T4,T5,T6
MuxZeroEnd	Covered	T4,T5,T6
default	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	663	if ((!rst_ni))
-2-:	666	if (en_msgbuf)
-3-:	671	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	778	if ((!rst_ni))
-2-:	780	if (start_i)
-3-:	782	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	787	if ((!rst_ni))
-2-:	789	if (start_i)
-3-:	791	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	797	if ((!rst_ni))
-2-:	799	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	801	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	718	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Covered	T4,T5,T6
7'b0000001	Covered	T4,T5,T6
7'b0000011	Covered	T4,T5,T6
7'b0000111	Covered	T4,T5,T6
7'b0001111	Covered	T4,T5,T6
7'b0011111	Covered	T4,T5,T6
7'b0111111	Covered	T4,T5,T6
7'b1111111	Covered	T4,T5,T6
default	Not Covered

---

Assert Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	22	100.00
Cover properties	4	4	100.00	4	100.00
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AbsorbedPulse_A	2147483647	352906	0	0
AlwaysPartialMsgBuf_M	2147483647	203175	0	0
CompleteBlockWhenProcess_A	2147483647	341214	0	0
DoneCondition_M	2147483647	352890	0	0
DonePulse_A	2147483647	352890	0	0
KeccakAddrInRange_A	2147483647	54169847	0	0
KeccakRunPulse_A	2147483647	3135335	0	0
MessageCondition_M	2147483647	49300848	0	0
ModeStableDuringOp_M	2147483647	36606	0	0
MsgReadyCondition_A	2147483647	2147483647	0	0
MsgWidthidth_A	1048	1048	0	0
NoPartialMsgFifo_M	2147483647	49097673	0	0
Pad01NotAttheEndOfBlock_A	2147483647	342043	0	0
PartialEndOfMsg_M	2147483647	203175	0	0
PrefixLessThanBlock_A	1048	1048	0	0
ProcessCondition_M	2147483647	352908	0	0
ProcessPulse_A	2147483647	352908	0	0
StartCondition_M	2147483647	353018	0	0
StartProcessDoneMutex_a	2147483647	2147483647	0	0
StartPulse_A	2147483647	353018	0	0
StrengthStableDuringOp_M	2147483647	43858	0	0
u_state_regs_A	2147483647	2147483647	0	0

AbsorbedPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352906	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

AlwaysPartialMsgBuf_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	203175	0	0
T4	166780	27	0	0
T5	916801	326	0	0
T6	181564	340	0	0
T7	1485	0	0	0
T13	908005	63	0	0
T14	225816	22	0	0
T15	471188	270	0	0
T16	323942	118	0	0
T17	362842	71	0	0
T18	0	213	0	0
T19	0	9	0	0
T20	1547	0	0	0

CompleteBlockWhenProcess_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	341214	0	0
T4	166780	28	0	0
T5	916801	358	0	0
T6	181564	372	0	0
T7	1485	0	0	0
T13	908005	65	0	0
T14	225816	23	0	0
T15	471188	289	0	0
T16	323942	135	0	0
T17	362842	76	0	0
T18	0	248	0	0
T19	0	9	0	0
T20	1547	0	0	0

DoneCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352890	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

DonePulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352890	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

KeccakAddrInRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	54169847	0	0
T4	166780	4891	0	0
T5	916801	93942	0	0
T6	181564	99756	0	0
T7	1485	15	0	0
T13	908005	49076	0	0
T14	225816	2507	0	0
T15	471188	71006	0	0
T16	323942	14236	0	0
T17	362842	59441	0	0
T18	0	62824	0	0
T20	1547	0	0	0

KeccakRunPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3135335	0	0
T4	166780	265	0	0
T5	916801	5526	0	0
T6	181564	5542	0	0
T7	1485	0	0	0
T13	908005	2596	0	0
T14	225816	135	0	0
T15	471188	5462	0	0
T16	323942	752	0	0
T17	362842	3209	0	0
T18	0	3349	0	0
T19	0	31	0	0
T20	1547	0	0	0

MessageCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49300848	0	0
T4	166780	4090	0	0
T5	916801	90674	0	0
T6	181564	96112	0	0
T7	1485	0	0	0
T13	908005	47399	0	0
T14	225816	1925	0	0
T15	471188	69082	0	0
T16	323942	10918	0	0
T17	362842	57521	0	0
T18	0	56250	0	0
T19	0	286	0	0
T20	1547	0	0	0

ModeStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36606	0	0
T4	166780	16	0	0
T5	916801	0	0	0
T6	181564	0	0	0
T7	1485	1	0	0
T13	908005	29	0	0
T14	225816	26	0	0
T15	471188	0	0	0
T16	323942	64	0	0
T17	362842	39	0	0
T18	0	163	0	0
T19	0	1	0	0
T20	1547	0	0	0
T31	0	136	0	0
T44	0	1	0	0

MsgReadyCondition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	166780	455870	0	0
T5	916801	871854	0	0
T6	181564	158914	0	0
T7	1485	0	0	0
T13	908005	598467	0	0
T14	225816	119671	0	0
T15	471188	438759	0	0
T16	323942	153436	0	0
T17	362842	192645	0	0
T18	0	267884	0	0
T19	0	10878	0	0
T20	1547	0	0	0

MsgWidthidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

NoPartialMsgFifo_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49097673	0	0
T4	166780	4063	0	0
T5	916801	90348	0	0
T6	181564	95772	0	0
T7	1485	0	0	0
T13	908005	47336	0	0
T14	225816	1903	0	0
T15	471188	68812	0	0
T16	323942	10800	0	0
T17	362842	57450	0	0
T18	0	56037	0	0
T19	0	277	0	0
T20	1547	0	0	0

Pad01NotAttheEndOfBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	342043	0	0
T4	166780	29	0	0
T5	916801	358	0	0
T6	181564	374	0	0
T7	1485	0	0	0
T13	908005	65	0	0
T14	225816	23	0	0
T15	471188	289	0	0
T16	323942	136	0	0
T17	362842	79	0	0
T18	0	252	0	0
T19	0	9	0	0
T20	1547	0	0	0

PartialEndOfMsg_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	203175	0	0
T4	166780	27	0	0
T5	916801	326	0	0
T6	181564	340	0	0
T7	1485	0	0	0
T13	908005	63	0	0
T14	225816	22	0	0
T15	471188	270	0	0
T16	323942	118	0	0
T17	362842	71	0	0
T18	0	213	0	0
T19	0	9	0	0
T20	1547	0	0	0

PrefixLessThanBlock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T20	1	1	0	0

ProcessCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352908	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

ProcessPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	352908	0	0
T4	166780	29	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	0	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T19	0	9	0	0
T20	1547	0	0	0

StartCondition_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	353018	0	0
T4	166780	32	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	1	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T20	1547	0	0	0

StartProcessDoneMutex_a

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	166780	166772	0	0
T5	916801	916791	0	0
T6	181564	181558	0	0
T7	1485	1323	0	0
T13	908005	907913	0	0
T14	225816	225756	0	0
T15	471188	471179	0	0
T16	323942	323879	0	0
T17	362842	362752	0	0
T20	1547	1449	0	0

StartPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	353018	0	0
T4	166780	32	0	0
T5	916801	374	0	0
T6	181564	390	0	0
T7	1485	1	0	0
T13	908005	69	0	0
T14	225816	27	0	0
T15	471188	310	0	0
T16	323942	141	0	0
T17	362842	80	0	0
T18	0	258	0	0
T20	1547	0	0	0

StrengthStableDuringOp_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	43858	0	0
T4	166780	23	0	0
T5	916801	2	0	0
T6	181564	2	0	0
T7	1485	3	0	0
T13	908005	31	0	0
T14	225816	27	0	0
T15	471188	2	0	0
T16	323942	79	0	0
T17	362842	44	0	0
T20	1547	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	166780	166772	0	0
T5	916801	916791	0	0
T6	181564	181558	0	0
T7	1485	1323	0	0
T13	908005	907913	0	0
T14	225816	225756	0	0
T15	471188	471179	0	0
T16	323942	323879	0	0
T17	362842	362752	0	0
T20	1547	1449	0	0

---

Cover Directives for Properties: Details

Name	Attempts	Matches	Incomplete
StComplete_C	2147483647	8822653	0
StMessageFeed_C	2147483647	2147483647	0
StPadSendMsg_C	2147483647	3924512	0
StPad_C	2147483647	342042	0

StComplete_C

Name	Attempts	Matches	Incomplete
Total	2147483647	8822653	0
T4	166780	725	0
T5	916801	9350	0
T6	181564	9750	0
T7	1485	0	0
T13	908005	1725	0
T14	225816	675	0
T15	471188	7750	0
T16	323942	3525	0
T17	362842	2000	0
T18	0	6450	0
T19	0	225	0
T20	1547	0	0

StMessageFeed_C

Name	Attempts	Matches	Incomplete
Total	2147483647	2147483647	0
T4	166780	456111	0
T5	916801	872406	0
T6	181564	159468	0
T7	1485	0	0
T13	908005	601010	0
T14	225816	119789	0
T15	471188	439305	0
T16	323942	154082	0
T17	362842	195797	0
T18	0	271038	0
T19	0	10900	0
T20	1547	0	0

StPadSendMsg_C

Name	Attempts	Matches	Incomplete
Total	2147483647	3924512	0
T4	166780	339	0
T5	916801	3220	0
T6	181564	3594	0
T7	1485	0	0
T13	908005	650	0
T14	225816	252	0
T15	471188	1884	0
T16	323942	1253	0
T17	362842	822	0
T18	0	2822	0
T19	0	144	0
T20	1547	0	0

StPad_C

Name	Attempts	Matches	Incomplete
Total	2147483647	342042	0
T4	166780	29	0
T5	916801	358	0
T6	181564	374	0
T7	1485	0	0
T13	908005	65	0
T14	225816	23	0
T15	471188	289	0
T16	323942	136	0
T17	362842	79	0
T18	0	252	0
T19	0	9	0
T20	1547	0	0