Group : kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg
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Group : kmac_env_pkg::app_cg_wrap::app_cfg_reg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

3 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
AppKeymgr_cg_(1) 100.00 1 100 1 64 64
AppLc_cg_(1) 100.00 1 100 1 64 64
AppRom_cg_(1) 100.00 1 100 1 64 64




Group Instance : AppKeymgr_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance AppKeymgr_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance AppKeymgr_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sw_configured_hash_mode 3 0 3 100.00 100 1 1 0



Group Instance : AppLc_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance AppLc_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance AppLc_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sw_configured_hash_mode 3 0 3 100.00 100 1 1 0



Group Instance : AppRom_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance AppRom_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance AppRom_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sw_configured_hash_mode 3 0 3 100.00 100 1 1 0


Summary for Variable sw_configured_hash_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for sw_configured_hash_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cshake 1207 1 T6 2 T17 1 T19 5
shake 1124 1 T6 2 T19 6 T25 6
sha3 1160 1 T6 7 T19 3 T25 6


Summary for Variable sw_configured_hash_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for sw_configured_hash_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cshake 551 1 T6 3 T19 5 T25 2
shake 593 1 T19 2 T30 2 T25 5
sha3 571 1 T6 8 T19 1 T30 1


Summary for Variable sw_configured_hash_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for sw_configured_hash_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
cshake 577 1 T6 1 T19 3 T25 4
shake 519 1 T6 4 T30 1 T35 13
sha3 577 1 T19 3 T25 2 T35 10

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