Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	263596543	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

210778220

1

T1

1308

T2

947

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	249629283	1			T1	666		T2	763		T3	2
values[0x0]	107834510	1			T1	303		T2	287		T3	111
values[0x1]	116910970	1			T1	340		T2	316		T3	261

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	205221193	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

269153570

1

T1

1308

T2

1079

T3

197

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3527804	1			T1	12		T2	6		T3	1
valid_sources[0x01]	3903201	1			T2	6		T3	1		T66	18
valid_sources[0x02]	3882515	1			T2	8		T58	1		T59	1
valid_sources[0x03]	1496439	1			T1	11		T2	2		T58	1
valid_sources[0x04]	1496600	1			T1	13		T2	7		T3	1
valid_sources[0x05]	1567246	1			T1	5		T2	8		T3	2
valid_sources[0x06]	1499245	1			T1	19		T3	1		T60	1
valid_sources[0x07]	1481809	1			T3	4		T66	15		T99	53
valid_sources[0x08]	4661883	1			T1	4		T2	4		T3	1
valid_sources[0x09]	2049306	1			T2	1		T3	1		T58	1
valid_sources[0x0a]	1866459	1			T2	13		T3	2		T59	1
valid_sources[0x0b]	1971411	1			T2	11		T66	16		T99	37
valid_sources[0x0c]	1492303	1			T2	2		T3	1		T60	2
valid_sources[0x0d]	1483552	1			T1	11		T2	4		T3	2
valid_sources[0x0e]	1496382	1			T3	1		T59	1		T60	1
valid_sources[0x0f]	2236152	1			T2	1		T3	4		T58	1
valid_sources[0x10]	1488871	1			T2	8		T60	1		T90	18
valid_sources[0x11]	2156704	1			T2	16		T3	1		T60	1
valid_sources[0x12]	1490795	1			T2	4		T3	1		T59	1
valid_sources[0x13]	1481687	1			T1	2		T2	7		T58	1
valid_sources[0x14]	1487032	1			T1	16		T2	1		T60	1
valid_sources[0x15]	1947616	1			T1	21		T2	5		T3	1
valid_sources[0x16]	3631021	1			T2	4		T3	2		T58	3
valid_sources[0x17]	1495046	1			T1	25		T2	1		T3	3
valid_sources[0x18]	1489526	1			T2	3		T3	1		T60	1
valid_sources[0x19]	1958761	1			T2	7		T60	1		T66	22
valid_sources[0x1a]	2111235	1			T3	7		T59	1		T66	6
valid_sources[0x1b]	1652842	1			T2	14		T3	1		T66	1
valid_sources[0x1c]	2153234	1			T1	17		T3	1		T58	7
valid_sources[0x1d]	1491204	1			T2	14		T3	1		T60	1
valid_sources[0x1e]	2407461	1			T2	2		T66	4		T99	53
valid_sources[0x1f]	1479852	1			T59	1		T60	1		T66	15
valid_sources[0x20]	1483529	1			T2	4		T3	2		T60	1
valid_sources[0x21]	2376790	1			T2	3		T3	1		T58	1
valid_sources[0x22]	1501938	1			T2	5		T60	1		T90	2
valid_sources[0x23]	1497872	1			T3	1		T58	1		T59	2
valid_sources[0x24]	1484843	1			T2	5		T59	1		T60	3
valid_sources[0x25]	2404219	1			T3	2		T66	1		T99	25
valid_sources[0x26]	3504046	1			T2	13		T99	61		T92	3
valid_sources[0x27]	1552985	1			T2	4		T3	2		T60	2
valid_sources[0x28]	1506857	1			T2	7		T59	2		T60	1
valid_sources[0x29]	1487353	1			T1	17		T2	7		T3	1
valid_sources[0x2a]	2251990	1			T2	6		T60	1		T90	3
valid_sources[0x2b]	1488950	1			T1	2		T2	6		T3	1
valid_sources[0x2c]	3547025	1			T1	8		T3	2		T60	1
valid_sources[0x2d]	1495177	1			T2	5		T3	1		T60	2
valid_sources[0x2e]	1571979	1			T66	26		T99	54		T92	5
valid_sources[0x2f]	1489250	1			T2	2		T60	1		T66	3
valid_sources[0x30]	1508079	1			T60	1		T99	63		T93	11
valid_sources[0x31]	1499047	1			T1	8		T2	9		T3	2
valid_sources[0x32]	1485535	1			T2	7		T3	2		T60	1
valid_sources[0x33]	1487873	1			T2	1		T3	2		T60	3
valid_sources[0x34]	1527448	1			T2	21		T3	4		T60	1
valid_sources[0x35]	3545447	1			T1	25		T2	2		T3	1
valid_sources[0x36]	1494970	1			T1	26		T2	5		T59	1
valid_sources[0x37]	1482765	1			T1	36		T2	5		T3	1
valid_sources[0x38]	3525642	1			T1	17		T2	2		T3	1
valid_sources[0x39]	1488865	1			T2	7		T3	1		T60	1
valid_sources[0x3a]	1478650	1			T1	4		T2	7		T3	2
valid_sources[0x3b]	1495996	1			T2	5		T3	1		T60	1
valid_sources[0x3c]	1479713	1			T2	2		T3	2		T60	2
valid_sources[0x3d]	1492414	1			T1	2		T2	3		T3	3
valid_sources[0x3e]	1484606	1			T2	8		T3	3		T60	4
valid_sources[0x3f]	1492247	1			T1	19		T2	15		T62	3
valid_sources[0x40]	1491725	1			T2	6		T3	1		T58	1
valid_sources[0x41]	1499685	1			T2	5		T58	3		T90	7
valid_sources[0x42]	1498869	1			T1	2		T2	3		T3	1
valid_sources[0x43]	2318631	1			T2	11		T3	2		T59	1
valid_sources[0x44]	3003035	1			T1	7		T2	4		T3	2
valid_sources[0x45]	1485292	1			T1	3		T2	7		T60	3
valid_sources[0x46]	1487584	1			T2	4		T60	1		T99	75
valid_sources[0x47]	1669940	1			T2	5		T3	2		T60	1
valid_sources[0x48]	1486932	1			T2	1		T3	3		T60	3
valid_sources[0x49]	1531318	1			T2	1		T3	3		T60	2
valid_sources[0x4a]	1494109	1			T2	14		T60	1		T66	17
valid_sources[0x4b]	1479792	1			T2	1		T3	3		T58	10
valid_sources[0x4c]	1490953	1			T2	4		T3	1		T59	2
valid_sources[0x4d]	1489404	1			T1	5		T2	1		T3	4
valid_sources[0x4e]	1488982	1			T1	12		T2	5		T3	1
valid_sources[0x4f]	1496553	1			T2	1		T3	3		T59	3
valid_sources[0x50]	1707001	1			T1	24		T2	8		T3	1
valid_sources[0x51]	1474934	1			T1	4		T2	10		T3	1
valid_sources[0x52]	1489853	1			T2	3		T59	1		T62	1
valid_sources[0x53]	3907674	1			T2	8		T3	2		T60	2
valid_sources[0x54]	1481580	1			T2	3		T3	2		T60	2
valid_sources[0x55]	1573703	1			T1	28		T2	6		T3	2
valid_sources[0x56]	1501047	1			T1	11		T2	11		T3	1
valid_sources[0x57]	1492651	1			T2	2		T3	1		T60	4
valid_sources[0x58]	1616582	1			T2	5		T3	1		T58	1
valid_sources[0x59]	1526304	1			T2	8		T66	2		T99	82
valid_sources[0x5a]	1670372	1			T1	12		T2	9		T3	2
valid_sources[0x5b]	1490466	1			T1	11		T2	7		T3	5
valid_sources[0x5c]	1486836	1			T1	1		T3	3		T60	1
valid_sources[0x5d]	3558113	1			T2	1		T3	4		T58	2
valid_sources[0x5e]	2303290	1			T1	5		T2	5		T3	1
valid_sources[0x5f]	1480982	1			T2	3		T3	2		T59	2
valid_sources[0x60]	1502166	1			T1	32		T2	4		T3	3
valid_sources[0x61]	1487745	1			T2	12		T58	1		T60	1
valid_sources[0x62]	2147339	1			T2	5		T3	1		T58	7
valid_sources[0x63]	1498968	1			T2	3		T3	2		T60	2
valid_sources[0x64]	2324083	1			T1	8		T2	10		T3	1
valid_sources[0x65]	1630538	1			T1	16		T2	5		T3	1
valid_sources[0x66]	2355151	1			T1	5		T2	2		T60	3
valid_sources[0x67]	1475584	1			T3	1		T66	1		T99	16
valid_sources[0x68]	3533421	1			T2	4		T3	1		T59	1
valid_sources[0x69]	2028533	1			T1	60		T3	2		T59	1
valid_sources[0x6a]	1493006	1			T1	2		T2	4		T3	2
valid_sources[0x6b]	3414614	1			T2	1		T3	1		T59	1
valid_sources[0x6c]	1661536	1			T2	11		T60	3		T66	9
valid_sources[0x6d]	1486287	1			T2	4		T60	2		T90	5
valid_sources[0x6e]	3529443	1			T2	12		T58	4		T66	8
valid_sources[0x6f]	1490928	1			T2	9		T3	1		T66	8
valid_sources[0x70]	1485069	1			T2	4		T3	3		T59	1
valid_sources[0x71]	2421349	1			T3	1		T60	3		T66	10
valid_sources[0x72]	1481873	1			T2	5		T3	1		T66	5
valid_sources[0x73]	1484976	1			T58	1		T66	40		T99	74
valid_sources[0x74]	1498651	1			T2	4		T3	1		T58	2
valid_sources[0x75]	2421458	1			T2	10		T3	1		T60	3
valid_sources[0x76]	1490877	1			T2	11		T3	2		T58	1
valid_sources[0x77]	2548608	1			T1	15		T2	8		T3	1
valid_sources[0x78]	2341741	1			T2	5		T66	14		T99	83
valid_sources[0x79]	1958009	1			T2	3		T3	1		T66	2
valid_sources[0x7a]	3919003	1			T1	19		T60	1		T66	2
valid_sources[0x7b]	1493311	1			T1	23		T2	14		T3	2
valid_sources[0x7c]	1485321	1			T2	7		T60	2		T90	2
valid_sources[0x7d]	2136951	1			T2	5		T3	4		T60	1
valid_sources[0x7e]	1658014	1			T1	5		T2	5		T3	1
valid_sources[0x7f]	2411073	1			T2	5		T59	1		T60	1
valid_sources[0x80]	1484500	1			T3	1		T60	3		T66	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

91659819

1

T1

665

T2

384

T3

2

values[0x0]

all_enables

biggest_size

63985709

1

T1

303

T2

272

T3

14

values[0x1]

all_enables

biggest_size

55132692

1

T1

340

T2

291

T3

14