Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

271508129

1

T1

1

T2

422

T3

344

full_word

211271103

1

T1

1308

T2

947

T3

30

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	482778932	1			T1	1309		T2	1359		T3	374
auto[TlIntgErrCmd]	103	1			T2	1		T66	8		T122	3
auto[TlIntgErrData]	98	1			T2	6		T66	6		T122	3
auto[TlIntgErrBoth]	99	1			T2	3		T66	6		T122	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

251142733

1

T1

666

T2

764

T3

2

auto[1]

231636499

1

T1

643

T2

605

T3

372

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	159359175	1			T1	1		T2	375		T58	28
auto[TlIntgErrNone]	partial	auto[1]	112148675	1			T2	37		T3	344		T58	49
auto[TlIntgErrNone]	full_word	auto[0]	91783419	1			T1	665		T2	384		T3	2
auto[TlIntgErrNone]	full_word	auto[1]	119487663	1			T1	643		T2	563		T3	28
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T66	2		T122	1		T124	4
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T2	1		T66	5		T122	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T157	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T66	1		T158	1		-	-
auto[TlIntgErrData]	partial	auto[0]	42	1			T2	3		T66	4		T124	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T2	3		T66	2		T122	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T124	1		T127	1		T156	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T122	1		T123	1		T159	2
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T2	2		T66	1		T122	1
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T2	1		T66	5		T122	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T160	2		T161	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T122	1		T162	1		T160	1