Unified Coverage Report :: Module :: keccak_round

Module : keccak_round

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.45	71.25	100.00		26.67	79.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_keccak	78.11	71.25	100.00		40.00	79.31	100.00

---

Module Instance : tb.dut.u_sha3.u_keccak

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.11	71.25	100.00		40.00	79.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.17	85.98	88.24	100.00	40.00	78.79	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.09	97.30	81.25		100.00	91.89	100.00	u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak_p	81.25	100.00	75.00			50.00	100.00
u_prim_sec_anchor_buf	100.00	100.00
u_round_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
TOTAL		80	57	71.25
CONT_ASSIGN	134	0	0
ALWAYS	137	3	3	100.00
ALWAYS	143	53	31	58.49
CONT_ASSIGN	309	1	1	100.00
ALWAYS	327	6	6	100.00
CONT_ASSIGN	336	1	1	100.00
ALWAYS	344	7	7	100.00
ALWAYS	366	4	3	75.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	403	0	0
CONT_ASSIGN	404	0	0
ALWAYS	427	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134		unreachable
137	3	3
143	1	1
145	1	1
146	1	1
147	1	1
149	1	1
150	1	1
152	1	1
154	1	1
155	1	1
157	1	1
159	1	1
161	1	1
163	1	1
165	1	1
167	1	1
168	1	1
169	1	1
174	1	1
176	1	1
177	1	1
179		unreachable
180	1	1
182	1	1
184	1	1
190	1	1
192	1	1
193		unreachable
195		unreachable
196		unreachable
198	1	1
200	1	1
206	0	1
207	0	1
216	0	1
217	0	1
218	0	1
220		unreachable
226	0	1
227	0	1
230	0	1
233	0	1
239	0	1
246	0	1
247	0	1
250	0	1
253	0	1
255	0	1
257		unreachable
258		unreachable
264	0	1
265	0	1
268	0	1
270	0	1
271		unreachable
273		unreachable
274		unreachable
276	0	1
278	0	1
283	0	1
288	1	1
289	1	1
301	1	1
302	1	1
			MISSING_ELSE
309	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
			MISSING_ELSE
336	1	1
344	1	1
345	1	1
346	1	1
347	1	1
351	1	1
352	1	1
355	1	1
			MISSING_ELSE
366	1	1
368	1	1
370	1	1
372	0	1
			MISSING_ELSE
			MISSING_ELSE
377	1	1
401	1	1
403		unreachable
404		unreachable
427	1	1
428	1	1
430	1	1

---

Cond Coverage for Module : keccak_round

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (int'(round) == (MaxRound - 1))
            ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Unreachable	T4,T5,T6

 LINE       180
 EXPRESSION (((!EnMasking)) && run_i)
             -------1------    --2--

-1-	-2-	Status	Tests
-	0	Covered	T4,T5,T6
-	1	Covered	T4,T5,T6

 LINE       216
 EXPRESSION (rand_early_i || rand_valid_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       309
 EXPRESSION ((keccak_st == KeccakStIdle) ? 1'b1 : 1'b0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       309
 SUB-EXPRESSION (keccak_st == KeccakStIdle)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       351
 EXPRESSION (addr_i == i[(DInAddr - 1):0])
            ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Module : keccak_round

Summary for FSM :: keccak_st

	Total	Covered	Percent
States	8	3	37.50	(Not included in score)
Transitions	15	4	26.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: keccak_st

---

states	Line No.	Covered	Tests
KeccakStActive	182	Covered	T1
KeccakStError	283	Not Covered
KeccakStIdle	165	Covered	T1
KeccakStPhase1	179	Not Covered
KeccakStPhase2Cycle1	217	Not Covered
KeccakStPhase2Cycle2	233	Not Covered
KeccakStPhase2Cycle3	255	Not Covered
KeccakStTerminalError	302	Covered	T1

transitions	Line No.	Covered	Tests
KeccakStActive->KeccakStIdle	193	Covered	T1
KeccakStActive->KeccakStTerminalError	302	Covered	T1
KeccakStError->KeccakStTerminalError	302	Not Covered
KeccakStIdle->KeccakStActive	182	Covered	T1
KeccakStIdle->KeccakStPhase1	179	Not Covered
KeccakStIdle->KeccakStTerminalError	302	Covered	T1
KeccakStPhase1->KeccakStPhase2Cycle1	217	Not Covered
KeccakStPhase1->KeccakStTerminalError	302	Not Covered
KeccakStPhase2Cycle1->KeccakStPhase2Cycle2	233	Not Covered
KeccakStPhase2Cycle1->KeccakStTerminalError	302	Not Covered
KeccakStPhase2Cycle2->KeccakStPhase2Cycle3	255	Not Covered
KeccakStPhase2Cycle2->KeccakStTerminalError	302	Not Covered
KeccakStPhase2Cycle3->KeccakStIdle	271	Not Covered
KeccakStPhase2Cycle3->KeccakStPhase1	276	Not Covered
KeccakStPhase2Cycle3->KeccakStTerminalError	302	Not Covered

---

Branch Coverage for Module : keccak_round

	Line No.	Total	Covered	Percent
Branches		29	23	79.31
TERNARY	309	2	2	100.00
IF	137	2	2	100.00
CASE	161	12	7	58.33
IF	301	2	2	100.00
IF	327	4	4	100.00
IF	345	2	2	100.00
IF	368	3	2	66.67
IF	427	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	309	((keccak_st == KeccakStIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	137	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	161	case (keccak_st)
-2-:	163	if (valid_i)
-3-:	169	if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))
-4-:	177	if ((EnMasking && run_i))
-5-:	180	if (((!EnMasking) && run_i))
-6-:	192	if (rnd_eq_end)
-7-:	216	if ((rand_early_i || rand_valid_i))
-8-:	246	if (rand_valid_i)
-9-:	270	if (rnd_eq_end)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KeccakStIdle	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
KeccakStIdle	0	1	-	-	-	-	-	-	Covered	T4,T5,T6
KeccakStIdle	0	0	1	-	-	-	-	-	Unreachable
KeccakStIdle	0	0	0	1	-	-	-	-	Covered	T4,T5,T6
KeccakStIdle	0	0	0	0	-	-	-	-	Covered	T4,T5,T6
KeccakStActive	-	-	-	-	1	-	-	-	Unreachable	T4,T5,T6
KeccakStActive	-	-	-	-	0	-	-	-	Covered	T4,T5,T6
KeccakStPhase1	-	-	-	-	-	1	-	-	Not Covered
KeccakStPhase1	-	-	-	-	-	0	-	-	Unreachable
KeccakStPhase2Cycle1	-	-	-	-	-	-	-	-	Not Covered
KeccakStPhase2Cycle2	-	-	-	-	-	-	1	-	Not Covered
KeccakStPhase2Cycle2	-	-	-	-	-	-	0	-	Unreachable
KeccakStPhase2Cycle3	-	-	-	-	-	-	-	1	Unreachable
KeccakStPhase2Cycle3	-	-	-	-	-	-	-	0	Not Covered
KeccakStError	-	-	-	-	-	-	-	-	Not Covered
KeccakStTerminalError	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	301	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	327	if ((!rst_n))
-2-:	329	if (rst_storage)
-3-:	331	if (update_storage)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	345	if (xor_message)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	368	if (rst_storage)
-2-:	370	if (((keccak_st != KeccakStIdle) || prim_mubi_pkg::mubi4_test_false_loose(clear_i)))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T4,T5,T6
0	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	427	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : keccak_round

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClearAssertStIdle_A	2147483647	354986	0	0
OneHot0ValidAndRun_A	2147483647	2147483647	0	0
ValidRunAssertStIdle_A	2147483647	58940339	0	0
WidthDivisableByDInWidth_A	1060	1060	0	0
gen_unmask_st_chk.UnmaskValidStates_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ClearAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	354986	0	0
T4	191736	390	0	0
T5	528307	63	0	0
T6	311444	84	0	0
T7	3044	0	0	0
T13	177128	374	0	0
T14	962806	246	0	0
T15	137468	310	0	0
T16	551569	127	0	0
T17	181884	18	0	0
T18	5846	9	0	0
T19	0	80	0	0

OneHot0ValidAndRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

ValidRunAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	58940339	0	0
T4	191736	105298	0	0
T5	528307	19702	0	0
T6	311444	8223	0	0
T7	3044	1	0	0
T13	177128	99468	0	0
T14	962806	54270	0	0
T15	137468	76468	0	0
T16	551569	92701	0	0
T17	181884	1464	0	0
T18	5846	638	0	0

WidthDivisableByDInWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_unmask_st_chk.UnmaskValidStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

Line Coverage for Instance : tb.dut.u_sha3.u_keccak

	Line No.	Total	Covered	Percent
TOTAL		80	57	71.25
CONT_ASSIGN	134	0	0
ALWAYS	137	3	3	100.00
ALWAYS	143	53	31	58.49
CONT_ASSIGN	309	1	1	100.00
ALWAYS	327	6	6	100.00
CONT_ASSIGN	336	1	1	100.00
ALWAYS	344	7	7	100.00
ALWAYS	366	4	3	75.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	403	0	0
CONT_ASSIGN	404	0	0
ALWAYS	427	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
134		unreachable
137	3	3
143	1	1
145	1	1
146	1	1
147	1	1
149	1	1
150	1	1
152	1	1
154	1	1
155	1	1
157	1	1
159	1	1
161	1	1
163	1	1
165	1	1
167	1	1
168	1	1
169	1	1
174	1	1
176	1	1
177	1	1
179		unreachable
180	1	1
182	1	1
184	1	1
190	1	1
192	1	1
193		unreachable
195		unreachable
196		unreachable
198	1	1
200	1	1
206	0	1
207	0	1
216	0	1
217	0	1
218	0	1
220		unreachable
226	0	1
227	0	1
230	0	1
233	0	1
239	0	1
246	0	1
247	0	1
250	0	1
253	0	1
255	0	1
257		unreachable
258		unreachable
264	0	1
265	0	1
268	0	1
270	0	1
271		unreachable
273		unreachable
274		unreachable
276	0	1
278	0	1
283	0	1
288	1	1
289	1	1
301	1	1
302	1	1
			MISSING_ELSE
309	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
			MISSING_ELSE
336	1	1
344	1	1
345	1	1
346	1	1
347	1	1
351	1	1
352	1	1
355	1	1
			MISSING_ELSE
366	1	1
368	1	1
370	1	1
372	0	1
			MISSING_ELSE
			MISSING_ELSE
377	1	1
401	1	1
403		unreachable
404		unreachable
427	1	1
428	1	1
430	1	1

---

Cond Coverage for Instance : tb.dut.u_sha3.u_keccak

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (int'(round) == (MaxRound - 1))
            ---------------1---------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Unreachable	T4,T5,T6

 LINE       180
 EXPRESSION (((!EnMasking)) && run_i)
             -------1------    --2--

-1-	-2-	Status	Tests
-	0	Covered	T4,T5,T6
-	1	Covered	T4,T5,T6

 LINE       216
 EXPRESSION (rand_early_i || rand_valid_i)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       309
 EXPRESSION ((keccak_st == KeccakStIdle) ? 1'b1 : 1'b0)
             -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       309
 SUB-EXPRESSION (keccak_st == KeccakStIdle)
                -------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       351
 EXPRESSION (addr_i == i[(DInAddr - 1):0])
            ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

FSM Coverage for Instance : tb.dut.u_sha3.u_keccak

Summary for FSM :: keccak_st

	Total	Covered	Percent
States	8	3	37.50	(Not included in score)
Transitions	10	4	40.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: keccak_st

---

states	Line No.	Covered	Tests
KeccakStActive	182	Covered	T1
KeccakStError	283	Excluded
KeccakStIdle	165	Covered	T1
KeccakStPhase1	179	Not Covered
KeccakStPhase2Cycle1	217	Not Covered
KeccakStPhase2Cycle2	233	Not Covered
KeccakStPhase2Cycle3	255	Not Covered
KeccakStTerminalError	302	Covered	T1

transitions	Line No.	Covered	Tests	Exclude Annotation
KeccakStActive->KeccakStIdle	193	Covered	T1
KeccakStActive->KeccakStTerminalError	302	Covered	T1
KeccakStError->KeccakStTerminalError	302	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
KeccakStIdle->KeccakStActive	182	Covered	T1
KeccakStIdle->KeccakStPhase1	179	Not Covered
KeccakStIdle->KeccakStTerminalError	302	Covered	T1
KeccakStPhase1->KeccakStPhase2Cycle1	217	Not Covered
KeccakStPhase1->KeccakStTerminalError	302	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
KeccakStPhase2Cycle1->KeccakStPhase2Cycle2	233	Not Covered
KeccakStPhase2Cycle1->KeccakStTerminalError	302	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
KeccakStPhase2Cycle2->KeccakStPhase2Cycle3	255	Not Covered
KeccakStPhase2Cycle2->KeccakStTerminalError	302	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
KeccakStPhase2Cycle3->KeccakStIdle	271	Not Covered
KeccakStPhase2Cycle3->KeccakStPhase1	276	Not Covered
KeccakStPhase2Cycle3->KeccakStTerminalError	302	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.

---

Branch Coverage for Instance : tb.dut.u_sha3.u_keccak

	Line No.	Total	Covered	Percent
Branches		29	23	79.31
TERNARY	309	2	2	100.00
IF	137	2	2	100.00
CASE	161	12	7	58.33
IF	301	2	2	100.00
IF	327	4	4	100.00
IF	345	2	2	100.00
IF	368	3	2	66.67
IF	427	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/keccak_round.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	309	((keccak_st == KeccakStIdle)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	137	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	161	case (keccak_st)
-2-:	163	if (valid_i)
-3-:	169	if (prim_mubi_pkg::mubi4_test_true_strict(clear_i))
-4-:	177	if ((EnMasking && run_i))
-5-:	180	if (((!EnMasking) && run_i))
-6-:	192	if (rnd_eq_end)
-7-:	216	if ((rand_early_i || rand_valid_i))
-8-:	246	if (rand_valid_i)
-9-:	270	if (rnd_eq_end)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KeccakStIdle	1	-	-	-	-	-	-	-	Covered	T4,T5,T6
KeccakStIdle	0	1	-	-	-	-	-	-	Covered	T4,T5,T6
KeccakStIdle	0	0	1	-	-	-	-	-	Unreachable
KeccakStIdle	0	0	0	1	-	-	-	-	Covered	T4,T5,T6
KeccakStIdle	0	0	0	0	-	-	-	-	Covered	T4,T5,T6
KeccakStActive	-	-	-	-	1	-	-	-	Unreachable	T4,T5,T6
KeccakStActive	-	-	-	-	0	-	-	-	Covered	T4,T5,T6
KeccakStPhase1	-	-	-	-	-	1	-	-	Not Covered
KeccakStPhase1	-	-	-	-	-	0	-	-	Unreachable
KeccakStPhase2Cycle1	-	-	-	-	-	-	-	-	Not Covered
KeccakStPhase2Cycle2	-	-	-	-	-	-	1	-	Not Covered
KeccakStPhase2Cycle2	-	-	-	-	-	-	0	-	Unreachable
KeccakStPhase2Cycle3	-	-	-	-	-	-	-	1	Unreachable
KeccakStPhase2Cycle3	-	-	-	-	-	-	-	0	Not Covered
KeccakStError	-	-	-	-	-	-	-	-	Not Covered
KeccakStTerminalError	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	301	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	327	if ((!rst_n))
-2-:	329	if (rst_storage)
-3-:	331	if (update_storage)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	345	if (xor_message)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	368	if (rst_storage)
-2-:	370	if (((keccak_st != KeccakStIdle) || prim_mubi_pkg::mubi4_test_false_loose(clear_i)))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Covered	T4,T5,T6
0	-	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	427	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sha3.u_keccak

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ClearAssertStIdle_A	2147483647	354986	0	0
OneHot0ValidAndRun_A	2147483647	2147483647	0	0
ValidRunAssertStIdle_A	2147483647	58940339	0	0
WidthDivisableByDInWidth_A	1060	1060	0	0
gen_unmask_st_chk.UnmaskValidStates_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ClearAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	354986	0	0
T4	191736	390	0	0
T5	528307	63	0	0
T6	311444	84	0	0
T7	3044	0	0	0
T13	177128	374	0	0
T14	962806	246	0	0
T15	137468	310	0	0
T16	551569	127	0	0
T17	181884	18	0	0
T18	5846	9	0	0
T19	0	80	0	0

OneHot0ValidAndRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

ValidRunAssertStIdle_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	58940339	0	0
T4	191736	105298	0	0
T5	528307	19702	0	0
T6	311444	8223	0	0
T7	3044	1	0	0
T13	177128	99468	0	0
T14	962806	54270	0	0
T15	137468	76468	0	0
T16	551569	92701	0	0
T17	181884	1464	0	0
T18	5846	638	0	0

WidthDivisableByDInWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1060	1060	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

gen_unmask_st_chk.UnmaskValidStates_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	191736	191727	0	0
T5	528307	528167	0	0
T6	311444	311195	0	0
T7	3044	2917	0	0
T13	177128	177119	0	0
T14	962806	962751	0	0
T15	137468	137458	0	0
T16	551569	551483	0	0
T17	181884	181765	0	0
T18	5846	5795	0	0