Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	120973740	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120973740	0	0
T3	3960	648	0	0
T58	1698	51	0	0
T59	4139	189	0	0
T60	3704	0	0	0
T61	1529	0	0	0
T62	1488	0	0	0
T63	1361	0	0	0
T66	32525	0	0	0
T90	6627	0	0	0
T91	918	0	0	0
T92	0	721	0	0
T93	0	312	0	0
T94	0	675	0	0
T95	0	436	0	0
T96	0	203	0	0
T100	0	242	0	0
T101	0	278	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	226192476	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	226192476	0	0
T3	3960	1100	0	0
T58	1698	51	0	0
T59	4139	494	0	0
T60	3704	0	0	0
T61	1529	0	0	0
T62	1488	0	0	0
T63	1361	0	0	0
T66	32525	0	0	0
T90	6627	0	0	0
T91	918	0	0	0
T92	0	404	0	0
T93	0	277	0	0
T94	0	2378	0	0
T95	0	1481	0	0
T96	0	421	0	0
T100	0	148	0	0
T101	0	262	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	328823868	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	328823868	0	0
T1	9014	1407	0	0
T2	5367	2663	0	0
T3	3960	3	0	0
T58	1698	104	0	0
T59	4139	374	0	0
T60	3704	324	0	0
T61	1529	267	0	0
T62	1488	22	0	0
T90	6627	1220	0	0
T91	918	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	630395897	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1274	1274	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	630395897	0	0
T1	9014	1309	0	0
T2	5367	1369	0	0
T3	3960	7	0	0
T58	1698	94	0	0
T59	4139	885	0	0
T60	3704	305	0	0
T61	1529	149	0	0
T62	1488	97	0	0
T90	6627	2212	0	0
T91	918	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9014	8865	0	0
T2	5367	4465	0	0
T3	3960	3870	0	0
T58	1698	1639	0	0
T59	4139	4064	0	0
T60	3704	3324	0	0
T61	1529	1317	0	0
T62	1488	1423	0	0
T90	6627	6568	0	0
T91	918	826	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1274	1274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0