Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	208434711	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

167093928

1

T1

12

T2

15

T3

1021

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	197601020	1			T1	19		T2	20		T3	772
values[0x0]	85314176	1			T1	11		T2	11		T3	299
values[0x1]	92613443	1			T1	8		T2	9		T3	252

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	162205750	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

213322889

1

T1

13

T2

19

T3

1096

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1139612	1			T3	3		T55	3		T61	2
valid_sources[0x01]	2928379	1			T3	3		T55	1		T61	1
valid_sources[0x02]	1134859	1			T3	7		T55	2		T61	3
valid_sources[0x03]	1138914	1			T3	5		T55	1		T61	4
valid_sources[0x04]	1138758	1			T3	5		T55	2		T61	3
valid_sources[0x05]	1826340	1			T3	7		T55	2		T61	2
valid_sources[0x06]	1264664	1			T3	9		T61	3		T84	5
valid_sources[0x07]	2240689	1			T3	7		T55	1		T61	3
valid_sources[0x08]	1127676	1			T3	4		T55	2		T63	1
valid_sources[0x09]	1158600	1			T3	9		T61	4		T60	2
valid_sources[0x0a]	1129617	1			T3	3		T61	1		T60	2
valid_sources[0x0b]	1155693	1			T3	7		T61	1		T60	2
valid_sources[0x0c]	1132789	1			T3	4		T61	1		T58	33
valid_sources[0x0d]	1591829	1			T3	5		T63	1		T60	2
valid_sources[0x0e]	1138372	1			T2	1		T3	4		T55	1
valid_sources[0x0f]	1130381	1			T3	4		T61	2		T60	1
valid_sources[0x10]	3551258	1			T1	1		T3	4		T61	6
valid_sources[0x11]	1126309	1			T3	6		T55	1		T61	1
valid_sources[0x12]	1310977	1			T1	1		T3	5		T55	1
valid_sources[0x13]	1130478	1			T3	8		T61	2		T60	2
valid_sources[0x14]	1254202	1			T3	6		T60	1		T59	25
valid_sources[0x15]	1135428	1			T1	4		T3	6		T55	4
valid_sources[0x16]	1143484	1			T3	5		T55	1		T61	3
valid_sources[0x17]	1160321	1			T3	7		T55	3		T61	10
valid_sources[0x18]	3559966	1			T3	4		T55	1		T57	3
valid_sources[0x19]	1168077	1			T1	1		T3	6		T55	1
valid_sources[0x1a]	1128334	1			T2	1		T3	4		T55	1
valid_sources[0x1b]	1129327	1			T3	6		T61	4		T84	5
valid_sources[0x1c]	1218943	1			T3	11		T60	1		T84	1
valid_sources[0x1d]	1139721	1			T3	2		T55	1		T63	2
valid_sources[0x1e]	2022868	1			T3	7		T55	2		T63	1
valid_sources[0x1f]	2105033	1			T1	3		T2	1		T3	4
valid_sources[0x20]	1134587	1			T3	1		T84	10		T87	1
valid_sources[0x21]	3546128	1			T3	1		T55	1		T61	1
valid_sources[0x22]	1134203	1			T3	8		T60	1		T83	1
valid_sources[0x23]	1276616	1			T3	6		T55	1		T61	1
valid_sources[0x24]	1997977	1			T3	12		T55	2		T61	1
valid_sources[0x25]	1130742	1			T3	9		T63	1		T60	2
valid_sources[0x26]	1604291	1			T3	5		T55	1		T61	4
valid_sources[0x27]	1788671	1			T2	4		T3	9		T55	1
valid_sources[0x28]	1137098	1			T3	5		T55	1		T84	6
valid_sources[0x29]	1145537	1			T1	1		T3	5		T84	8
valid_sources[0x2a]	1378678	1			T3	4		T55	1		T61	5
valid_sources[0x2b]	1305359	1			T3	7		T55	1		T56	110
valid_sources[0x2c]	1126972	1			T3	4		T61	1		T60	2
valid_sources[0x2d]	1132861	1			T3	4		T55	1		T83	1
valid_sources[0x2e]	1138550	1			T3	5		T61	3		T83	2
valid_sources[0x2f]	1132591	1			T3	4		T55	1		T60	3
valid_sources[0x30]	1125051	1			T3	11		T55	1		T56	84
valid_sources[0x31]	1136084	1			T3	2		T55	2		T61	3
valid_sources[0x32]	1138100	1			T3	2		T55	2		T61	5
valid_sources[0x33]	1127684	1			T3	5		T55	1		T61	4
valid_sources[0x34]	3148543	1			T3	8		T61	1		T59	28
valid_sources[0x35]	1161720	1			T3	3		T63	1		T61	3
valid_sources[0x36]	1137637	1			T2	2		T3	3		T55	1
valid_sources[0x37]	1236733	1			T61	5		T84	6		T80	6
valid_sources[0x38]	4229477	1			T55	2		T61	3		T60	1
valid_sources[0x39]	1174813	1			T2	2		T3	2		T61	5
valid_sources[0x3a]	1129297	1			T3	7		T61	4		T60	1
valid_sources[0x3b]	1133645	1			T2	2		T3	10		T61	2
valid_sources[0x3c]	1133326	1			T1	2		T3	8		T55	4
valid_sources[0x3d]	1134566	1			T55	1		T84	10		T86	256
valid_sources[0x3e]	1126566	1			T63	1		T61	7		T59	2
valid_sources[0x3f]	1142563	1			T55	1		T61	2		T60	1
valid_sources[0x40]	3195977	1			T3	7		T55	1		T61	1
valid_sources[0x41]	1139987	1			T3	3		T55	2		T63	1
valid_sources[0x42]	2018431	1			T3	6		T55	2		T61	8
valid_sources[0x43]	1132253	1			T3	9		T55	1		T60	2
valid_sources[0x44]	1124698	1			T3	4		T55	2		T61	2
valid_sources[0x45]	1134239	1			T3	9		T55	1		T60	3
valid_sources[0x46]	2943589	1			T3	3		T55	1		T61	6
valid_sources[0x47]	1139821	1			T2	2		T55	1		T83	5
valid_sources[0x48]	1134880	1			T3	5		T61	1		T84	6
valid_sources[0x49]	1140991	1			T3	3		T84	14		T78	2
valid_sources[0x4a]	1398915	1			T3	6		T55	1		T61	3
valid_sources[0x4b]	1136195	1			T3	7		T55	1		T61	1
valid_sources[0x4c]	1806795	1			T3	8		T61	6		T84	5
valid_sources[0x4d]	1123244	1			T3	6		T61	2		T84	7
valid_sources[0x4e]	1273294	1			T3	4		T55	2		T61	8
valid_sources[0x4f]	1139830	1			T3	8		T55	2		T61	1
valid_sources[0x50]	2040521	1			T3	4		T60	1		T84	1
valid_sources[0x51]	1135887	1			T3	3		T55	1		T61	7
valid_sources[0x52]	3559706	1			T3	7		T60	1		T84	5
valid_sources[0x53]	1137130	1			T3	9		T55	1		T61	2
valid_sources[0x54]	1144939	1			T3	7		T55	1		T61	1
valid_sources[0x55]	1132842	1			T3	9		T55	2		T61	2
valid_sources[0x56]	2009673	1			T3	6		T55	1		T61	3
valid_sources[0x57]	2021473	1			T1	2		T3	5		T55	1
valid_sources[0x58]	1233507	1			T3	2		T59	4		T124	67
valid_sources[0x59]	1137969	1			T3	5		T61	1		T84	6
valid_sources[0x5a]	1126673	1			T61	9		T84	12		T80	1
valid_sources[0x5b]	1154249	1			T3	3		T55	2		T61	6
valid_sources[0x5c]	1136458	1			T3	2		T56	120		T61	5
valid_sources[0x5d]	1782378	1			T3	1		T55	2		T61	7
valid_sources[0x5e]	3546327	1			T3	7		T55	2		T63	1
valid_sources[0x5f]	1128479	1			T3	9		T55	1		T61	2
valid_sources[0x60]	1122767	1			T3	10		T60	3		T84	5
valid_sources[0x61]	1143658	1			T3	8		T61	9		T60	1
valid_sources[0x62]	1526240	1			T2	1		T3	11		T61	4
valid_sources[0x63]	1130109	1			T1	2		T3	4		T55	1
valid_sources[0x64]	1134083	1			T3	8		T55	2		T59	78
valid_sources[0x65]	1208059	1			T3	5		T61	4		T60	1
valid_sources[0x66]	1310226	1			T3	9		T55	1		T61	4
valid_sources[0x67]	1129629	1			T3	4		T55	1		T61	2
valid_sources[0x68]	1133114	1			T3	12		T61	4		T83	1
valid_sources[0x69]	2534446	1			T3	5		T55	1		T61	3
valid_sources[0x6a]	1148713	1			T1	1		T3	1		T55	1
valid_sources[0x6b]	1127918	1			T2	1		T3	4		T60	2
valid_sources[0x6c]	1136369	1			T2	1		T3	5		T55	1
valid_sources[0x6d]	1125691	1			T3	2		T63	1		T61	4
valid_sources[0x6e]	1131708	1			T3	1		T55	2		T61	1
valid_sources[0x6f]	1129701	1			T3	3		T55	1		T60	1
valid_sources[0x70]	1129661	1			T3	7		T63	1		T61	11
valid_sources[0x71]	1129604	1			T1	2		T3	6		T55	2
valid_sources[0x72]	1140888	1			T3	6		T55	1		T61	4
valid_sources[0x73]	1130306	1			T3	7		T61	2		T60	2
valid_sources[0x74]	1130307	1			T3	13		T55	3		T61	8
valid_sources[0x75]	1131648	1			T3	2		T61	8		T60	1
valid_sources[0x76]	2019868	1			T2	1		T3	1		T60	1
valid_sources[0x77]	1132206	1			T3	4		T59	47		T84	2
valid_sources[0x78]	1543130	1			T2	2		T3	6		T63	1
valid_sources[0x79]	2164833	1			T3	1		T55	1		T56	54
valid_sources[0x7a]	1140114	1			T3	3		T55	1		T61	5
valid_sources[0x7b]	1133324	1			T3	1		T55	1		T61	1
valid_sources[0x7c]	1141780	1			T3	4		T55	1		T84	5
valid_sources[0x7d]	3554258	1			T3	9		T60	3		T84	9
valid_sources[0x7e]	1144522	1			T3	4		T82	5		T83	1
valid_sources[0x7f]	1132778	1			T1	2		T3	2		T55	1
valid_sources[0x80]	1129352	1			T3	5		T55	1		T84	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72862455

1

T1

7

T2

11

T3

489

values[0x0]

all_enables

biggest_size

50618472

1

T1

3

T2

4

T3

288

values[0x1]

all_enables

biggest_size

43613001

1

T1

2

T3

244

T55

12