Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

216034811

1

T1

26

T2

25

T3

302

full_word

167565084

1

T1

12

T2

15

T3

1021

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	383599645	1			T1	38		T2	40		T3	1323
auto[TlIntgErrCmd]	86	1			T59	2		T84	4		T105	4
auto[TlIntgErrData]	72	1			T59	1		T84	3		T105	3
auto[TlIntgErrBoth]	92	1			T59	7		T84	3		T105	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

199045282

1

T1

19

T2

20

T3

772

auto[1]

184554613

1

T1

19

T2

20

T3

551

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	126064836	1			T1	12		T2	9		T3	283
auto[TlIntgErrNone]	partial	auto[1]	89969754	1			T1	14		T2	16		T3	19
auto[TlIntgErrNone]	full_word	auto[0]	72980336	1			T1	7		T2	11		T3	489
auto[TlIntgErrNone]	full_word	auto[1]	94584719	1			T1	5		T2	4		T3	532
auto[TlIntgErrCmd]	partial	auto[0]	26	1			T59	2		T84	1		T105	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T84	2		T105	3		T106	7
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T156	1		T157	1		T158	3
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T84	1		T106	1		T152	1
auto[TlIntgErrData]	partial	auto[0]	33	1			T59	1		T84	1		T105	3
auto[TlIntgErrData]	partial	auto[1]	26	1			T84	2		T106	1		T155	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T106	1		T160	1		T161	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T106	1		T155	1		T152	2
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T59	2		T84	1		T105	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T59	4		T84	2		T105	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T59	1		T152	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T106	1		T153	1		T119	1