Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	95473262	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1031	1031	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	95473262	0	0
T4	0	263	0	0
T5	0	5176	0	0
T6	0	255	0	0
T7	0	60	0	0
T55	2200	277	0	0
T56	4686	0	0	0
T57	1066	0	0	0
T58	8558	215	0	0
T59	4713	0	0	0
T60	3213	0	0	0
T61	2753	0	0	0
T63	1054	0	0	0
T78	0	287	0	0
T79	0	1	0	0
T80	0	205	0	0
T81	0	86	0	0
T82	896	0	0	0
T83	1586	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	159982235	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1031	1031	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	159982235	0	0
T4	0	263	0	0
T5	0	5176	0	0
T6	0	255	0	0
T7	0	124	0	0
T13	0	250	0	0
T55	2200	142	0	0
T56	4686	0	0	0
T57	1066	0	0	0
T58	8558	215	0	0
T59	4713	0	0	0
T60	3213	0	0	0
T61	2753	0	0	0
T63	1054	0	0	0
T78	0	207	0	0
T80	0	164	0	0
T81	0	86	0	0
T82	896	0	0	0
T83	1586	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	260206523	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1031	1031	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	260206523	0	0
T1	1045	38	0	0
T2	2047	40	0	0
T3	4588	2579	0	0
T55	2200	135	0	0
T56	4686	2932	0	0
T57	1066	22	0	0
T58	8558	857	0	0
T60	3213	471	0	0
T61	2753	1487	0	0
T63	1054	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	442662017	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	1031	1031	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	442662017	0	0
T1	1045	175	0	0
T2	2047	197	0	0
T3	4588	1323	0	0
T55	2200	73	0	0
T56	4686	1361	0	0
T57	1066	22	0	0
T58	8558	818	0	0
T60	3213	1040	0	0
T61	2753	679	0	0
T63	1054	22	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1045	991	0	0
T2	2047	1973	0	0
T3	4588	4177	0	0
T55	2200	2098	0	0
T56	4686	4257	0	0
T57	1066	998	0	0
T58	8558	8475	0	0
T60	3213	2875	0	0
T61	2753	2426	0	0
T63	1054	967	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0