Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1695644	0	0
entropy_period_rd_A	2147483647	1995	0	0
intr_enable_rd_A	2147483647	2587	0	0
prefix_0_rd_A	2147483647	1978	0	0
prefix_10_rd_A	2147483647	1824	0	0
prefix_1_rd_A	2147483647	2028	0	0
prefix_2_rd_A	2147483647	2002	0	0
prefix_3_rd_A	2147483647	1943	0	0
prefix_4_rd_A	2147483647	1768	0	0
prefix_5_rd_A	2147483647	2035	0	0
prefix_6_rd_A	2147483647	1755	0	0
prefix_7_rd_A	2147483647	1989	0	0
prefix_8_rd_A	2147483647	1815	0	0
prefix_9_rd_A	2147483647	1835	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1695644	0	0
T36	0	33618	0	0
T37	0	74226	0	0
T58	8558	244	0	0
T59	4713	2	0	0
T60	3213	0	0	0
T78	2596	60	0	0
T80	0	115	0	0
T81	0	28	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	1	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T105	0	1	0	0
T106	0	3	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1995	0	0
T59	4713	0	0	0
T60	3213	10	0	0
T75	0	113	0	0
T78	2596	0	0	0
T79	0	4	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	24	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	131	0	0
T126	0	78	0	0
T127	0	164	0	0
T128	0	222	0	0
T129	0	29	0	0
T130	0	6	0	0
T131	1145	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2587	0	0
T1	1045	22	0	0
T2	2047	10	0	0
T3	4588	0	0	0
T55	2200	0	0	0
T56	4686	0	0	0
T57	1066	0	0	0
T58	8558	0	0	0
T60	3213	7	0	0
T61	2753	0	0	0
T63	1054	0	0	0
T75	0	68	0	0
T84	0	35	0	0
T106	0	132	0	0
T126	0	54	0	0
T127	0	159	0	0
T128	0	157	0	0
T132	0	21	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1978	0	0
T59	4713	0	0	0
T60	3213	12	0	0
T75	0	66	0	0
T78	2596	0	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	26	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	83	0	0
T110	0	9	0	0
T126	0	52	0	0
T127	0	158	0	0
T128	0	210	0	0
T129	0	66	0	0
T131	1145	0	0	0
T133	0	2	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1824	0	0
T59	4713	0	0	0
T60	3213	15	0	0
T75	0	58	0	0
T78	2596	0	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	15	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T97	0	54	0	0
T106	0	64	0	0
T126	0	32	0	0
T127	0	175	0	0
T128	0	189	0	0
T129	0	48	0	0
T130	0	5	0	0
T131	1145	0	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2028	0	0
T59	4713	0	0	0
T60	3213	18	0	0
T75	0	62	0	0
T78	2596	0	0	0
T79	0	2	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	27	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	78	0	0
T110	0	1	0	0
T126	0	78	0	0
T127	0	190	0	0
T128	0	197	0	0
T129	0	43	0	0
T131	1145	0	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2002	0	0
T59	4713	0	0	0
T60	3213	11	0	0
T75	0	92	0	0
T78	2596	0	0	0
T79	0	5	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	31	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	60	0	0
T126	0	83	0	0
T127	0	176	0	0
T128	0	161	0	0
T129	0	51	0	0
T130	0	9	0	0
T131	1145	0	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1943	0	0
T59	4713	0	0	0
T60	3213	5	0	0
T75	0	96	0	0
T78	2596	0	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	20	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	56	0	0
T110	0	9	0	0
T126	0	64	0	0
T127	0	157	0	0
T128	0	178	0	0
T129	0	38	0	0
T131	1145	0	0	0
T133	0	5	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1768	0	0
T59	4713	0	0	0
T60	3213	6	0	0
T75	0	70	0	0
T78	2596	0	0	0
T79	0	6	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	19	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	79	0	0
T126	0	74	0	0
T127	0	167	0	0
T128	0	92	0	0
T129	0	31	0	0
T131	1145	0	0	0
T133	0	9	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2035	0	0
T59	4713	0	0	0
T60	3213	9	0	0
T75	0	97	0	0
T78	2596	0	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	19	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	86	0	0
T126	0	70	0	0
T127	0	182	0	0
T128	0	193	0	0
T129	0	66	0	0
T130	0	15	0	0
T131	1145	0	0	0
T134	0	3	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1755	0	0
T59	4713	0	0	0
T60	3213	13	0	0
T75	0	99	0	0
T78	2596	0	0	0
T79	0	1	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	26	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	55	0	0
T126	0	34	0	0
T127	0	88	0	0
T128	0	160	0	0
T129	0	56	0	0
T130	0	10	0	0
T131	1145	0	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1989	0	0
T59	4713	0	0	0
T60	3213	21	0	0
T75	0	90	0	0
T78	2596	0	0	0
T79	0	7	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	21	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	85	0	0
T126	0	56	0	0
T127	0	131	0	0
T128	0	188	0	0
T129	0	36	0	0
T130	0	6	0	0
T131	1145	0	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1815	0	0
T59	4713	0	0	0
T60	3213	5	0	0
T75	0	77	0	0
T78	2596	0	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	5	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	69	0	0
T126	0	62	0	0
T127	0	150	0	0
T128	0	152	0	0
T129	0	36	0	0
T130	0	11	0	0
T131	1145	0	0	0
T133	0	6	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1835	0	0
T59	4713	0	0	0
T60	3213	18	0	0
T75	0	105	0	0
T78	2596	0	0	0
T79	0	6	0	0
T82	896	0	0	0
T83	1586	0	0	0
T84	12976	23	0	0
T85	1554	0	0	0
T86	30425	0	0	0
T87	1406	0	0	0
T106	0	96	0	0
T126	0	57	0	0
T127	0	141	0	0
T128	0	150	0	0
T129	0	51	0	0
T131	1145	0	0	0
T133	0	1	0	0