Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	343	1			T3	5		T7	5		T8	8
all_values[1]	343	1			T3	5		T7	5		T8	8
all_values[2]	343	1			T3	5		T7	5		T8	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

552

1

T3

3

T7

14

T8

10

auto[1]

477

1

T3

12

T7

1

T8

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

594

1

T3

9

T7

15

T8

12

auto[1]

435

1

T3

6

T8

12

T10

12

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102	1			T3	1		T7	4		T23	1
all_values[0]	auto[0]	auto[1]	69	1			T8	1		T10	2		T69	1
all_values[0]	auto[1]	auto[0]	96	1			T3	2		T7	1		T8	4
all_values[0]	auto[1]	auto[1]	76	1			T3	2		T8	3		T10	2
all_values[1]	auto[0]	auto[0]	116	1			T3	1		T7	5		T8	3
all_values[1]	auto[0]	auto[1]	73	1			T8	3		T10	2		T23	3
all_values[1]	auto[1]	auto[0]	82	1			T3	2		T8	1		T10	3
all_values[1]	auto[1]	auto[1]	72	1			T3	2		T8	1		T10	2
all_values[2]	auto[0]	auto[0]	124	1			T3	1		T7	5		T8	2
all_values[2]	auto[0]	auto[1]	68	1			T8	1		T10	3		T25	1
all_values[2]	auto[1]	auto[0]	74	1			T3	2		T8	2		T10	1
all_values[2]	auto[1]	auto[1]	77	1			T3	2		T8	3		T10	1