Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
49.00	49.31	65.68	16.53	0.00	49.06	100.00	62.41

Total tests in report: 215

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
44.43	44.43	48.83	48.83	58.72	58.72	16.20	16.20	0.00	0.00	47.86	47.86	95.29	95.29	44.11	44.11	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3644591093
46.13	1.70	49.10	0.27	60.33	1.60	16.72	0.52	0.00	0.00	48.61	0.75	95.55	0.26	52.62	8.51	/workspace/coverage/cover_reg_top/43.kmac_intr_test.1645553233
47.37	1.24	49.31	0.21	62.62	2.30	17.16	0.44	0.00	0.00	48.84	0.23	97.64	2.09	56.03	3.40	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.563548505
48.19	0.82	49.31	0.00	64.92	2.30	17.29	0.13	0.00	0.00	49.06	0.23	97.91	0.26	58.87	2.84	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1131882237
48.49	0.30	49.31	0.00	64.92	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	2.09	58.87	0.00	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1866720822
48.65	0.16	49.31	0.00	65.06	0.15	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	59.86	0.99	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3249663810
48.76	0.10	49.31	0.00	65.06	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	60.57	0.71	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3089125679
48.84	0.09	49.31	0.00	65.39	0.33	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	60.85	0.28	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3150293079
48.90	0.06	49.31	0.00	65.39	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	61.28	0.43	/workspace/coverage/cover_reg_top/10.kmac_intr_test.2778129436
48.95	0.04	49.31	0.00	65.54	0.15	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	61.42	0.14	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.687710493
48.99	0.04	49.31	0.00	65.54	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	61.70	0.28	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.636426267
49.03	0.04	49.31	0.00	65.54	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	61.99	0.28	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2841323054
49.06	0.03	49.31	0.00	65.61	0.07	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	62.13	0.14	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4292135503
49.08	0.02	49.31	0.00	65.61	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	62.27	0.14	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1355426981
49.10	0.02	49.31	0.00	65.61	0.00	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	62.41	0.14	/workspace/coverage/cover_reg_top/12.kmac_intr_test.537520846
49.11	0.01	49.31	0.00	65.68	0.07	17.29	0.00	0.00	0.00	49.06	0.00	100.00	0.00	62.41	0.00	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.897972086

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1402651744
/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3072030717
/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3875064187
/workspace/coverage/cover_reg_top/0.kmac_csr_rw.2185911728
/workspace/coverage/cover_reg_top/0.kmac_intr_test.3963048966
/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3394972083
/workspace/coverage/cover_reg_top/0.kmac_mem_walk.3585871548
/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2233697184
/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.575801700
/workspace/coverage/cover_reg_top/0.kmac_tl_errors.3297192889
/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3567408916
/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3529968055
/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3902084186
/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3631094163
/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.339094723
/workspace/coverage/cover_reg_top/1.kmac_csr_rw.114103915
/workspace/coverage/cover_reg_top/1.kmac_intr_test.526680837
/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1051339638
/workspace/coverage/cover_reg_top/1.kmac_mem_walk.3260531501
/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1660205576
/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.128964574
/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.711926616
/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2631112579
/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3951832437
/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2248301972
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4116486527
/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3681468458
/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1749468216
/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1954036860
/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2497817835
/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2143841641
/workspace/coverage/cover_reg_top/11.kmac_intr_test.2192651521
/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1214729849
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4178032340
/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2533088766
/workspace/coverage/cover_reg_top/11.kmac_tl_errors.3150816986
/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2908378445
/workspace/coverage/cover_reg_top/12.kmac_csr_rw.3759592498
/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1575411807
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.318685242
/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.64428270
/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2820578847
/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1056673798
/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2079301340
/workspace/coverage/cover_reg_top/13.kmac_intr_test.2795031047
/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.517191905
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1167580276
/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1135369225
/workspace/coverage/cover_reg_top/13.kmac_tl_errors.771122104
/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3227083691
/workspace/coverage/cover_reg_top/14.kmac_csr_rw.1113294393
/workspace/coverage/cover_reg_top/14.kmac_intr_test.846068294
/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.429632810
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2922040963
/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4038799773
/workspace/coverage/cover_reg_top/14.kmac_tl_errors.1304564087
/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.98776177
/workspace/coverage/cover_reg_top/15.kmac_csr_rw.3919753196
/workspace/coverage/cover_reg_top/15.kmac_intr_test.2645292360
/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2671958883
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.809986689
/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4138930958
/workspace/coverage/cover_reg_top/15.kmac_tl_errors.3354676626
/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2258138357
/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3010484051
/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1943646613
/workspace/coverage/cover_reg_top/16.kmac_intr_test.183001742
/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2934663344
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.794832437
/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.483426369
/workspace/coverage/cover_reg_top/16.kmac_tl_errors.2000295817
/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.292270498
/workspace/coverage/cover_reg_top/17.kmac_csr_rw.780159925
/workspace/coverage/cover_reg_top/17.kmac_intr_test.2776448285
/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2316936217
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3009663684
/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2528851779
/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2678225038
/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1222559031
/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2006221832
/workspace/coverage/cover_reg_top/18.kmac_csr_rw.1035005338
/workspace/coverage/cover_reg_top/18.kmac_intr_test.510654704
/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2769923791
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1466275761
/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.896196107
/workspace/coverage/cover_reg_top/18.kmac_tl_errors.3432412423
/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.230078195
/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1762044551
/workspace/coverage/cover_reg_top/19.kmac_csr_rw.2192942576
/workspace/coverage/cover_reg_top/19.kmac_intr_test.3977958832
/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.153050262
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1032907577
/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.683672714
/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3426653937
/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2231430352
/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.645002440
/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.37433022
/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1155390932
/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1202670729
/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3312543389
/workspace/coverage/cover_reg_top/2.kmac_intr_test.1922782142
/workspace/coverage/cover_reg_top/2.kmac_mem_walk.403722237
/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3403670525
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1549083877
/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1253704728
/workspace/coverage/cover_reg_top/2.kmac_tl_errors.2735519342
/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1386287463
/workspace/coverage/cover_reg_top/20.kmac_intr_test.1352726772
/workspace/coverage/cover_reg_top/21.kmac_intr_test.3136236413
/workspace/coverage/cover_reg_top/22.kmac_intr_test.520101568
/workspace/coverage/cover_reg_top/23.kmac_intr_test.1543181469
/workspace/coverage/cover_reg_top/24.kmac_intr_test.667759960
/workspace/coverage/cover_reg_top/25.kmac_intr_test.1553676863
/workspace/coverage/cover_reg_top/26.kmac_intr_test.220701128
/workspace/coverage/cover_reg_top/27.kmac_intr_test.1865846731
/workspace/coverage/cover_reg_top/28.kmac_intr_test.3393532591
/workspace/coverage/cover_reg_top/29.kmac_intr_test.13051502
/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1711392413
/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2915173558
/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3461709309
/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3801967575
/workspace/coverage/cover_reg_top/3.kmac_csr_rw.983757753
/workspace/coverage/cover_reg_top/3.kmac_intr_test.2215743258
/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2020056600
/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1058916137
/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3049249622
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.503547060
/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.954562763
/workspace/coverage/cover_reg_top/3.kmac_tl_errors.1100574708
/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.100921408
/workspace/coverage/cover_reg_top/30.kmac_intr_test.1303279396
/workspace/coverage/cover_reg_top/31.kmac_intr_test.450781776
/workspace/coverage/cover_reg_top/32.kmac_intr_test.604809919
/workspace/coverage/cover_reg_top/33.kmac_intr_test.2224513914
/workspace/coverage/cover_reg_top/34.kmac_intr_test.501264238
/workspace/coverage/cover_reg_top/35.kmac_intr_test.2927066170
/workspace/coverage/cover_reg_top/36.kmac_intr_test.162321026
/workspace/coverage/cover_reg_top/37.kmac_intr_test.1840537675
/workspace/coverage/cover_reg_top/38.kmac_intr_test.678164472
/workspace/coverage/cover_reg_top/39.kmac_intr_test.1008800299
/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.455807912
/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3684800640
/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.4126534413
/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3131895515
/workspace/coverage/cover_reg_top/4.kmac_csr_rw.3833234235
/workspace/coverage/cover_reg_top/4.kmac_intr_test.3783795626
/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3290165687
/workspace/coverage/cover_reg_top/4.kmac_mem_walk.2930679538
/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2852949696
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3064548756
/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2963628878
/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.121104051
/workspace/coverage/cover_reg_top/40.kmac_intr_test.966413135
/workspace/coverage/cover_reg_top/41.kmac_intr_test.379283909
/workspace/coverage/cover_reg_top/42.kmac_intr_test.4282610113
/workspace/coverage/cover_reg_top/44.kmac_intr_test.2274111536
/workspace/coverage/cover_reg_top/45.kmac_intr_test.1108706830
/workspace/coverage/cover_reg_top/46.kmac_intr_test.2321430788
/workspace/coverage/cover_reg_top/47.kmac_intr_test.4079616844
/workspace/coverage/cover_reg_top/48.kmac_intr_test.2437202556
/workspace/coverage/cover_reg_top/49.kmac_intr_test.2719894999
/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3469549091
/workspace/coverage/cover_reg_top/5.kmac_csr_rw.2666890273
/workspace/coverage/cover_reg_top/5.kmac_intr_test.2461538091
/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3181248224
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2385418747
/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3368436262
/workspace/coverage/cover_reg_top/5.kmac_tl_errors.1734251698
/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2379607149
/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2268245900
/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3941747308
/workspace/coverage/cover_reg_top/6.kmac_intr_test.2413834319
/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.437616895
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2398013696
/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3492743573
/workspace/coverage/cover_reg_top/6.kmac_tl_errors.1884448311
/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1297083757
/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1270887954
/workspace/coverage/cover_reg_top/7.kmac_csr_rw.1733658239
/workspace/coverage/cover_reg_top/7.kmac_intr_test.1481427704
/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.69551780
/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.47427169
/workspace/coverage/cover_reg_top/7.kmac_tl_errors.975726116
/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1299731507
/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.274246193
/workspace/coverage/cover_reg_top/8.kmac_csr_rw.3111731626
/workspace/coverage/cover_reg_top/8.kmac_intr_test.675182617
/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.511275587
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3444978700
/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1801508319
/workspace/coverage/cover_reg_top/8.kmac_tl_errors.1579294157
/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1396851619
/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4008065992
/workspace/coverage/cover_reg_top/9.kmac_csr_rw.349123721
/workspace/coverage/cover_reg_top/9.kmac_intr_test.1391636373
/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2560324179
/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3828162532
/workspace/coverage/cover_reg_top/9.kmac_tl_errors.3446891920
/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1782763857

Total test records in report: 215

tests.html | tests1.html | tests2.html | tests3.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1943646613	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:48 PM PST 24	38246020 ps
T2	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.1113294393	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:50 PM PST 24	22323485 ps
T3	/workspace/coverage/cover_reg_top/5.kmac_intr_test.2461538091	Jan 10 01:10:59 PM PST 24	Jan 10 01:12:26 PM PST 24	56742912 ps
T4	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1954036860	Jan 10 01:11:40 PM PST 24	Jan 10 01:12:59 PM PST 24	136011396 ps
T7	/workspace/coverage/cover_reg_top/9.kmac_intr_test.1391636373	Jan 10 01:11:09 PM PST 24	Jan 10 01:12:37 PM PST 24	19686012 ps
T8	/workspace/coverage/cover_reg_top/46.kmac_intr_test.2321430788	Jan 10 01:11:48 PM PST 24	Jan 10 01:13:02 PM PST 24	18932239 ps
T11	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3290165687	Jan 10 01:10:57 PM PST 24	Jan 10 01:12:23 PM PST 24	49571191 ps
T5	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3644591093	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:51 PM PST 24	266037659 ps
T10	/workspace/coverage/cover_reg_top/43.kmac_intr_test.1645553233	Jan 10 01:11:51 PM PST 24	Jan 10 01:13:16 PM PST 24	48406935 ps
T6	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1355426981	Jan 10 01:10:57 PM PST 24	Jan 10 01:12:26 PM PST 24	70119207 ps
T12	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1866720822	Jan 10 01:10:40 PM PST 24	Jan 10 01:12:05 PM PST 24	47124971 ps
T9	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3444978700	Jan 10 01:11:28 PM PST 24	Jan 10 01:12:48 PM PST 24	111778309 ps
T23	/workspace/coverage/cover_reg_top/39.kmac_intr_test.1008800299	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:50 PM PST 24	40604149 ps
T24	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3009663684	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:48 PM PST 24	173743458 ps
T13	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2908378445	Jan 10 01:11:39 PM PST 24	Jan 10 01:12:56 PM PST 24	208795838 ps
T25	/workspace/coverage/cover_reg_top/18.kmac_intr_test.510654704	Jan 10 01:11:35 PM PST 24	Jan 10 01:12:59 PM PST 24	15229170 ps
T26	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3567408916	Jan 10 01:10:45 PM PST 24	Jan 10 01:12:11 PM PST 24	151828786 ps
T27	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1549083877	Jan 10 01:11:07 PM PST 24	Jan 10 01:12:33 PM PST 24	37224542 ps
T14	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1749468216	Jan 10 01:11:19 PM PST 24	Jan 10 01:12:44 PM PST 24	32931086 ps
T41	/workspace/coverage/cover_reg_top/6.kmac_intr_test.2413834319	Jan 10 01:11:00 PM PST 24	Jan 10 01:12:27 PM PST 24	35894888 ps
T30	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1782763857	Jan 10 01:11:10 PM PST 24	Jan 10 01:12:37 PM PST 24	779860086 ps
T69	/workspace/coverage/cover_reg_top/29.kmac_intr_test.13051502	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:52 PM PST 24	15965085 ps
T32	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2769923791	Jan 10 01:11:32 PM PST 24	Jan 10 01:12:50 PM PST 24	24395412 ps
T28	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1396851619	Jan 10 01:11:37 PM PST 24	Jan 10 01:12:57 PM PST 24	98388484 ps
T33	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.3833234235	Jan 10 01:10:57 PM PST 24	Jan 10 01:12:23 PM PST 24	85497108 ps
T34	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.683672714	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:52 PM PST 24	105235553 ps
T35	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.437616895	Jan 10 01:10:50 PM PST 24	Jan 10 01:12:16 PM PST 24	203444451 ps
T36	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1131882237	Jan 10 01:11:16 PM PST 24	Jan 10 01:12:40 PM PST 24	119400779 ps
T51	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2963628878	Jan 10 01:10:53 PM PST 24	Jan 10 01:12:24 PM PST 24	437613116 ps
T84	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.3585871548	Jan 10 01:10:46 PM PST 24	Jan 10 01:12:10 PM PST 24	14972154 ps
T66	/workspace/coverage/cover_reg_top/44.kmac_intr_test.2274111536	Jan 10 01:11:52 PM PST 24	Jan 10 01:13:16 PM PST 24	19304301 ps
T71	/workspace/coverage/cover_reg_top/25.kmac_intr_test.1553676863	Jan 10 01:11:32 PM PST 24	Jan 10 01:13:03 PM PST 24	33381981 ps
T37	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.794832437	Jan 10 01:11:26 PM PST 24	Jan 10 01:12:49 PM PST 24	67064829 ps
T15	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3150293079	Jan 10 01:11:00 PM PST 24	Jan 10 01:12:28 PM PST 24	147329259 ps
T42	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2671958883	Jan 10 01:11:32 PM PST 24	Jan 10 01:13:04 PM PST 24	40707333 ps
T85	/workspace/coverage/cover_reg_top/38.kmac_intr_test.678164472	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:50 PM PST 24	27314664 ps
T43	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3941747308	Jan 10 01:10:57 PM PST 24	Jan 10 01:12:26 PM PST 24	27483111 ps
T86	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.3260531501	Jan 10 01:10:44 PM PST 24	Jan 10 01:12:08 PM PST 24	30569600 ps
T60	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.3111731626	Jan 10 01:11:09 PM PST 24	Jan 10 01:12:35 PM PST 24	299099815 ps
T70	/workspace/coverage/cover_reg_top/22.kmac_intr_test.520101568	Jan 10 01:11:43 PM PST 24	Jan 10 01:12:59 PM PST 24	15897505 ps
T47	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.687710493	Jan 10 01:10:37 PM PST 24	Jan 10 01:12:03 PM PST 24	124122632 ps
T16	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.2000295817	Jan 10 01:11:28 PM PST 24	Jan 10 01:12:48 PM PST 24	43745274 ps
T17	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.563548505	Jan 10 01:10:51 PM PST 24	Jan 10 01:12:17 PM PST 24	250328416 ps
T87	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2437202556	Jan 10 01:11:48 PM PST 24	Jan 10 01:13:07 PM PST 24	19710252 ps
T44	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3312543389	Jan 10 01:10:45 PM PST 24	Jan 10 01:12:08 PM PST 24	142094994 ps
T18	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.771122104	Jan 10 01:11:33 PM PST 24	Jan 10 01:12:56 PM PST 24	125656729 ps
T45	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.780159925	Jan 10 01:11:41 PM PST 24	Jan 10 01:13:07 PM PST 24	19468559 ps
T67	/workspace/coverage/cover_reg_top/34.kmac_intr_test.501264238	Jan 10 01:11:40 PM PST 24	Jan 10 01:12:56 PM PST 24	37209604 ps
T19	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.1884448311	Jan 10 01:10:45 PM PST 24	Jan 10 01:12:10 PM PST 24	24065910 ps
T20	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.98776177	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:49 PM PST 24	45598706 ps
T61	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3902084186	Jan 10 01:10:45 PM PST 24	Jan 10 01:12:21 PM PST 24	4879651459 ps
T21	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2006221832	Jan 10 01:11:34 PM PST 24	Jan 10 01:12:55 PM PST 24	21336101 ps
T88	/workspace/coverage/cover_reg_top/14.kmac_intr_test.846068294	Jan 10 01:11:26 PM PST 24	Jan 10 01:12:49 PM PST 24	15031314 ps
T46	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3181248224	Jan 10 01:11:30 PM PST 24	Jan 10 01:12:52 PM PST 24	75808695 ps
T62	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1214729849	Jan 10 01:11:21 PM PST 24	Jan 10 01:12:48 PM PST 24	125245309 ps
T89	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2079301340	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:47 PM PST 24	13607385 ps
T22	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3227083691	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:50 PM PST 24	62476406 ps
T90	/workspace/coverage/cover_reg_top/47.kmac_intr_test.4079616844	Jan 10 01:11:47 PM PST 24	Jan 10 01:13:13 PM PST 24	12730111 ps
T52	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2528851779	Jan 10 01:11:29 PM PST 24	Jan 10 01:12:57 PM PST 24	66310436 ps
T91	/workspace/coverage/cover_reg_top/10.kmac_intr_test.2778129436	Jan 10 01:11:11 PM PST 24	Jan 10 01:12:38 PM PST 24	17282056 ps
T29	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3131895515	Jan 10 01:10:57 PM PST 24	Jan 10 01:12:24 PM PST 24	32624096 ps
T92	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3631094163	Jan 10 01:11:01 PM PST 24	Jan 10 01:12:30 PM PST 24	35954387 ps
T31	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.897972086	Jan 10 01:11:11 PM PST 24	Jan 10 01:12:39 PM PST 24	183108475 ps
T63	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.809986689	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:48 PM PST 24	55570707 ps
T93	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.37433022	Jan 10 01:10:52 PM PST 24	Jan 10 01:12:24 PM PST 24	167083510 ps
T68	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.3354676626	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:48 PM PST 24	91588077 ps
T72	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1386287463	Jan 10 01:10:42 PM PST 24	Jan 10 01:12:10 PM PST 24	831575827 ps
T94	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.2185911728	Jan 10 01:10:39 PM PST 24	Jan 10 01:12:04 PM PST 24	18554159 ps
T95	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1155390932	Jan 10 01:10:55 PM PST 24	Jan 10 01:12:20 PM PST 24	36322948 ps
T48	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4116486527	Jan 10 01:11:10 PM PST 24	Jan 10 01:12:35 PM PST 24	36478197 ps
T96	/workspace/coverage/cover_reg_top/16.kmac_intr_test.183001742	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:47 PM PST 24	20857661 ps
T97	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.292270498	Jan 10 01:11:32 PM PST 24	Jan 10 01:12:51 PM PST 24	67995508 ps
T82	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1167580276	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:48 PM PST 24	114047589 ps
T64	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2915173558	Jan 10 01:10:44 PM PST 24	Jan 10 01:12:19 PM PST 24	816265580 ps
T65	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2233697184	Jan 10 01:10:43 PM PST 24	Jan 10 01:12:07 PM PST 24	238053199 ps
T98	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.339094723	Jan 10 01:10:47 PM PST 24	Jan 10 01:12:15 PM PST 24	76798489 ps
T99	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1402651744	Jan 10 01:10:42 PM PST 24	Jan 10 01:12:13 PM PST 24	268105412 ps
T100	/workspace/coverage/cover_reg_top/35.kmac_intr_test.2927066170	Jan 10 01:12:02 PM PST 24	Jan 10 01:13:16 PM PST 24	25805715 ps
T77	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.100921408	Jan 10 01:10:51 PM PST 24	Jan 10 01:12:16 PM PST 24	261657046 ps
T101	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.896196107	Jan 10 01:11:34 PM PST 24	Jan 10 01:12:55 PM PST 24	250182999 ps
T76	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.121104051	Jan 10 01:10:55 PM PST 24	Jan 10 01:12:28 PM PST 24	605060070 ps
T83	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3249663810	Jan 10 01:11:08 PM PST 24	Jan 10 01:12:38 PM PST 24	485294921 ps
T55	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3681468458	Jan 10 01:11:07 PM PST 24	Jan 10 01:12:34 PM PST 24	102436545 ps
T102	/workspace/coverage/cover_reg_top/13.kmac_intr_test.2795031047	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:48 PM PST 24	53418479 ps
T103	/workspace/coverage/cover_reg_top/15.kmac_intr_test.2645292360	Jan 10 01:11:38 PM PST 24	Jan 10 01:13:00 PM PST 24	42109673 ps
T104	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3469549091	Jan 10 01:10:56 PM PST 24	Jan 10 01:12:26 PM PST 24	36988970 ps
T105	/workspace/coverage/cover_reg_top/28.kmac_intr_test.3393532591	Jan 10 01:11:41 PM PST 24	Jan 10 01:13:07 PM PST 24	31524546 ps
T106	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3875064187	Jan 10 01:10:59 PM PST 24	Jan 10 01:12:28 PM PST 24	19626955 ps
T107	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1032907577	Jan 10 01:11:34 PM PST 24	Jan 10 01:12:55 PM PST 24	68519879 ps
T108	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.503547060	Jan 10 01:10:48 PM PST 24	Jan 10 01:12:13 PM PST 24	26219226 ps
T109	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2852949696	Jan 10 01:10:51 PM PST 24	Jan 10 01:12:17 PM PST 24	44379067 ps
T59	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.1304564087	Jan 10 01:11:25 PM PST 24	Jan 10 01:12:55 PM PST 24	1257318888 ps
T110	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.2930679538	Jan 10 01:11:12 PM PST 24	Jan 10 01:12:38 PM PST 24	15703411 ps
T111	/workspace/coverage/cover_reg_top/30.kmac_intr_test.1303279396	Jan 10 01:12:00 PM PST 24	Jan 10 01:13:12 PM PST 24	43608316 ps
T112	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.349123721	Jan 10 01:11:41 PM PST 24	Jan 10 01:13:07 PM PST 24	39862893 ps
T113	/workspace/coverage/cover_reg_top/12.kmac_intr_test.537520846	Jan 10 01:11:18 PM PST 24	Jan 10 01:12:44 PM PST 24	31707014 ps
T114	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.2192942576	Jan 10 01:11:44 PM PST 24	Jan 10 01:12:59 PM PST 24	99712386 ps
T115	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.517191905	Jan 10 01:11:26 PM PST 24	Jan 10 01:12:50 PM PST 24	108756142 ps
T116	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2497817835	Jan 10 01:11:08 PM PST 24	Jan 10 01:12:44 PM PST 24	29683465 ps
T117	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.575801700	Jan 10 01:10:47 PM PST 24	Jan 10 01:12:11 PM PST 24	54901798 ps
T118	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.483426369	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:51 PM PST 24	122985860 ps
T119	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.403722237	Jan 10 01:10:50 PM PST 24	Jan 10 01:12:14 PM PST 24	33746021 ps
T49	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2385418747	Jan 10 01:10:52 PM PST 24	Jan 10 01:12:17 PM PST 24	368133437 ps
T120	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4008065992	Jan 10 01:11:08 PM PST 24	Jan 10 01:12:44 PM PST 24	21197590 ps
T121	/workspace/coverage/cover_reg_top/36.kmac_intr_test.162321026	Jan 10 01:30:42 PM PST 24	Jan 10 01:30:43 PM PST 24	50773513 ps
T38	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2020056600	Jan 10 01:11:00 PM PST 24	Jan 10 01:12:26 PM PST 24	28151489 ps
T122	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3461709309	Jan 10 01:10:52 PM PST 24	Jan 10 01:12:16 PM PST 24	33395121 ps
T123	/workspace/coverage/cover_reg_top/23.kmac_intr_test.1543181469	Jan 10 01:11:37 PM PST 24	Jan 10 01:12:54 PM PST 24	44344517 ps
T73	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2841323054	Jan 10 01:11:29 PM PST 24	Jan 10 01:13:00 PM PST 24	477460453 ps
T124	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2231430352	Jan 10 01:11:32 PM PST 24	Jan 10 01:12:51 PM PST 24	83181754 ps
T125	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1056673798	Jan 10 01:11:27 PM PST 24	Jan 10 01:12:48 PM PST 24	84552599 ps
T57	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2678225038	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:52 PM PST 24	314761150 ps
T126	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.153050262	Jan 10 01:11:30 PM PST 24	Jan 10 01:12:52 PM PST 24	76880142 ps
T53	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3064548756	Jan 10 01:10:57 PM PST 24	Jan 10 01:12:26 PM PST 24	116749838 ps
T127	/workspace/coverage/cover_reg_top/11.kmac_intr_test.2192651521	Jan 10 01:11:18 PM PST 24	Jan 10 01:12:44 PM PST 24	122296668 ps
T128	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1058916137	Jan 10 01:11:02 PM PST 24	Jan 10 01:12:28 PM PST 24	21909134 ps
T129	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1660205576	Jan 10 01:11:01 PM PST 24	Jan 10 01:12:30 PM PST 24	27416764 ps
T130	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1575411807	Jan 10 01:11:07 PM PST 24	Jan 10 01:12:33 PM PST 24	27825432 ps
T131	/workspace/coverage/cover_reg_top/49.kmac_intr_test.2719894999	Jan 10 01:11:47 PM PST 24	Jan 10 01:13:13 PM PST 24	24338558 ps
T132	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4178032340	Jan 10 01:11:17 PM PST 24	Jan 10 01:12:41 PM PST 24	115567661 ps
T133	/workspace/coverage/cover_reg_top/3.kmac_intr_test.2215743258	Jan 10 01:10:49 PM PST 24	Jan 10 01:12:16 PM PST 24	45347020 ps
T134	/workspace/coverage/cover_reg_top/32.kmac_intr_test.604809919	Jan 10 01:12:00 PM PST 24	Jan 10 01:13:12 PM PST 24	27005040 ps
T135	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.4126534413	Jan 10 01:11:23 PM PST 24	Jan 10 01:12:45 PM PST 24	69008194 ps
T136	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1801508319	Jan 10 01:11:38 PM PST 24	Jan 10 01:13:02 PM PST 24	59400993 ps
T137	/workspace/coverage/cover_reg_top/17.kmac_intr_test.2776448285	Jan 10 01:11:30 PM PST 24	Jan 10 01:12:51 PM PST 24	12148230 ps
T138	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2934663344	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:52 PM PST 24	290681071 ps
T139	/workspace/coverage/cover_reg_top/41.kmac_intr_test.379283909	Jan 10 01:11:42 PM PST 24	Jan 10 01:13:07 PM PST 24	43770278 ps
T140	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.274246193	Jan 10 01:11:06 PM PST 24	Jan 10 01:12:39 PM PST 24	21509266 ps
T141	/workspace/coverage/cover_reg_top/1.kmac_intr_test.526680837	Jan 10 01:10:47 PM PST 24	Jan 10 01:12:10 PM PST 24	12635204 ps
T142	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.69551780	Jan 10 01:11:09 PM PST 24	Jan 10 01:12:35 PM PST 24	81173923 ps
T143	/workspace/coverage/cover_reg_top/24.kmac_intr_test.667759960	Jan 10 01:11:37 PM PST 24	Jan 10 01:12:53 PM PST 24	40233212 ps
T144	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2143841641	Jan 10 01:11:04 PM PST 24	Jan 10 01:12:32 PM PST 24	23271007 ps
T145	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.429632810	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:53 PM PST 24	90039406 ps
T146	/workspace/coverage/cover_reg_top/27.kmac_intr_test.1865846731	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:50 PM PST 24	13437068 ps
T147	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1466275761	Jan 10 01:11:41 PM PST 24	Jan 10 01:13:07 PM PST 24	116033131 ps
T148	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4038799773	Jan 10 01:11:26 PM PST 24	Jan 10 01:12:50 PM PST 24	80533840 ps
T74	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2258138357	Jan 10 01:11:26 PM PST 24	Jan 10 01:12:53 PM PST 24	200352049 ps
T149	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2922040963	Jan 10 01:11:32 PM PST 24	Jan 10 01:13:03 PM PST 24	20401563 ps
T150	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1202670729	Jan 10 01:10:52 PM PST 24	Jan 10 01:12:20 PM PST 24	196074059 ps
T39	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1051339638	Jan 10 01:10:49 PM PST 24	Jan 10 01:12:14 PM PST 24	154983996 ps
T151	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3783795626	Jan 10 01:10:49 PM PST 24	Jan 10 01:12:16 PM PST 24	49242563 ps
T152	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1270887954	Jan 10 01:11:16 PM PST 24	Jan 10 01:12:41 PM PST 24	322136478 ps
T153	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3072030717	Jan 10 01:10:48 PM PST 24	Jan 10 01:12:20 PM PST 24	318289905 ps
T54	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2398013696	Jan 10 01:10:49 PM PST 24	Jan 10 01:12:13 PM PST 24	87287143 ps
T154	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.3919753196	Jan 10 01:11:29 PM PST 24	Jan 10 01:12:57 PM PST 24	40475007 ps
T155	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.455807912	Jan 10 01:11:00 PM PST 24	Jan 10 01:12:36 PM PST 24	445118608 ps
T156	/workspace/coverage/cover_reg_top/31.kmac_intr_test.450781776	Jan 10 01:11:32 PM PST 24	Jan 10 01:13:03 PM PST 24	55995972 ps
T157	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.983757753	Jan 10 01:10:51 PM PST 24	Jan 10 01:12:14 PM PST 24	14667835 ps
T158	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3136236413	Jan 10 01:12:00 PM PST 24	Jan 10 01:13:13 PM PST 24	10535875 ps
T159	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.1035005338	Jan 10 01:11:32 PM PST 24	Jan 10 01:13:03 PM PST 24	90281059 ps
T160	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2268245900	Jan 10 01:11:03 PM PST 24	Jan 10 01:12:30 PM PST 24	34172578 ps
T56	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.975726116	Jan 10 01:10:44 PM PST 24	Jan 10 01:12:10 PM PST 24	496664761 ps
T161	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3801967575	Jan 10 01:11:20 PM PST 24	Jan 10 01:12:44 PM PST 24	214826260 ps
T162	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1222559031	Jan 10 01:11:32 PM PST 24	Jan 10 01:12:52 PM PST 24	148226224 ps
T58	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3426653937	Jan 10 01:11:35 PM PST 24	Jan 10 01:12:55 PM PST 24	96871118 ps
T163	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.128964574	Jan 10 01:10:45 PM PST 24	Jan 10 01:12:10 PM PST 24	271306889 ps
T164	/workspace/coverage/cover_reg_top/8.kmac_intr_test.675182617	Jan 10 01:11:16 PM PST 24	Jan 10 01:12:39 PM PST 24	36749016 ps
T165	/workspace/coverage/cover_reg_top/0.kmac_intr_test.3963048966	Jan 10 01:10:37 PM PST 24	Jan 10 01:12:02 PM PST 24	14901714 ps
T166	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3951832437	Jan 10 01:11:11 PM PST 24	Jan 10 01:12:38 PM PST 24	71582327 ps
T167	/workspace/coverage/cover_reg_top/2.kmac_intr_test.1922782142	Jan 10 01:10:37 PM PST 24	Jan 10 01:12:02 PM PST 24	77534495 ps
T168	/workspace/coverage/cover_reg_top/40.kmac_intr_test.966413135	Jan 10 01:11:29 PM PST 24	Jan 10 01:12:57 PM PST 24	52010850 ps
T169	/workspace/coverage/cover_reg_top/20.kmac_intr_test.1352726772	Jan 10 01:11:40 PM PST 24	Jan 10 01:12:55 PM PST 24	164612152 ps
T170	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3049249622	Jan 10 01:11:00 PM PST 24	Jan 10 01:12:28 PM PST 24	351256629 ps
T171	/workspace/coverage/cover_reg_top/37.kmac_intr_test.1840537675	Jan 10 01:50:51 PM PST 24	Jan 10 01:50:53 PM PST 24	20553955 ps
T172	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3529968055	Jan 10 01:10:45 PM PST 24	Jan 10 01:12:18 PM PST 24	4341409230 ps
T173	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.3446891920	Jan 10 01:11:08 PM PST 24	Jan 10 01:12:38 PM PST 24	356545729 ps
T174	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.511275587	Jan 10 01:11:07 PM PST 24	Jan 10 01:12:34 PM PST 24	290485438 ps
T175	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3010484051	Jan 10 01:11:29 PM PST 24	Jan 10 01:12:57 PM PST 24	127254267 ps
T75	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3089125679	Jan 10 01:11:30 PM PST 24	Jan 10 01:12:56 PM PST 24	550582838 ps
T176	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1135369225	Jan 10 01:11:29 PM PST 24	Jan 10 01:12:58 PM PST 24	98162470 ps
T177	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.3297192889	Jan 10 01:10:47 PM PST 24	Jan 10 01:12:16 PM PST 24	166046794 ps
T178	/workspace/coverage/cover_reg_top/19.kmac_intr_test.3977958832	Jan 10 01:12:05 PM PST 24	Jan 10 01:13:20 PM PST 24	51981907 ps
T179	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3828162532	Jan 10 01:11:18 PM PST 24	Jan 10 01:12:44 PM PST 24	37238672 ps
T180	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.318685242	Jan 10 01:11:17 PM PST 24	Jan 10 01:12:41 PM PST 24	117066561 ps
T80	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.636426267	Jan 10 01:11:15 PM PST 24	Jan 10 01:12:43 PM PST 24	113539437 ps
T50	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3492743573	Jan 10 01:10:52 PM PST 24	Jan 10 01:12:17 PM PST 24	50307431 ps
T181	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.3759592498	Jan 10 01:11:09 PM PST 24	Jan 10 01:12:37 PM PST 24	56874881 ps
T79	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1299731507	Jan 10 01:10:58 PM PST 24	Jan 10 01:12:32 PM PST 24	551539131 ps
T78	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.230078195	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:56 PM PST 24	509332398 ps
T182	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2533088766	Jan 10 01:11:06 PM PST 24	Jan 10 01:12:39 PM PST 24	142373747 ps
T183	/workspace/coverage/cover_reg_top/33.kmac_intr_test.2224513914	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:50 PM PST 24	15232439 ps
T184	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.2735519342	Jan 10 01:11:06 PM PST 24	Jan 10 01:12:43 PM PST 24	88511272 ps
T185	/workspace/coverage/cover_reg_top/45.kmac_intr_test.1108706830	Jan 10 01:11:47 PM PST 24	Jan 10 01:13:02 PM PST 24	80223790 ps
T186	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.2666890273	Jan 10 01:10:48 PM PST 24	Jan 10 01:12:13 PM PST 24	59732079 ps
T187	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.3150816986	Jan 10 01:11:37 PM PST 24	Jan 10 01:13:08 PM PST 24	381952968 ps
T188	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2560324179	Jan 10 01:11:17 PM PST 24	Jan 10 01:12:41 PM PST 24	50728924 ps
T189	/workspace/coverage/cover_reg_top/26.kmac_intr_test.220701128	Jan 10 01:11:58 PM PST 24	Jan 10 01:13:12 PM PST 24	162054983 ps
T190	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4292135503	Jan 10 01:10:48 PM PST 24	Jan 10 01:12:12 PM PST 24	26655573 ps
T191	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3403670525	Jan 10 01:10:47 PM PST 24	Jan 10 01:12:13 PM PST 24	80513715 ps
T40	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3394972083	Jan 10 01:10:42 PM PST 24	Jan 10 01:12:06 PM PST 24	144295407 ps
T192	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3684800640	Jan 10 01:11:05 PM PST 24	Jan 10 01:12:42 PM PST 24	819146676 ps
T193	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3368436262	Jan 10 01:11:20 PM PST 24	Jan 10 01:12:44 PM PST 24	37085243 ps
T81	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2820578847	Jan 10 01:11:18 PM PST 24	Jan 10 01:12:48 PM PST 24	286834207 ps
T194	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.1733658239	Jan 10 01:10:57 PM PST 24	Jan 10 01:12:26 PM PST 24	32649529 ps
T195	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.711926616	Jan 10 01:10:46 PM PST 24	Jan 10 01:12:14 PM PST 24	224832241 ps
T196	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.64428270	Jan 10 01:11:18 PM PST 24	Jan 10 01:12:46 PM PST 24	568438136 ps
T197	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1253704728	Jan 10 01:11:07 PM PST 24	Jan 10 01:12:33 PM PST 24	48007878 ps
T198	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.47427169	Jan 10 01:11:00 PM PST 24	Jan 10 01:12:28 PM PST 24	195796524 ps
T199	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.3432412423	Jan 10 01:11:32 PM PST 24	Jan 10 01:12:55 PM PST 24	82556566 ps
T200	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.114103915	Jan 10 01:10:50 PM PST 24	Jan 10 01:12:15 PM PST 24	34150165 ps
T201	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.1100574708	Jan 10 01:11:06 PM PST 24	Jan 10 01:12:35 PM PST 24	118611436 ps
T202	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2379607149	Jan 10 01:10:53 PM PST 24	Jan 10 01:12:26 PM PST 24	243864167 ps
T203	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1762044551	Jan 10 01:11:32 PM PST 24	Jan 10 01:12:50 PM PST 24	21338566 ps
T204	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.954562763	Jan 10 01:10:49 PM PST 24	Jan 10 01:12:14 PM PST 24	73462500 ps
T205	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2248301972	Jan 10 01:11:08 PM PST 24	Jan 10 01:12:40 PM PST 24	44696089 ps
T206	/workspace/coverage/cover_reg_top/7.kmac_intr_test.1481427704	Jan 10 01:10:55 PM PST 24	Jan 10 01:12:19 PM PST 24	45856905 ps
T207	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2631112579	Jan 10 01:11:19 PM PST 24	Jan 10 01:12:43 PM PST 24	48323419 ps
T208	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1297083757	Jan 10 01:10:57 PM PST 24	Jan 10 01:12:27 PM PST 24	275808020 ps
T209	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1711392413	Jan 10 01:10:49 PM PST 24	Jan 10 01:12:23 PM PST 24	572126515 ps
T210	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.1734251698	Jan 10 01:10:54 PM PST 24	Jan 10 01:12:23 PM PST 24	38233938 ps
T211	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2316936217	Jan 10 01:11:31 PM PST 24	Jan 10 01:12:51 PM PST 24	52711239 ps
T212	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4138930958	Jan 10 01:11:38 PM PST 24	Jan 10 01:12:58 PM PST 24	53132721 ps
T213	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.645002440	Jan 10 01:10:50 PM PST 24	Jan 10 01:12:33 PM PST 24	231035924 ps
T214	/workspace/coverage/cover_reg_top/42.kmac_intr_test.4282610113	Jan 10 01:12:01 PM PST 24	Jan 10 01:13:15 PM PST 24	42770432 ps
T215	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.1579294157	Jan 10 01:11:11 PM PST 24	Jan 10 01:12:39 PM PST 24	118842159 ps

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3644591093
Short name	T5
Test name
Test status
Simulation time	266037659 ps
CPU time	5.06 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:51 PM PST 24
Peak memory	207324 kb
Host	smart-bed6e7c4-d327-463f-b6fb-820c6c1aac78
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644591093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3644 591093 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.1645553233
Short name	T10
Test name
Test status
Simulation time	48406935 ps
CPU time	0.75 seconds
Started	Jan 10 01:11:51 PM PST 24
Finished	Jan 10 01:13:16 PM PST 24
Peak memory	207032 kb
Host	smart-e07f4162-760e-4a1f-aebb-54edebb7f39f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645553233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.1645553233 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.563548505
Short name	T17
Test name
Test status
Simulation time	250328416 ps
CPU time	2.06 seconds
Started	Jan 10 01:10:51 PM PST 24
Finished	Jan 10 01:12:17 PM PST 24
Peak memory	215656 kb
Host	smart-bb0d5447-cd2e-4b95-b1ca-ccae5891e572
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563548505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.563548505 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1131882237
Short name	T36
Test name
Test status
Simulation time	119400779 ps
CPU time	1.24 seconds
Started	Jan 10 01:11:16 PM PST 24
Finished	Jan 10 01:12:40 PM PST 24
Peak memory	215568 kb
Host	smart-08d40d51-83f6-4a4b-ba73-9de10580fb3d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131882237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.1131882237 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.1866720822
Short name	T12
Test name
Test status
Simulation time	47124971 ps
CPU time	1.57 seconds
Started	Jan 10 01:10:40 PM PST 24
Finished	Jan 10 01:12:05 PM PST 24
Peak memory	215472 kb
Host	smart-1cb70429-8f35-4461-a64a-57a4837b6afd
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866720822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.1866720822 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.3249663810
Short name	T83
Test name
Test status
Simulation time	485294921 ps
CPU time	2.91 seconds
Started	Jan 10 01:11:08 PM PST 24
Finished	Jan 10 01:12:38 PM PST 24
Peak memory	216004 kb
Host	smart-65c9ae91-f046-4b89-9f78-7204a4a153c2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249663810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac _shadow_reg_errors_with_csr_rw.3249663810 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3089125679
Short name	T75
Test name
Test status
Simulation time	550582838 ps
CPU time	5.15 seconds
Started	Jan 10 01:11:30 PM PST 24
Finished	Jan 10 01:12:56 PM PST 24
Peak memory	219208 kb
Host	smart-fb276304-e151-4f26-a381-c92f659355ad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089125679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3089 125679 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.3150293079
Short name	T15
Test name
Test status
Simulation time	147329259 ps
CPU time	2.26 seconds
Started	Jan 10 01:11:00 PM PST 24
Finished	Jan 10 01:12:28 PM PST 24
Peak memory	215588 kb
Host	smart-a8bd5c9d-d88f-4054-a389-581d1c0eeded
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150293079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.3150293079 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.2778129436
Short name	T91
Test name
Test status
Simulation time	17282056 ps
CPU time	0.79 seconds
Started	Jan 10 01:11:11 PM PST 24
Finished	Jan 10 01:12:38 PM PST 24
Peak memory	206916 kb
Host	smart-ef4a7dbf-04d5-42d3-825d-6c69082346e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778129436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.2778129436 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.687710493
Short name	T47
Test name
Test status
Simulation time	124122632 ps
CPU time	2.79 seconds
Started	Jan 10 01:10:37 PM PST 24
Finished	Jan 10 01:12:03 PM PST 24
Peak memory	215836 kb
Host	smart-11446ea4-2208-4f21-a209-970893b08949
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687710493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_ shadow_reg_errors_with_csr_rw.687710493 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.636426267
Short name	T80
Test name
Test status
Simulation time	113539437 ps
CPU time	2.52 seconds
Started	Jan 10 01:11:15 PM PST 24
Finished	Jan 10 01:12:43 PM PST 24
Peak memory	207260 kb
Host	smart-3f76021e-3a85-49f8-89c3-ccb4b047027e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636426267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.63642 6267 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.2841323054
Short name	T73
Test name
Test status
Simulation time	477460453 ps
CPU time	4.72 seconds
Started	Jan 10 01:11:29 PM PST 24
Finished	Jan 10 01:13:00 PM PST 24
Peak memory	215360 kb
Host	smart-e0523709-ec3c-4a23-a403-907df3f94aed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841323054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.2841 323054 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4292135503
Short name	T190
Test name
Test status
Simulation time	26655573 ps
CPU time	0.92 seconds
Started	Jan 10 01:10:48 PM PST 24
Finished	Jan 10 01:12:12 PM PST 24
Peak memory	206992 kb
Host	smart-475b9dd0-c688-41e4-86c7-45eb4b360558
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292135503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.4292135503 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.1355426981
Short name	T6
Test name
Test status
Simulation time	70119207 ps
CPU time	1.71 seconds
Started	Jan 10 01:10:57 PM PST 24
Finished	Jan 10 01:12:26 PM PST 24
Peak memory	223568 kb
Host	smart-36ff6c72-b531-4893-9246-7e9d1ec91a0f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355426981 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.1355426981 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.537520846
Short name	T113
Test name
Test status
Simulation time	31707014 ps
CPU time	0.76 seconds
Started	Jan 10 01:11:18 PM PST 24
Finished	Jan 10 01:12:44 PM PST 24
Peak memory	206932 kb
Host	smart-c1b718ae-7b75-4f08-b90f-2a3018e645f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537520846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.537520846 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.897972086
Short name	T31
Test name
Test status
Simulation time	183108475 ps
CPU time	2.53 seconds
Started	Jan 10 01:11:11 PM PST 24
Finished	Jan 10 01:12:39 PM PST 24
Peak memory	215536 kb
Host	smart-dbebab82-8e7a-43f9-816d-5650bbdbf57c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897972086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.897972086 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.1402651744
Short name	T99
Test name
Test status
Simulation time	268105412 ps
CPU time	8.63 seconds
Started	Jan 10 01:10:42 PM PST 24
Finished	Jan 10 01:12:13 PM PST 24
Peak memory	207424 kb
Host	smart-488793a5-0142-4fb0-a9c1-18dc3333137a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402651744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.1402651 744 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3072030717
Short name	T153
Test name
Test status
Simulation time	318289905 ps
CPU time	8.94 seconds
Started	Jan 10 01:10:48 PM PST 24
Finished	Jan 10 01:12:20 PM PST 24
Peak memory	207248 kb
Host	smart-2d556ec5-f00e-469f-9b11-0dcea40376bc
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072030717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3072030 717 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3875064187
Short name	T106
Test name
Test status
Simulation time	19626955 ps
CPU time	1.04 seconds
Started	Jan 10 01:10:59 PM PST 24
Finished	Jan 10 01:12:28 PM PST 24
Peak memory	207208 kb
Host	smart-6bf39ded-7cb7-4ded-adb2-50380cef0fe4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875064187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3875064 187 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.2185911728
Short name	T94
Test name
Test status
Simulation time	18554159 ps
CPU time	0.91 seconds
Started	Jan 10 01:10:39 PM PST 24
Finished	Jan 10 01:12:04 PM PST 24
Peak memory	207012 kb
Host	smart-59df9d4d-164b-4bfc-970c-4d0f906ab35b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185911728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2185911728 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.3963048966
Short name	T165
Test name
Test status
Simulation time	14901714 ps
CPU time	0.77 seconds
Started	Jan 10 01:10:37 PM PST 24
Finished	Jan 10 01:12:02 PM PST 24
Peak memory	207028 kb
Host	smart-459d944d-48d4-43b4-bd7f-889e69c03dc1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963048966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.3963048966 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3394972083
Short name	T40
Test name
Test status
Simulation time	144295407 ps
CPU time	1.42 seconds
Started	Jan 10 01:10:42 PM PST 24
Finished	Jan 10 01:12:06 PM PST 24
Peak memory	215420 kb
Host	smart-3dd3afe3-07c2-4ad5-b398-6045cdda0b0f
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394972083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.3394972083 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.3585871548
Short name	T84
Test name
Test status
Simulation time	14972154 ps
CPU time	0.73 seconds
Started	Jan 10 01:10:46 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	207040 kb
Host	smart-651c039f-86ff-43c7-8d41-845ad202576c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585871548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3585871548 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.2233697184
Short name	T65
Test name
Test status
Simulation time	238053199 ps
CPU time	1.71 seconds
Started	Jan 10 01:10:43 PM PST 24
Finished	Jan 10 01:12:07 PM PST 24
Peak memory	215488 kb
Host	smart-9f1c2551-c4b7-4470-a141-d4328f20efbe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233697184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.2233697184 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.575801700
Short name	T117
Test name
Test status
Simulation time	54901798 ps
CPU time	1.07 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:11 PM PST 24
Peak memory	215816 kb
Host	smart-8146acb4-5f0b-4d1c-b50e-60d82f0e9f98
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575801700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_e rrors.575801700 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.3297192889
Short name	T177
Test name
Test status
Simulation time	166046794 ps
CPU time	2.69 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:16 PM PST 24
Peak memory	215564 kb
Host	smart-67d84d6d-c25a-4665-baed-abf51339ac24
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297192889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3297192889 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.3567408916
Short name	T26
Test name
Test status
Simulation time	151828786 ps
CPU time	3.15 seconds
Started	Jan 10 01:10:45 PM PST 24
Finished	Jan 10 01:12:11 PM PST 24
Peak memory	215452 kb
Host	smart-f650738f-6447-4292-904d-da01c1fd56c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567408916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.35674 08916 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3529968055
Short name	T172
Test name
Test status
Simulation time	4341409230 ps
CPU time	10.83 seconds
Started	Jan 10 01:10:45 PM PST 24
Finished	Jan 10 01:12:18 PM PST 24
Peak memory	215648 kb
Host	smart-a4d275c4-03bb-491a-ba9d-f30517e25019
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529968055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3529968 055 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3902084186
Short name	T61
Test name
Test status
Simulation time	4879651459 ps
CPU time	13.4 seconds
Started	Jan 10 01:10:45 PM PST 24
Finished	Jan 10 01:12:21 PM PST 24
Peak memory	207392 kb
Host	smart-1f65c30d-a373-4810-847e-5442e92aa5b0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902084186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3902084 186 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3631094163
Short name	T92
Test name
Test status
Simulation time	35954387 ps
CPU time	0.98 seconds
Started	Jan 10 01:11:01 PM PST 24
Finished	Jan 10 01:12:30 PM PST 24
Peak memory	206936 kb
Host	smart-157a95e7-90a5-46c1-aabf-7984505fc8a0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631094163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3631094 163 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.339094723
Short name	T98
Test name
Test status
Simulation time	76798489 ps
CPU time	2.11 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:15 PM PST 24
Peak memory	223664 kb
Host	smart-5390b319-d2ab-4c96-bc12-ea556d4ed2d7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339094723 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.339094723 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.114103915
Short name	T200
Test name
Test status
Simulation time	34150165 ps
CPU time	1.18 seconds
Started	Jan 10 01:10:50 PM PST 24
Finished	Jan 10 01:12:15 PM PST 24
Peak memory	207304 kb
Host	smart-51ba2ffa-dc37-4560-b7be-6efa1df46281
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114103915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.114103915 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.526680837
Short name	T141
Test name
Test status
Simulation time	12635204 ps
CPU time	0.79 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	207068 kb
Host	smart-96b0b9d2-2a81-4f46-9271-56f74e62c151
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526680837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.526680837 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1051339638
Short name	T39
Test name
Test status
Simulation time	154983996 ps
CPU time	1.45 seconds
Started	Jan 10 01:10:49 PM PST 24
Finished	Jan 10 01:12:14 PM PST 24
Peak memory	215380 kb
Host	smart-055b5e11-ef00-497b-9637-2d1cf5dddd38
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051339638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.1051339638 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.3260531501
Short name	T86
Test name
Test status
Simulation time	30569600 ps
CPU time	0.7 seconds
Started	Jan 10 01:10:44 PM PST 24
Finished	Jan 10 01:12:08 PM PST 24
Peak memory	207076 kb
Host	smart-291b0bda-5170-4e95-aecc-5e7955d527e9
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260531501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3260531501 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1660205576
Short name	T129
Test name
Test status
Simulation time	27416764 ps
CPU time	1.35 seconds
Started	Jan 10 01:11:01 PM PST 24
Finished	Jan 10 01:12:30 PM PST 24
Peak memory	215784 kb
Host	smart-393cb943-3a25-4193-9a0d-2b1aa07ac250
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660205576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr _outstanding.1660205576 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.128964574
Short name	T163
Test name
Test status
Simulation time	271306889 ps
CPU time	2.51 seconds
Started	Jan 10 01:10:45 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	223880 kb
Host	smart-52c8d8ee-68d6-445e-8a34-572764b1c5e7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128964574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_ shadow_reg_errors_with_csr_rw.128964574 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.711926616
Short name	T195
Test name
Test status
Simulation time	224832241 ps
CPU time	4.72 seconds
Started	Jan 10 01:10:46 PM PST 24
Finished	Jan 10 01:12:14 PM PST 24
Peak memory	207232 kb
Host	smart-c1a06e23-21a5-41bc-afbc-2fb4f6ab4fcc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711926616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.711926 616 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.2631112579
Short name	T207
Test name
Test status
Simulation time	48323419 ps
CPU time	1.27 seconds
Started	Jan 10 01:11:19 PM PST 24
Finished	Jan 10 01:12:43 PM PST 24
Peak memory	215492 kb
Host	smart-eef883af-fcb0-4e41-91d1-47a7a6461d83
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631112579 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.2631112579 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.3951832437
Short name	T166
Test name
Test status
Simulation time	71582327 ps
CPU time	0.97 seconds
Started	Jan 10 01:11:11 PM PST 24
Finished	Jan 10 01:12:38 PM PST 24
Peak memory	207012 kb
Host	smart-0fd666fd-41b2-4846-8ca6-f2155424f093
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951832437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.3951832437 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2248301972
Short name	T205
Test name
Test status
Simulation time	44696089 ps
CPU time	1.49 seconds
Started	Jan 10 01:11:08 PM PST 24
Finished	Jan 10 01:12:40 PM PST 24
Peak memory	215404 kb
Host	smart-9837a36d-b76c-4aa6-847a-5f645ca47eab
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248301972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.2248301972 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.4116486527
Short name	T48
Test name
Test status
Simulation time	36478197 ps
CPU time	1.02 seconds
Started	Jan 10 01:11:10 PM PST 24
Finished	Jan 10 01:12:35 PM PST 24
Peak memory	207084 kb
Host	smart-e5310f63-493c-4e73-a873-51a4860ec1b8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116486527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.4116486527 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3681468458
Short name	T55
Test name
Test status
Simulation time	102436545 ps
CPU time	1.63 seconds
Started	Jan 10 01:11:07 PM PST 24
Finished	Jan 10 01:12:34 PM PST 24
Peak memory	223668 kb
Host	smart-5ffe3f74-d155-48ae-8891-ae9c894ac370
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681468458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.3681468458 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.1749468216
Short name	T14
Test name
Test status
Simulation time	32931086 ps
CPU time	2.03 seconds
Started	Jan 10 01:11:19 PM PST 24
Finished	Jan 10 01:12:44 PM PST 24
Peak memory	223752 kb
Host	smart-b7a27fd2-d1d5-465d-921b-4e4c65f6b3a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749468216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1749468216 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.1954036860
Short name	T4
Test name
Test status
Simulation time	136011396 ps
CPU time	4.31 seconds
Started	Jan 10 01:11:40 PM PST 24
Finished	Jan 10 01:12:59 PM PST 24
Peak memory	215444 kb
Host	smart-69b71315-eaf6-4e71-9e43-414a15c57228
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954036860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1954 036860 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2497817835
Short name	T116
Test name
Test status
Simulation time	29683465 ps
CPU time	1.27 seconds
Started	Jan 10 01:11:08 PM PST 24
Finished	Jan 10 01:12:44 PM PST 24
Peak memory	215544 kb
Host	smart-deec7429-b78a-4365-851c-21a12cf53014
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497817835 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2497817835 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2143841641
Short name	T144
Test name
Test status
Simulation time	23271007 ps
CPU time	1.13 seconds
Started	Jan 10 01:11:04 PM PST 24
Finished	Jan 10 01:12:32 PM PST 24
Peak memory	207132 kb
Host	smart-98994680-4340-4a2b-b7c8-1c301a7b09fb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143841641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2143841641 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.2192651521
Short name	T127
Test name
Test status
Simulation time	122296668 ps
CPU time	0.72 seconds
Started	Jan 10 01:11:18 PM PST 24
Finished	Jan 10 01:12:44 PM PST 24
Peak memory	206944 kb
Host	smart-8fda2bbd-d6b2-413e-ae1a-43eeb519db29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192651521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2192651521 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1214729849
Short name	T62
Test name
Test status
Simulation time	125245309 ps
CPU time	2.72 seconds
Started	Jan 10 01:11:21 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	207232 kb
Host	smart-9df4aa60-9493-47ac-98ba-f1e21b8c9ccd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214729849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs r_outstanding.1214729849 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.4178032340
Short name	T132
Test name
Test status
Simulation time	115567661 ps
CPU time	1.13 seconds
Started	Jan 10 01:11:17 PM PST 24
Finished	Jan 10 01:12:41 PM PST 24
Peak memory	215776 kb
Host	smart-93b85c94-31f5-4762-8fde-c6f8cbdd832c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178032340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.4178032340 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.2533088766
Short name	T182
Test name
Test status
Simulation time	142373747 ps
CPU time	2.16 seconds
Started	Jan 10 01:11:06 PM PST 24
Finished	Jan 10 01:12:39 PM PST 24
Peak memory	215520 kb
Host	smart-930a9d31-971b-450f-90ec-01116bc28b38
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533088766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma c_shadow_reg_errors_with_csr_rw.2533088766 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.3150816986
Short name	T187
Test name
Test status
Simulation time	381952968 ps
CPU time	2.59 seconds
Started	Jan 10 01:11:37 PM PST 24
Finished	Jan 10 01:13:08 PM PST 24
Peak memory	218356 kb
Host	smart-1c70cb39-244b-4512-96b4-9af0c2d2b279
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150816986 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3150816986 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2908378445
Short name	T13
Test name
Test status
Simulation time	208795838 ps
CPU time	1.45 seconds
Started	Jan 10 01:11:39 PM PST 24
Finished	Jan 10 01:12:56 PM PST 24
Peak memory	215456 kb
Host	smart-efe8f840-3e9f-4ff9-b4b7-af3ecb734bbb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908378445 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2908378445 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.3759592498
Short name	T181
Test name
Test status
Simulation time	56874881 ps
CPU time	1.09 seconds
Started	Jan 10 01:11:09 PM PST 24
Finished	Jan 10 01:12:37 PM PST 24
Peak memory	215328 kb
Host	smart-47b01929-c6f5-4658-8542-737565b8ae1f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759592498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3759592498 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1575411807
Short name	T130
Test name
Test status
Simulation time	27825432 ps
CPU time	1.48 seconds
Started	Jan 10 01:11:07 PM PST 24
Finished	Jan 10 01:12:33 PM PST 24
Peak memory	215476 kb
Host	smart-614b53cf-e217-4446-9bae-14ac50a98fa8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575411807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.1575411807 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.318685242
Short name	T180
Test name
Test status
Simulation time	117066561 ps
CPU time	1.12 seconds
Started	Jan 10 01:11:17 PM PST 24
Finished	Jan 10 01:12:41 PM PST 24
Peak memory	215752 kb
Host	smart-4733f05e-80db-459e-a9a4-ef07cb6f7516
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318685242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_ errors.318685242 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.64428270
Short name	T196
Test name
Test status
Simulation time	568438136 ps
CPU time	2.87 seconds
Started	Jan 10 01:11:18 PM PST 24
Finished	Jan 10 01:12:46 PM PST 24
Peak memory	216024 kb
Host	smart-53cdfc62-5f4e-4a73-81f8-a2aa61e4defa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64428270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_ shadow_reg_errors_with_csr_rw.64428270 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2820578847
Short name	T81
Test name
Test status
Simulation time	286834207 ps
CPU time	4.93 seconds
Started	Jan 10 01:11:18 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	218296 kb
Host	smart-cf7f7e84-262e-4fb8-a66f-f83b6d2c8d83
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820578847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2820 578847 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.1056673798
Short name	T125
Test name
Test status
Simulation time	84552599 ps
CPU time	1.41 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	222900 kb
Host	smart-7f147ab8-dce4-4094-a8a7-03a3b45dd8ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056673798 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.1056673798 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2079301340
Short name	T89
Test name
Test status
Simulation time	13607385 ps
CPU time	0.9 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:47 PM PST 24
Peak memory	215472 kb
Host	smart-4d5eb7c3-b7b4-4bbe-8987-fac97858a24f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079301340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2079301340 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.2795031047
Short name	T102
Test name
Test status
Simulation time	53418479 ps
CPU time	0.73 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	207060 kb
Host	smart-a8315ab1-7d0c-476e-961b-2dca9f3d8292
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795031047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2795031047 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.517191905
Short name	T115
Test name
Test status
Simulation time	108756142 ps
CPU time	2.44 seconds
Started	Jan 10 01:11:26 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	215484 kb
Host	smart-18df6342-bc28-4c2d-af4a-a38533e56a27
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517191905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr _outstanding.517191905 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.1167580276
Short name	T82
Test name
Test status
Simulation time	114047589 ps
CPU time	1.48 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	215672 kb
Host	smart-c46f6270-4d15-4e27-a029-a07db19a294c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167580276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.1167580276 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.1135369225
Short name	T176
Test name
Test status
Simulation time	98162470 ps
CPU time	2.68 seconds
Started	Jan 10 01:11:29 PM PST 24
Finished	Jan 10 01:12:58 PM PST 24
Peak memory	223056 kb
Host	smart-50cc4717-0167-45ed-bcd2-a2b0f5d030a9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135369225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.1135369225 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.771122104
Short name	T18
Test name
Test status
Simulation time	125656729 ps
CPU time	3.21 seconds
Started	Jan 10 01:11:33 PM PST 24
Finished	Jan 10 01:12:56 PM PST 24
Peak memory	215652 kb
Host	smart-de148e50-0441-40ce-a9ed-dbd4653262f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771122104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.771122104 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.3227083691
Short name	T22
Test name
Test status
Simulation time	62476406 ps
CPU time	1.49 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	223740 kb
Host	smart-40da2677-8d63-4128-97f5-32c1edc1167e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227083691 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.3227083691 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.1113294393
Short name	T2
Test name
Test status
Simulation time	22323485 ps
CPU time	0.99 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	207236 kb
Host	smart-935917d5-e648-4f67-a87f-279ca881b8e3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113294393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.1113294393 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.846068294
Short name	T88
Test name
Test status
Simulation time	15031314 ps
CPU time	0.76 seconds
Started	Jan 10 01:11:26 PM PST 24
Finished	Jan 10 01:12:49 PM PST 24
Peak memory	207040 kb
Host	smart-e2063af9-6994-4721-b138-7a32b35376aa
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846068294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.846068294 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.429632810
Short name	T145
Test name
Test status
Simulation time	90039406 ps
CPU time	2.37 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:53 PM PST 24
Peak memory	215416 kb
Host	smart-e5335ffe-55f4-489f-bfe9-34f2a5810b5e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429632810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr _outstanding.429632810 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2922040963
Short name	T149
Test name
Test status
Simulation time	20401563 ps
CPU time	1.04 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:13:03 PM PST 24
Peak memory	215616 kb
Host	smart-75a264cc-9bad-4136-b496-608a04aeb22d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922040963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg _errors.2922040963 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4038799773
Short name	T148
Test name
Test status
Simulation time	80533840 ps
CPU time	2.18 seconds
Started	Jan 10 01:11:26 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	215544 kb
Host	smart-50d9b3af-de50-4cc7-9a9c-fac2f44c45fc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038799773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.4038799773 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.1304564087
Short name	T59
Test name
Test status
Simulation time	1257318888 ps
CPU time	2.17 seconds
Started	Jan 10 01:11:25 PM PST 24
Finished	Jan 10 01:12:55 PM PST 24
Peak memory	215572 kb
Host	smart-dfd93241-98e1-4f79-997c-254b92a75716
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304564087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1304564087 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.98776177
Short name	T20
Test name
Test status
Simulation time	45598706 ps
CPU time	2.23 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:49 PM PST 24
Peak memory	223520 kb
Host	smart-686746fe-ceb6-4d02-a23b-4d18ef153c2c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98776177 -assert nopostproc +UVM_TESTNAME=k mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.98776177 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.3919753196
Short name	T154
Test name
Test status
Simulation time	40475007 ps
CPU time	1.04 seconds
Started	Jan 10 01:11:29 PM PST 24
Finished	Jan 10 01:12:57 PM PST 24
Peak memory	207296 kb
Host	smart-cb9a4e89-9934-48d5-8a7c-a60dc7521864
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919753196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.3919753196 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.2645292360
Short name	T103
Test name
Test status
Simulation time	42109673 ps
CPU time	0.73 seconds
Started	Jan 10 01:11:38 PM PST 24
Finished	Jan 10 01:13:00 PM PST 24
Peak memory	207036 kb
Host	smart-da1efd4b-ac31-48b8-8496-f384e3c03f96
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645292360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2645292360 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.2671958883
Short name	T42
Test name
Test status
Simulation time	40707333 ps
CPU time	1.42 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:13:04 PM PST 24
Peak memory	215800 kb
Host	smart-3a048768-85e4-4030-9d0c-ca2cbfecf316
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671958883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.2671958883 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.809986689
Short name	T63
Test name
Test status
Simulation time	55570707 ps
CPU time	1.48 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	215820 kb
Host	smart-6b3bcc29-d2ea-4ff0-af81-bdfe0bc8a3fe
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809986689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_ errors.809986689 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.4138930958
Short name	T212
Test name
Test status
Simulation time	53132721 ps
CPU time	1.58 seconds
Started	Jan 10 01:11:38 PM PST 24
Finished	Jan 10 01:12:58 PM PST 24
Peak memory	215512 kb
Host	smart-de8ffd7f-1136-4142-80dc-8c754d02dcc7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138930958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.4138930958 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.3354676626
Short name	T68
Test name
Test status
Simulation time	91588077 ps
CPU time	1.55 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	215484 kb
Host	smart-0ae64482-eb5c-4eab-9aa3-24cefcf34437
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354676626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3354676626 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.2258138357
Short name	T74
Test name
Test status
Simulation time	200352049 ps
CPU time	4.47 seconds
Started	Jan 10 01:11:26 PM PST 24
Finished	Jan 10 01:12:53 PM PST 24
Peak memory	207220 kb
Host	smart-2b0e4dd6-c3af-498c-9530-5ac49f1ec7d3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258138357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.2258 138357 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.3010484051
Short name	T175
Test name
Test status
Simulation time	127254267 ps
CPU time	1.65 seconds
Started	Jan 10 01:11:29 PM PST 24
Finished	Jan 10 01:12:57 PM PST 24
Peak memory	223436 kb
Host	smart-1cb2ce15-04eb-45ef-977f-0ee7b5d7331b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010484051 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.3010484051 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.1943646613
Short name	T1
Test name
Test status
Simulation time	38246020 ps
CPU time	1.15 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	207248 kb
Host	smart-aa514f16-bf61-4b15-bb25-3981a789a916
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943646613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.1943646613 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.183001742
Short name	T96
Test name
Test status
Simulation time	20857661 ps
CPU time	0.76 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:47 PM PST 24
Peak memory	207076 kb
Host	smart-fd3ccde6-1c8b-4422-bfe1-aa21ae86fef3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183001742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.183001742 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.2934663344
Short name	T138
Test name
Test status
Simulation time	290681071 ps
CPU time	1.56 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:52 PM PST 24
Peak memory	215408 kb
Host	smart-b0f31c1e-7cec-452b-9b1c-f99ae9bda2d7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934663344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.2934663344 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.794832437
Short name	T37
Test name
Test status
Simulation time	67064829 ps
CPU time	1.44 seconds
Started	Jan 10 01:11:26 PM PST 24
Finished	Jan 10 01:12:49 PM PST 24
Peak memory	215756 kb
Host	smart-2efbe0b3-b783-40f4-b89f-bec3287dc2d5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794832437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_ errors.794832437 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.483426369
Short name	T118
Test name
Test status
Simulation time	122985860 ps
CPU time	1.63 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:51 PM PST 24
Peak memory	215992 kb
Host	smart-ca4aa625-2ffd-4bab-8bce-e12999448fa4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483426369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac _shadow_reg_errors_with_csr_rw.483426369 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.2000295817
Short name	T16
Test name
Test status
Simulation time	43745274 ps
CPU time	1.43 seconds
Started	Jan 10 01:11:28 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	215536 kb
Host	smart-1cdfa71e-a5d5-41a5-b14d-8e8cebad32a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000295817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2000295817 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.292270498
Short name	T97
Test name
Test status
Simulation time	67995508 ps
CPU time	1.59 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:12:51 PM PST 24
Peak memory	215348 kb
Host	smart-0f610f87-5710-4d9c-818e-3d0e5ccf86c2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292270498 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.292270498 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.780159925
Short name	T45
Test name
Test status
Simulation time	19468559 ps
CPU time	1.08 seconds
Started	Jan 10 01:11:41 PM PST 24
Finished	Jan 10 01:13:07 PM PST 24
Peak memory	207124 kb
Host	smart-e2a53bbf-302b-4eb6-8fba-97219c683e71
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780159925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.780159925 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.2776448285
Short name	T137
Test name
Test status
Simulation time	12148230 ps
CPU time	0.74 seconds
Started	Jan 10 01:11:30 PM PST 24
Finished	Jan 10 01:12:51 PM PST 24
Peak memory	207028 kb
Host	smart-1c9c80f4-f389-4b44-8bf1-9ba5b7f1e441
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776448285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.2776448285 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2316936217
Short name	T211
Test name
Test status
Simulation time	52711239 ps
CPU time	1.52 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:51 PM PST 24
Peak memory	215604 kb
Host	smart-5fc33858-c23b-4466-a615-fb1695678d48
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316936217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.2316936217 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3009663684
Short name	T24
Test name
Test status
Simulation time	173743458 ps
CPU time	1.2 seconds
Started	Jan 10 01:11:27 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	215876 kb
Host	smart-d6fcf524-871b-4ea2-83f8-058e7da09928
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009663684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg _errors.3009663684 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2528851779
Short name	T52
Test name
Test status
Simulation time	66310436 ps
CPU time	1.73 seconds
Started	Jan 10 01:11:29 PM PST 24
Finished	Jan 10 01:12:57 PM PST 24
Peak memory	215540 kb
Host	smart-5fa154b7-441e-459a-9e46-0b9b63fd6769
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528851779 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma c_shadow_reg_errors_with_csr_rw.2528851779 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.2678225038
Short name	T57
Test name
Test status
Simulation time	314761150 ps
CPU time	2.32 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:52 PM PST 24
Peak memory	215620 kb
Host	smart-a7b160c8-2c5d-46de-b6fe-63b312f3c43f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678225038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2678225038 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1222559031
Short name	T162
Test name
Test status
Simulation time	148226224 ps
CPU time	2.87 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:12:52 PM PST 24
Peak memory	215544 kb
Host	smart-dc9083b2-2219-472b-b675-b3ea0b7d18a6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222559031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1222 559031 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.2006221832
Short name	T21
Test name
Test status
Simulation time	21336101 ps
CPU time	1.15 seconds
Started	Jan 10 01:11:34 PM PST 24
Finished	Jan 10 01:12:55 PM PST 24
Peak memory	215500 kb
Host	smart-8edf4009-dbac-4558-9466-f052a26618c8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006221832 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.2006221832 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.1035005338
Short name	T159
Test name
Test status
Simulation time	90281059 ps
CPU time	0.93 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:13:03 PM PST 24
Peak memory	207080 kb
Host	smart-10206544-88ac-4328-8250-7aef5d13239b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035005338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1035005338 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.510654704
Short name	T25
Test name
Test status
Simulation time	15229170 ps
CPU time	0.73 seconds
Started	Jan 10 01:11:35 PM PST 24
Finished	Jan 10 01:12:59 PM PST 24
Peak memory	206988 kb
Host	smart-98f75da3-f96e-4e8d-aa29-c0cb3e5fe9dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510654704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.510654704 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2769923791
Short name	T32
Test name
Test status
Simulation time	24395412 ps
CPU time	1.44 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	215412 kb
Host	smart-912676ff-6c24-4aac-b2ae-b6961f78f5d4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769923791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.2769923791 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1466275761
Short name	T147
Test name
Test status
Simulation time	116033131 ps
CPU time	1.17 seconds
Started	Jan 10 01:11:41 PM PST 24
Finished	Jan 10 01:13:07 PM PST 24
Peak memory	215792 kb
Host	smart-bcabead8-eb3a-4414-902f-8b96854c4eb2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466275761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.1466275761 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.896196107
Short name	T101
Test name
Test status
Simulation time	250182999 ps
CPU time	1.85 seconds
Started	Jan 10 01:11:34 PM PST 24
Finished	Jan 10 01:12:55 PM PST 24
Peak memory	215860 kb
Host	smart-67426565-63db-4bc6-9d32-3969d2e346a7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896196107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac _shadow_reg_errors_with_csr_rw.896196107 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.3432412423
Short name	T199
Test name
Test status
Simulation time	82556566 ps
CPU time	2.47 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:12:55 PM PST 24
Peak memory	215464 kb
Host	smart-8d78516e-00d9-423b-8a26-0da4a9bc8aef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432412423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3432412423 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.230078195
Short name	T78
Test name
Test status
Simulation time	509332398 ps
CPU time	5.25 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:56 PM PST 24
Peak memory	215472 kb
Host	smart-94b83916-96fe-4512-9770-76b20304a284
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230078195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.23007 8195 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.1762044551
Short name	T203
Test name
Test status
Simulation time	21338566 ps
CPU time	1.18 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	215380 kb
Host	smart-be19d7d5-d9dc-4019-8365-5bf90410ba61
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762044551 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.1762044551 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.2192942576
Short name	T114
Test name
Test status
Simulation time	99712386 ps
CPU time	1.08 seconds
Started	Jan 10 01:11:44 PM PST 24
Finished	Jan 10 01:12:59 PM PST 24
Peak memory	207136 kb
Host	smart-cc45c7a0-7beb-4752-827b-eb1eb1f25b82
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192942576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2192942576 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.3977958832
Short name	T178
Test name
Test status
Simulation time	51981907 ps
CPU time	0.77 seconds
Started	Jan 10 01:12:05 PM PST 24
Finished	Jan 10 01:13:20 PM PST 24
Peak memory	207004 kb
Host	smart-f60254e7-550d-446c-964d-8f9d0934e495
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977958832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3977958832 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.153050262
Short name	T126
Test name
Test status
Simulation time	76880142 ps
CPU time	1.75 seconds
Started	Jan 10 01:11:30 PM PST 24
Finished	Jan 10 01:12:52 PM PST 24
Peak memory	215520 kb
Host	smart-dda4722d-dfa1-443b-84fd-7d9f9cdb7e09
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153050262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr _outstanding.153050262 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1032907577
Short name	T107
Test name
Test status
Simulation time	68519879 ps
CPU time	1.16 seconds
Started	Jan 10 01:11:34 PM PST 24
Finished	Jan 10 01:12:55 PM PST 24
Peak memory	207592 kb
Host	smart-a817f23c-9ccb-4073-b5d4-cc5be6446799
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032907577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.1032907577 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.683672714
Short name	T34
Test name
Test status
Simulation time	105235553 ps
CPU time	1.73 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:52 PM PST 24
Peak memory	215620 kb
Host	smart-a9192982-b025-4642-91cc-ecd1cb104991
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683672714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac _shadow_reg_errors_with_csr_rw.683672714 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.3426653937
Short name	T58
Test name
Test status
Simulation time	96871118 ps
CPU time	2.5 seconds
Started	Jan 10 01:11:35 PM PST 24
Finished	Jan 10 01:12:55 PM PST 24
Peak memory	215452 kb
Host	smart-000dd264-e045-4784-be20-e8c69dbf1f70
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426653937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.3426653937 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2231430352
Short name	T124
Test name
Test status
Simulation time	83181754 ps
CPU time	2.5 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:12:51 PM PST 24
Peak memory	215476 kb
Host	smart-378fcabb-b71e-4bc9-a96f-fbcbb0dc30af
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231430352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2231 430352 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.645002440
Short name	T213
Test name
Test status
Simulation time	231035924 ps
CPU time	8.87 seconds
Started	Jan 10 01:10:50 PM PST 24
Finished	Jan 10 01:12:33 PM PST 24
Peak memory	207224 kb
Host	smart-748b9a25-4ca2-4bb9-9d31-a62dcb8a8f6e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645002440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.64500244 0 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.37433022
Short name	T93
Test name
Test status
Simulation time	167083510 ps
CPU time	8.52 seconds
Started	Jan 10 01:10:52 PM PST 24
Finished	Jan 10 01:12:24 PM PST 24
Peak memory	207168 kb
Host	smart-7d04f780-9fbd-4a16-981d-de1e0c7db032
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37433022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.37433022 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1155390932
Short name	T95
Test name
Test status
Simulation time	36322948 ps
CPU time	1.1 seconds
Started	Jan 10 01:10:55 PM PST 24
Finished	Jan 10 01:12:20 PM PST 24
Peak memory	207204 kb
Host	smart-85e2671e-998d-491a-a782-b6e35d86c206
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155390932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1155390 932 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.1202670729
Short name	T150
Test name
Test status
Simulation time	196074059 ps
CPU time	1.96 seconds
Started	Jan 10 01:10:52 PM PST 24
Finished	Jan 10 01:12:20 PM PST 24
Peak memory	223656 kb
Host	smart-ed1ce1a4-5fb6-4aa1-aee7-28f343581219
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202670729 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.1202670729 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3312543389
Short name	T44
Test name
Test status
Simulation time	142094994 ps
CPU time	1.05 seconds
Started	Jan 10 01:10:45 PM PST 24
Finished	Jan 10 01:12:08 PM PST 24
Peak memory	215412 kb
Host	smart-17935ca9-b101-4118-9c26-d818212c5952
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312543389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3312543389 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.1922782142
Short name	T167
Test name
Test status
Simulation time	77534495 ps
CPU time	0.74 seconds
Started	Jan 10 01:10:37 PM PST 24
Finished	Jan 10 01:12:02 PM PST 24
Peak memory	206872 kb
Host	smart-019af915-6f47-47d4-a020-588749395d16
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922782142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.1922782142 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.403722237
Short name	T119
Test name
Test status
Simulation time	33746021 ps
CPU time	0.69 seconds
Started	Jan 10 01:10:50 PM PST 24
Finished	Jan 10 01:12:14 PM PST 24
Peak memory	207020 kb
Host	smart-cb117316-76f7-4799-a382-9583a3e11094
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403722237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.403722237 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3403670525
Short name	T191
Test name
Test status
Simulation time	80513715 ps
CPU time	1.38 seconds
Started	Jan 10 01:10:47 PM PST 24
Finished	Jan 10 01:12:13 PM PST 24
Peak memory	215356 kb
Host	smart-14d25238-b006-4501-932b-7c4659a501a4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403670525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr _outstanding.3403670525 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1549083877
Short name	T27
Test name
Test status
Simulation time	37224542 ps
CPU time	1 seconds
Started	Jan 10 01:11:07 PM PST 24
Finished	Jan 10 01:12:33 PM PST 24
Peak memory	215508 kb
Host	smart-69c16582-74dd-4d8a-944f-49ee83d8d024
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549083877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.1549083877 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.1253704728
Short name	T197
Test name
Test status
Simulation time	48007878 ps
CPU time	1.54 seconds
Started	Jan 10 01:11:07 PM PST 24
Finished	Jan 10 01:12:33 PM PST 24
Peak memory	207276 kb
Host	smart-e6d1b77d-0c88-4095-ab4b-ce5880c305a6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253704728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac _shadow_reg_errors_with_csr_rw.1253704728 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.2735519342
Short name	T184
Test name
Test status
Simulation time	88511272 ps
CPU time	2.47 seconds
Started	Jan 10 01:11:06 PM PST 24
Finished	Jan 10 01:12:43 PM PST 24
Peak memory	215556 kb
Host	smart-608d4a38-e6d9-475e-b932-262fdb6c0733
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735519342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.2735519342 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1386287463
Short name	T72
Test name
Test status
Simulation time	831575827 ps
CPU time	4.74 seconds
Started	Jan 10 01:10:42 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	215484 kb
Host	smart-8585c69f-19a6-4ccd-814a-dc66746b004f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386287463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.13862 87463 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.1352726772
Short name	T169
Test name
Test status
Simulation time	164612152 ps
CPU time	0.73 seconds
Started	Jan 10 01:11:40 PM PST 24
Finished	Jan 10 01:12:55 PM PST 24
Peak memory	207020 kb
Host	smart-0de5705a-d45c-4449-9804-be4a605aef60
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352726772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1352726772 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.3136236413
Short name	T158
Test name
Test status
Simulation time	10535875 ps
CPU time	0.74 seconds
Started	Jan 10 01:12:00 PM PST 24
Finished	Jan 10 01:13:13 PM PST 24
Peak memory	206928 kb
Host	smart-8fba189c-83ca-4d66-920a-c3366a5d2a6d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136236413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.3136236413 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.520101568
Short name	T70
Test name
Test status
Simulation time	15897505 ps
CPU time	0.75 seconds
Started	Jan 10 01:11:43 PM PST 24
Finished	Jan 10 01:12:59 PM PST 24
Peak memory	206948 kb
Host	smart-a5cbcdcf-f5ec-4574-9aa0-50f0c8c676e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520101568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.520101568 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.1543181469
Short name	T123
Test name
Test status
Simulation time	44344517 ps
CPU time	0.77 seconds
Started	Jan 10 01:11:37 PM PST 24
Finished	Jan 10 01:12:54 PM PST 24
Peak memory	207068 kb
Host	smart-2f1ded10-536c-48a8-8ffc-98c12718d4bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543181469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1543181469 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.667759960
Short name	T143
Test name
Test status
Simulation time	40233212 ps
CPU time	0.75 seconds
Started	Jan 10 01:11:37 PM PST 24
Finished	Jan 10 01:12:53 PM PST 24
Peak memory	207072 kb
Host	smart-84faa797-1bed-4eb8-b781-0f0c4ff2bffb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667759960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.667759960 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.1553676863
Short name	T71
Test name
Test status
Simulation time	33381981 ps
CPU time	0.74 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:13:03 PM PST 24
Peak memory	207056 kb
Host	smart-2162862c-b3a7-4037-adc4-c87a3d88e970
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553676863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.1553676863 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.220701128
Short name	T189
Test name
Test status
Simulation time	162054983 ps
CPU time	0.76 seconds
Started	Jan 10 01:11:58 PM PST 24
Finished	Jan 10 01:13:12 PM PST 24
Peak memory	207052 kb
Host	smart-3d63278f-3826-4bdb-b26b-baa57df8c37a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220701128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.220701128 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.1865846731
Short name	T146
Test name
Test status
Simulation time	13437068 ps
CPU time	0.83 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	207056 kb
Host	smart-921ab2a0-0c40-4359-9788-cacc7ee580c1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865846731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.1865846731 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.3393532591
Short name	T105
Test name
Test status
Simulation time	31524546 ps
CPU time	0.74 seconds
Started	Jan 10 01:11:41 PM PST 24
Finished	Jan 10 01:13:07 PM PST 24
Peak memory	207052 kb
Host	smart-85469af1-c672-4c74-889b-148006520ea7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393532591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3393532591 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.13051502
Short name	T69
Test name
Test status
Simulation time	15965085 ps
CPU time	0.76 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:52 PM PST 24
Peak memory	207052 kb
Host	smart-65fc3aac-dd0c-4f4a-87db-e09ed2af6626
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13051502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.13051502 +enable_mas king=0 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.1711392413
Short name	T209
Test name
Test status
Simulation time	572126515 ps
CPU time	10.55 seconds
Started	Jan 10 01:10:49 PM PST 24
Finished	Jan 10 01:12:23 PM PST 24
Peak memory	215344 kb
Host	smart-02141777-e98d-4fb8-b531-1086226ba49d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711392413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.1711392 413 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2915173558
Short name	T64
Test name
Test status
Simulation time	816265580 ps
CPU time	11.74 seconds
Started	Jan 10 01:10:44 PM PST 24
Finished	Jan 10 01:12:19 PM PST 24
Peak memory	207380 kb
Host	smart-d3d575dc-ae2c-4ed7-8c2f-46bf6fc6c145
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915173558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2915173 558 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.3461709309
Short name	T122
Test name
Test status
Simulation time	33395121 ps
CPU time	0.96 seconds
Started	Jan 10 01:10:52 PM PST 24
Finished	Jan 10 01:12:16 PM PST 24
Peak memory	207072 kb
Host	smart-57934651-5d48-4766-bd8e-f7ae81f96af3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461709309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.3461709 309 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3801967575
Short name	T161
Test name
Test status
Simulation time	214826260 ps
CPU time	1.61 seconds
Started	Jan 10 01:11:20 PM PST 24
Finished	Jan 10 01:12:44 PM PST 24
Peak memory	215480 kb
Host	smart-7b0e39a8-36c4-4a7e-8fc8-23cc9076dacd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801967575 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3801967575 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.983757753
Short name	T157
Test name
Test status
Simulation time	14667835 ps
CPU time	0.92 seconds
Started	Jan 10 01:10:51 PM PST 24
Finished	Jan 10 01:12:14 PM PST 24
Peak memory	207220 kb
Host	smart-204bd57b-2d93-43e8-add6-b99e95c7f12e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983757753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.983757753 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.2215743258
Short name	T133
Test name
Test status
Simulation time	45347020 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:49 PM PST 24
Finished	Jan 10 01:12:16 PM PST 24
Peak memory	206940 kb
Host	smart-90ba67ae-b2e4-4459-8d3c-dabcf750d0f0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215743258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.2215743258 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2020056600
Short name	T38
Test name
Test status
Simulation time	28151489 ps
CPU time	1.04 seconds
Started	Jan 10 01:11:00 PM PST 24
Finished	Jan 10 01:12:26 PM PST 24
Peak memory	215392 kb
Host	smart-7e4c26f9-c5a1-45b9-aa21-7e042ba5faf7
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020056600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.2020056600 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1058916137
Short name	T128
Test name
Test status
Simulation time	21909134 ps
CPU time	0.7 seconds
Started	Jan 10 01:11:02 PM PST 24
Finished	Jan 10 01:12:28 PM PST 24
Peak memory	206976 kb
Host	smart-5e185c62-2491-4e7d-a0d4-8c4cb62bc15c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058916137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1058916137 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.3049249622
Short name	T170
Test name
Test status
Simulation time	351256629 ps
CPU time	2.65 seconds
Started	Jan 10 01:11:00 PM PST 24
Finished	Jan 10 01:12:28 PM PST 24
Peak memory	215532 kb
Host	smart-87d7539d-f3e3-48fa-bed9-cf842e6aacac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049249622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr _outstanding.3049249622 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.503547060
Short name	T108
Test name
Test status
Simulation time	26219226 ps
CPU time	1.04 seconds
Started	Jan 10 01:10:48 PM PST 24
Finished	Jan 10 01:12:13 PM PST 24
Peak memory	215748 kb
Host	smart-e09a26af-9bce-4bbb-bc01-b339000e7f98
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503547060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e rrors.503547060 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.954562763
Short name	T204
Test name
Test status
Simulation time	73462500 ps
CPU time	2 seconds
Started	Jan 10 01:10:49 PM PST 24
Finished	Jan 10 01:12:14 PM PST 24
Peak memory	223940 kb
Host	smart-d254e349-1688-48ca-a02a-78dcb0efa128
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954562763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_ shadow_reg_errors_with_csr_rw.954562763 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.1100574708
Short name	T201
Test name
Test status
Simulation time	118611436 ps
CPU time	2.04 seconds
Started	Jan 10 01:11:06 PM PST 24
Finished	Jan 10 01:12:35 PM PST 24
Peak memory	215568 kb
Host	smart-02f5d246-597f-4a1d-a986-42758c117971
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100574708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1100574708 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.100921408
Short name	T77
Test name
Test status
Simulation time	261657046 ps
CPU time	3.02 seconds
Started	Jan 10 01:10:51 PM PST 24
Finished	Jan 10 01:12:16 PM PST 24
Peak memory	215560 kb
Host	smart-30399767-6fe4-45cc-8495-d185f91b1f16
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100921408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.100921 408 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.1303279396
Short name	T111
Test name
Test status
Simulation time	43608316 ps
CPU time	0.74 seconds
Started	Jan 10 01:12:00 PM PST 24
Finished	Jan 10 01:13:12 PM PST 24
Peak memory	206996 kb
Host	smart-8329f667-0e2a-409c-a523-866ed314de57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303279396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1303279396 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.450781776
Short name	T156
Test name
Test status
Simulation time	55995972 ps
CPU time	0.77 seconds
Started	Jan 10 01:11:32 PM PST 24
Finished	Jan 10 01:13:03 PM PST 24
Peak memory	206892 kb
Host	smart-a765d114-31dd-401f-b343-9c739dc8e6d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450781776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.450781776 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.604809919
Short name	T134
Test name
Test status
Simulation time	27005040 ps
CPU time	0.71 seconds
Started	Jan 10 01:12:00 PM PST 24
Finished	Jan 10 01:13:12 PM PST 24
Peak memory	206968 kb
Host	smart-c3a023de-252b-4e44-ab92-2a2d80416bba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604809919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.604809919 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.2224513914
Short name	T183
Test name
Test status
Simulation time	15232439 ps
CPU time	0.76 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	207012 kb
Host	smart-b324c158-29c2-4648-8fe1-4495999986bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224513914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.2224513914 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.501264238
Short name	T67
Test name
Test status
Simulation time	37209604 ps
CPU time	0.75 seconds
Started	Jan 10 01:11:40 PM PST 24
Finished	Jan 10 01:12:56 PM PST 24
Peak memory	206948 kb
Host	smart-fc6e6b6a-3b28-42ee-8ae1-21bc05c99025
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501264238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.501264238 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.2927066170
Short name	T100
Test name
Test status
Simulation time	25805715 ps
CPU time	0.76 seconds
Started	Jan 10 01:12:02 PM PST 24
Finished	Jan 10 01:13:16 PM PST 24
Peak memory	206984 kb
Host	smart-07ab307d-b53a-44d8-a58f-ed0a9c114137
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927066170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.2927066170 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.162321026
Short name	T121
Test name
Test status
Simulation time	50773513 ps
CPU time	0.77 seconds
Started	Jan 10 01:30:42 PM PST 24
Finished	Jan 10 01:30:43 PM PST 24
Peak memory	207052 kb
Host	smart-5bb0890d-0bb8-4f3b-9508-b56fbe265a8b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162321026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.162321026 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.1840537675
Short name	T171
Test name
Test status
Simulation time	20553955 ps
CPU time	0.84 seconds
Started	Jan 10 01:50:51 PM PST 24
Finished	Jan 10 01:50:53 PM PST 24
Peak memory	206996 kb
Host	smart-e0d2a1f5-8fe4-419b-85a4-c8990ad637f4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840537675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1840537675 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.678164472
Short name	T85
Test name
Test status
Simulation time	27314664 ps
CPU time	0.76 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	207032 kb
Host	smart-4b8b3981-85d4-4504-9129-b1d8e7ed5e21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678164472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.678164472 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.1008800299
Short name	T23
Test name
Test status
Simulation time	40604149 ps
CPU time	0.74 seconds
Started	Jan 10 01:11:31 PM PST 24
Finished	Jan 10 01:12:50 PM PST 24
Peak memory	207020 kb
Host	smart-33b88ebb-a02a-4581-bc25-db5d9cb84b64
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008800299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.1008800299 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.455807912
Short name	T155
Test name
Test status
Simulation time	445118608 ps
CPU time	10.54 seconds
Started	Jan 10 01:11:00 PM PST 24
Finished	Jan 10 01:12:36 PM PST 24
Peak memory	207352 kb
Host	smart-8f9ae452-3e7b-46a6-a4ca-5f42267097f9
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455807912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.45580791 2 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3684800640
Short name	T192
Test name
Test status
Simulation time	819146676 ps
CPU time	11.62 seconds
Started	Jan 10 01:11:05 PM PST 24
Finished	Jan 10 01:12:42 PM PST 24
Peak memory	207424 kb
Host	smart-6b5c3e51-b051-4e07-8df0-ea57c2521660
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684800640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3684800 640 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.4126534413
Short name	T135
Test name
Test status
Simulation time	69008194 ps
CPU time	1.14 seconds
Started	Jan 10 01:11:23 PM PST 24
Finished	Jan 10 01:12:45 PM PST 24
Peak memory	215480 kb
Host	smart-83a9ce81-2ec3-4ba4-be4e-efa6cd621c71
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126534413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.4126534 413 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.3131895515
Short name	T29
Test name
Test status
Simulation time	32624096 ps
CPU time	1.93 seconds
Started	Jan 10 01:10:57 PM PST 24
Finished	Jan 10 01:12:24 PM PST 24
Peak memory	223720 kb
Host	smart-46436227-2e72-4267-ba9b-a3139c1c7461
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131895515 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.3131895515 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.3833234235
Short name	T33
Test name
Test status
Simulation time	85497108 ps
CPU time	1.1 seconds
Started	Jan 10 01:10:57 PM PST 24
Finished	Jan 10 01:12:23 PM PST 24
Peak memory	207316 kb
Host	smart-54faeaff-27ce-4650-aa0c-ad3b7824ff70
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833234235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.3833234235 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.3783795626
Short name	T151
Test name
Test status
Simulation time	49242563 ps
CPU time	0.8 seconds
Started	Jan 10 01:10:49 PM PST 24
Finished	Jan 10 01:12:16 PM PST 24
Peak memory	207080 kb
Host	smart-89d31109-c9b1-404a-b5e5-fd17124c40c1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783795626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3783795626 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3290165687
Short name	T11
Test name
Test status
Simulation time	49571191 ps
CPU time	1.2 seconds
Started	Jan 10 01:10:57 PM PST 24
Finished	Jan 10 01:12:23 PM PST 24
Peak memory	215368 kb
Host	smart-78280bd1-e0bc-4678-ae44-4a5269ddbb9e
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290165687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.3290165687 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.2930679538
Short name	T110
Test name
Test status
Simulation time	15703411 ps
CPU time	0.67 seconds
Started	Jan 10 01:11:12 PM PST 24
Finished	Jan 10 01:12:38 PM PST 24
Peak memory	206856 kb
Host	smart-5c24dfef-fb19-4063-a0f7-3b822849edb7
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930679538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.2930679538 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.2852949696
Short name	T109
Test name
Test status
Simulation time	44379067 ps
CPU time	2.37 seconds
Started	Jan 10 01:10:51 PM PST 24
Finished	Jan 10 01:12:17 PM PST 24
Peak memory	215532 kb
Host	smart-0ce31c43-80a3-4069-abcb-d103351acb03
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852949696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr _outstanding.2852949696 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3064548756
Short name	T53
Test name
Test status
Simulation time	116749838 ps
CPU time	1.08 seconds
Started	Jan 10 01:10:57 PM PST 24
Finished	Jan 10 01:12:26 PM PST 24
Peak memory	215816 kb
Host	smart-a8fc1ef8-02cb-4778-894e-e875e5b474f0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064548756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.3064548756 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.2963628878
Short name	T51
Test name
Test status
Simulation time	437613116 ps
CPU time	2.95 seconds
Started	Jan 10 01:10:53 PM PST 24
Finished	Jan 10 01:12:24 PM PST 24
Peak memory	223288 kb
Host	smart-8d1c5891-5a31-4b1c-977b-95aa59f3d223
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963628878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.2963628878 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.121104051
Short name	T76
Test name
Test status
Simulation time	605060070 ps
CPU time	4.15 seconds
Started	Jan 10 01:10:55 PM PST 24
Finished	Jan 10 01:12:28 PM PST 24
Peak memory	207232 kb
Host	smart-904d88fe-e6fc-4dac-8eb8-86e333d2245d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121104051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.121104 051 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.966413135
Short name	T168
Test name
Test status
Simulation time	52010850 ps
CPU time	0.72 seconds
Started	Jan 10 01:11:29 PM PST 24
Finished	Jan 10 01:12:57 PM PST 24
Peak memory	207048 kb
Host	smart-f758cf6f-decd-4f58-9f53-b7a233422105
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966413135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.966413135 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.379283909
Short name	T139
Test name
Test status
Simulation time	43770278 ps
CPU time	0.73 seconds
Started	Jan 10 01:11:42 PM PST 24
Finished	Jan 10 01:13:07 PM PST 24
Peak memory	206908 kb
Host	smart-46dde007-97b7-4724-9647-b9fde3eea88a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379283909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.379283909 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.4282610113
Short name	T214
Test name
Test status
Simulation time	42770432 ps
CPU time	0.73 seconds
Started	Jan 10 01:12:01 PM PST 24
Finished	Jan 10 01:13:15 PM PST 24
Peak memory	207040 kb
Host	smart-89f1526c-6427-4865-b648-e4ae9d992e77
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282610113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.4282610113 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.2274111536
Short name	T66
Test name
Test status
Simulation time	19304301 ps
CPU time	0.79 seconds
Started	Jan 10 01:11:52 PM PST 24
Finished	Jan 10 01:13:16 PM PST 24
Peak memory	207036 kb
Host	smart-ab9ff221-29e0-45d5-bc6f-ef7afad09a52
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274111536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.2274111536 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.1108706830
Short name	T185
Test name
Test status
Simulation time	80223790 ps
CPU time	0.75 seconds
Started	Jan 10 01:11:47 PM PST 24
Finished	Jan 10 01:13:02 PM PST 24
Peak memory	207060 kb
Host	smart-2a788b5d-4678-4e47-8a84-2cbf08b12997
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108706830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.1108706830 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.2321430788
Short name	T8
Test name
Test status
Simulation time	18932239 ps
CPU time	0.78 seconds
Started	Jan 10 01:11:48 PM PST 24
Finished	Jan 10 01:13:02 PM PST 24
Peak memory	207048 kb
Host	smart-0a35b754-c3d5-44af-b5a3-f1601f456b3b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321430788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2321430788 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.4079616844
Short name	T90
Test name
Test status
Simulation time	12730111 ps
CPU time	0.75 seconds
Started	Jan 10 01:11:47 PM PST 24
Finished	Jan 10 01:13:13 PM PST 24
Peak memory	207100 kb
Host	smart-1ebc28e3-4df7-4603-a237-4ac8a5d7aff0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079616844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.4079616844 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2437202556
Short name	T87
Test name
Test status
Simulation time	19710252 ps
CPU time	0.81 seconds
Started	Jan 10 01:11:48 PM PST 24
Finished	Jan 10 01:13:07 PM PST 24
Peak memory	207016 kb
Host	smart-65a9eefd-08df-483f-bfac-6c2cb45c98d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437202556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2437202556 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.2719894999
Short name	T131
Test name
Test status
Simulation time	24338558 ps
CPU time	0.76 seconds
Started	Jan 10 01:11:47 PM PST 24
Finished	Jan 10 01:13:13 PM PST 24
Peak memory	206908 kb
Host	smart-43793ada-4aab-4549-8702-1e98e229ba54
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719894999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2719894999 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.3469549091
Short name	T104
Test name
Test status
Simulation time	36988970 ps
CPU time	1.75 seconds
Started	Jan 10 01:10:56 PM PST 24
Finished	Jan 10 01:12:26 PM PST 24
Peak memory	223468 kb
Host	smart-9ba9e039-dc7f-4b63-9e0b-44019e0717e6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469549091 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.3469549091 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.2666890273
Short name	T186
Test name
Test status
Simulation time	59732079 ps
CPU time	0.93 seconds
Started	Jan 10 01:10:48 PM PST 24
Finished	Jan 10 01:12:13 PM PST 24
Peak memory	206968 kb
Host	smart-a5976d3d-44ee-4aae-ad09-aada14221614
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666890273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.2666890273 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.2461538091
Short name	T3
Test name
Test status
Simulation time	56742912 ps
CPU time	0.74 seconds
Started	Jan 10 01:10:59 PM PST 24
Finished	Jan 10 01:12:26 PM PST 24
Peak memory	206968 kb
Host	smart-80a8c4c2-cb79-4625-901c-6073fe672bfb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461538091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2461538091 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.3181248224
Short name	T46
Test name
Test status
Simulation time	75808695 ps
CPU time	2.14 seconds
Started	Jan 10 01:11:30 PM PST 24
Finished	Jan 10 01:12:52 PM PST 24
Peak memory	215452 kb
Host	smart-ea69629b-a482-4407-8c96-29de194dcbe8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181248224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.3181248224 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2385418747
Short name	T49
Test name
Test status
Simulation time	368133437 ps
CPU time	1.12 seconds
Started	Jan 10 01:10:52 PM PST 24
Finished	Jan 10 01:12:17 PM PST 24
Peak memory	215832 kb
Host	smart-043c57b9-d3ec-4150-8e88-7be95f73fb4b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385418747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.2385418747 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3368436262
Short name	T193
Test name
Test status
Simulation time	37085243 ps
CPU time	1.77 seconds
Started	Jan 10 01:11:20 PM PST 24
Finished	Jan 10 01:12:44 PM PST 24
Peak memory	215780 kb
Host	smart-9116deda-efad-4993-8a86-1e8e9efeee2d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368436262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.3368436262 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.1734251698
Short name	T210
Test name
Test status
Simulation time	38233938 ps
CPU time	2.16 seconds
Started	Jan 10 01:10:54 PM PST 24
Finished	Jan 10 01:12:23 PM PST 24
Peak memory	215536 kb
Host	smart-c7b889f7-2c0e-4673-a10a-5cfddaf28b50
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734251698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1734251698 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.2379607149
Short name	T202
Test name
Test status
Simulation time	243864167 ps
CPU time	5.14 seconds
Started	Jan 10 01:10:53 PM PST 24
Finished	Jan 10 01:12:26 PM PST 24
Peak memory	215368 kb
Host	smart-8c089c2a-ab96-4b8d-8676-cf71f672879a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379607149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.23796 07149 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2268245900
Short name	T160
Test name
Test status
Simulation time	34172578 ps
CPU time	1.5 seconds
Started	Jan 10 01:11:03 PM PST 24
Finished	Jan 10 01:12:30 PM PST 24
Peak memory	215392 kb
Host	smart-443172f9-c5e9-4b2b-8981-8149430d7a31
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268245900 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2268245900 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3941747308
Short name	T43
Test name
Test status
Simulation time	27483111 ps
CPU time	1.1 seconds
Started	Jan 10 01:10:57 PM PST 24
Finished	Jan 10 01:12:26 PM PST 24
Peak memory	207308 kb
Host	smart-5448ed57-369e-4af9-8d0c-0c1dc1ee42fe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941747308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3941747308 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.2413834319
Short name	T41
Test name
Test status
Simulation time	35894888 ps
CPU time	0.72 seconds
Started	Jan 10 01:11:00 PM PST 24
Finished	Jan 10 01:12:27 PM PST 24
Peak memory	206948 kb
Host	smart-ff7908d3-8a4f-43a3-baaa-83bcad06e6dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413834319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2413834319 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.437616895
Short name	T35
Test name
Test status
Simulation time	203444451 ps
CPU time	2.56 seconds
Started	Jan 10 01:10:50 PM PST 24
Finished	Jan 10 01:12:16 PM PST 24
Peak memory	215448 kb
Host	smart-cd6a77a2-fe28-4777-84d4-04cc409e836c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437616895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_ outstanding.437616895 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.2398013696
Short name	T54
Test name
Test status
Simulation time	87287143 ps
CPU time	1.23 seconds
Started	Jan 10 01:10:49 PM PST 24
Finished	Jan 10 01:12:13 PM PST 24
Peak memory	215840 kb
Host	smart-c4927902-9be2-4c28-bcda-2268098441c8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398013696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_ errors.2398013696 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3492743573
Short name	T50
Test name
Test status
Simulation time	50307431 ps
CPU time	2.24 seconds
Started	Jan 10 01:10:52 PM PST 24
Finished	Jan 10 01:12:17 PM PST 24
Peak memory	223612 kb
Host	smart-a9680bd9-e738-4090-9ebe-ca6a1b02498b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492743573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.3492743573 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.1884448311
Short name	T19
Test name
Test status
Simulation time	24065910 ps
CPU time	1.56 seconds
Started	Jan 10 01:10:45 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	215700 kb
Host	smart-21cad84b-6700-4eb1-a977-e6cc1ed8d237
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884448311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.1884448311 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1297083757
Short name	T208
Test name
Test status
Simulation time	275808020 ps
CPU time	4.94 seconds
Started	Jan 10 01:10:57 PM PST 24
Finished	Jan 10 01:12:27 PM PST 24
Peak memory	207364 kb
Host	smart-64b3d2de-d72f-477e-a5fc-51fdd5f680a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297083757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.12970 83757 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1270887954
Short name	T152
Test name
Test status
Simulation time	322136478 ps
CPU time	1.86 seconds
Started	Jan 10 01:11:16 PM PST 24
Finished	Jan 10 01:12:41 PM PST 24
Peak memory	223604 kb
Host	smart-bf5189eb-838b-4f6f-8097-075c675aea4a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270887954 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.1270887954 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.1733658239
Short name	T194
Test name
Test status
Simulation time	32649529 ps
CPU time	1.15 seconds
Started	Jan 10 01:10:57 PM PST 24
Finished	Jan 10 01:12:26 PM PST 24
Peak memory	215360 kb
Host	smart-ca1324b3-f001-4758-a436-b4bacefa66f7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733658239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1733658239 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.1481427704
Short name	T206
Test name
Test status
Simulation time	45856905 ps
CPU time	0.76 seconds
Started	Jan 10 01:10:55 PM PST 24
Finished	Jan 10 01:12:19 PM PST 24
Peak memory	207040 kb
Host	smart-b247a9b4-9c33-44eb-a2dc-2a8d2e49e56c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481427704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1481427704 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.69551780
Short name	T142
Test name
Test status
Simulation time	81173923 ps
CPU time	1.42 seconds
Started	Jan 10 01:11:09 PM PST 24
Finished	Jan 10 01:12:35 PM PST 24
Peak memory	215384 kb
Host	smart-3827c1a6-0d91-40ed-ab1c-d200ef85e5a1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69551780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_o utstanding.69551780 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.47427169
Short name	T198
Test name
Test status
Simulation time	195796524 ps
CPU time	2.83 seconds
Started	Jan 10 01:11:00 PM PST 24
Finished	Jan 10 01:12:28 PM PST 24
Peak memory	216092 kb
Host	smart-39625ae0-e3a1-4f30-8211-567948434ed8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47427169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_s hadow_reg_errors_with_csr_rw.47427169 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.975726116
Short name	T56
Test name
Test status
Simulation time	496664761 ps
CPU time	3.56 seconds
Started	Jan 10 01:10:44 PM PST 24
Finished	Jan 10 01:12:10 PM PST 24
Peak memory	215700 kb
Host	smart-dbd13612-fd5c-47af-a055-adcf5c3cfd8a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975726116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.975726116 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1299731507
Short name	T79
Test name
Test status
Simulation time	551539131 ps
CPU time	5.74 seconds
Started	Jan 10 01:10:58 PM PST 24
Finished	Jan 10 01:12:32 PM PST 24
Peak memory	215476 kb
Host	smart-b3c95618-1bf5-453d-b9a8-58ce4d24f284
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299731507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.12997 31507 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.274246193
Short name	T140
Test name
Test status
Simulation time	21509266 ps
CPU time	1.98 seconds
Started	Jan 10 01:11:06 PM PST 24
Finished	Jan 10 01:12:39 PM PST 24
Peak memory	223408 kb
Host	smart-f6a4eca1-10d9-4b37-836c-42a5f716638d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274246193 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.274246193 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.3111731626
Short name	T60
Test name
Test status
Simulation time	299099815 ps
CPU time	0.97 seconds
Started	Jan 10 01:11:09 PM PST 24
Finished	Jan 10 01:12:35 PM PST 24
Peak memory	206968 kb
Host	smart-dee98abe-ecaf-48cf-b825-165413872a9c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111731626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3111731626 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.675182617
Short name	T164
Test name
Test status
Simulation time	36749016 ps
CPU time	0.74 seconds
Started	Jan 10 01:11:16 PM PST 24
Finished	Jan 10 01:12:39 PM PST 24
Peak memory	207084 kb
Host	smart-65197ca8-8e08-4428-ac04-08cb306bb91a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675182617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.675182617 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.511275587
Short name	T174
Test name
Test status
Simulation time	290485438 ps
CPU time	1.69 seconds
Started	Jan 10 01:11:07 PM PST 24
Finished	Jan 10 01:12:34 PM PST 24
Peak memory	215556 kb
Host	smart-1c151e9e-04e6-413a-8ef9-4299f8ae8f3f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511275587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_ outstanding.511275587 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.3444978700
Short name	T9
Test name
Test status
Simulation time	111778309 ps
CPU time	1.04 seconds
Started	Jan 10 01:11:28 PM PST 24
Finished	Jan 10 01:12:48 PM PST 24
Peak memory	215736 kb
Host	smart-318d78b2-9358-4d2f-af16-778a6e4d4f77
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444978700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_ errors.3444978700 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.1801508319
Short name	T136
Test name
Test status
Simulation time	59400993 ps
CPU time	2.55 seconds
Started	Jan 10 01:11:38 PM PST 24
Finished	Jan 10 01:13:02 PM PST 24
Peak memory	223144 kb
Host	smart-d875b064-0b2d-4676-bedb-562dec757193
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801508319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.1801508319 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.1579294157
Short name	T215
Test name
Test status
Simulation time	118842159 ps
CPU time	2.09 seconds
Started	Jan 10 01:11:11 PM PST 24
Finished	Jan 10 01:12:39 PM PST 24
Peak memory	215456 kb
Host	smart-ce29c5f9-73de-4769-b195-c9ebac5f9b4c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579294157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.1579294157 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.1396851619
Short name	T28
Test name
Test status
Simulation time	98388484 ps
CPU time	3.94 seconds
Started	Jan 10 01:11:37 PM PST 24
Finished	Jan 10 01:12:57 PM PST 24
Peak memory	217940 kb
Host	smart-4cc6df51-9711-4a17-b625-e97395baccd3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396851619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.13968 51619 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.4008065992
Short name	T120
Test name
Test status
Simulation time	21197590 ps
CPU time	1.22 seconds
Started	Jan 10 01:11:08 PM PST 24
Finished	Jan 10 01:12:44 PM PST 24
Peak memory	215404 kb
Host	smart-53a6667a-8085-4b5b-b462-f9da3c11ec0f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008065992 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.4008065992 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.349123721
Short name	T112
Test name
Test status
Simulation time	39862893 ps
CPU time	0.91 seconds
Started	Jan 10 01:11:41 PM PST 24
Finished	Jan 10 01:13:07 PM PST 24
Peak memory	207036 kb
Host	smart-bb533c77-02f4-44dd-becc-fb80e7c96a88
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349123721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.349123721 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.1391636373
Short name	T7
Test name
Test status
Simulation time	19686012 ps
CPU time	0.73 seconds
Started	Jan 10 01:11:09 PM PST 24
Finished	Jan 10 01:12:37 PM PST 24
Peak memory	207076 kb
Host	smart-bfbe3206-a296-4995-8bbe-e2d0bb44a013
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391636373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1391636373 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2560324179
Short name	T188
Test name
Test status
Simulation time	50728924 ps
CPU time	1.58 seconds
Started	Jan 10 01:11:17 PM PST 24
Finished	Jan 10 01:12:41 PM PST 24
Peak memory	215404 kb
Host	smart-f2760a98-025f-4d5d-96cb-aee8dbe5ded5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560324179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr _outstanding.2560324179 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3828162532
Short name	T179
Test name
Test status
Simulation time	37238672 ps
CPU time	1.16 seconds
Started	Jan 10 01:11:18 PM PST 24
Finished	Jan 10 01:12:44 PM PST 24
Peak memory	215740 kb
Host	smart-01f27ebd-6183-4e04-8efc-cadc3afdc0d2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828162532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.3828162532 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.3446891920
Short name	T173
Test name
Test status
Simulation time	356545729 ps
CPU time	1.76 seconds
Started	Jan 10 01:11:08 PM PST 24
Finished	Jan 10 01:12:38 PM PST 24
Peak memory	215512 kb
Host	smart-a28a9b69-ef12-4673-9ff9-606a196490c0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446891920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3446891920 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.1782763857
Short name	T30
Test name
Test status
Simulation time	779860086 ps
CPU time	3.05 seconds
Started	Jan 10 01:11:10 PM PST 24
Finished	Jan 10 01:12:37 PM PST 24
Peak memory	215416 kb
Host	smart-6c89e2e9-5e50-4ee8-8462-daee69cf6917
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782763857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.17827 63857 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest