Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	343	1			T3	5		T7	5		T8	8
all_pins[1]	343	1			T3	5		T7	5		T8	8
all_pins[2]	343	1			T3	5		T7	5		T8	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	824	1			T3	7		T7	15		T8	16
values[0x1]	205	1			T3	8		T8	8		T10	5
transitions[0x0=>0x1]	138	1			T3	2		T8	7		T10	5
transitions[0x1=>0x0]	146	1			T3	2		T8	7		T10	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	267	1			T3	3		T7	5		T8	5
all_pins[0]	values[0x1]	76	1			T3	2		T8	3		T10	2
all_pins[0]	transitions[0x0=>0x1]	49	1			T8	3		T10	2		T23	3
all_pins[0]	transitions[0x1=>0x0]	42	1			T3	1		T8	2		T10	2
all_pins[1]	values[0x0]	274	1			T3	2		T7	5		T8	6
all_pins[1]	values[0x1]	69	1			T3	3		T8	2		T10	2
all_pins[1]	transitions[0x0=>0x1]	50	1			T8	2		T10	2		T41	1
all_pins[1]	transitions[0x1=>0x0]	41	1			T8	3		T10	1		T25	2
all_pins[2]	values[0x0]	283	1			T3	2		T7	5		T8	5
all_pins[2]	values[0x1]	60	1			T3	3		T8	3		T10	1
all_pins[2]	transitions[0x0=>0x1]	39	1			T3	2		T8	2		T10	1
all_pins[2]	transitions[0x1=>0x0]	63	1			T3	1		T8	2		T10	2