Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T3	4		T7	4		T8	7
all_values[1]	284	1			T3	4		T7	4		T8	7
all_values[2]	284	1			T3	4		T7	4		T8	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

477

1

T3

3

T7

11

T8

11

auto[1]

375

1

T3

9

T7

1

T8

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

337

1

T3

2

T7

7

T8

5

auto[1]

515

1

T3

10

T7

5

T8

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

509

1

T3

6

T7

8

T8

14

auto[1]

343

1

T3

6

T7

4

T8

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

56

1

T3

1

T7

3

T23

1

all_values[0]

auto[0]

auto[0]

auto[1]

31

1

T8

2

T10

1

T66

1

all_values[0]

auto[0]

auto[1]

auto[0]

51

1

T3

1

T7

1

T8

2

all_values[0]

auto[0]

auto[1]

auto[1]

31

1

T3

1

T8

1

T10

1

all_values[0]

auto[1]

auto[0]

auto[1]

73

1

T8

1

T10

2

T23

1

all_values[0]

auto[1]

auto[1]

auto[1]

42

1

T3

1

T8

1

T10

1

all_values[1]

auto[0]

auto[0]

auto[0]

71

1

T7

3

T8

2

T10

1

all_values[1]

auto[0]

auto[0]

auto[1]

22

1

T8

1

T25

1

T70

1

all_values[1]

auto[0]

auto[1]

auto[0]

40

1

T10

3

T41

1

T71

2

all_values[1]

auto[0]

auto[1]

auto[1]

26

1

T3

1

T8

2

T10

1

all_values[1]

auto[1]

auto[0]

auto[1]

65

1

T3

1

T7

1

T10

2

all_values[1]

auto[1]

auto[1]

auto[1]

60

1

T3

2

T8

2

T23

2

all_values[2]

auto[0]

auto[0]

auto[0]

69

1

T8

1

T10

1

T41

1

all_values[2]

auto[0]

auto[0]

auto[1]

33

1

T7

1

T8

1

T10

1

all_values[2]

auto[0]

auto[1]

auto[0]

50

1

T23

2

T41

1

T69

4

all_values[2]

auto[0]

auto[1]

auto[1]

29

1

T3

2

T8

2

T10

1

all_values[2]

auto[1]

auto[0]

auto[1]

57

1

T3

1

T7

3

T8

3

all_values[2]

auto[1]

auto[1]

auto[1]

46

1

T3

1

T10

1

T23

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal