Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_kmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257473752	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

206899357

1

T1

43

T2

518

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	243957731	1			T1	2		T2	414		T3	2
values[0x0]	105759027	1			T1	131		T2	147		T3	76
values[0x1]	114656351	1			T1	229		T2	128		T3	158

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200430741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

263942368

1

T1

173

T2

564

T3

121

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1384655	1			T2	4		T46	59		T44	4
valid_sources[0x01]	1380274	1			T1	7		T2	6		T3	2
valid_sources[0x02]	1380469	1			T2	6		T3	2		T46	75
valid_sources[0x03]	1396099	1			T2	2		T46	49		T49	1
valid_sources[0x04]	3443724	1			T3	1		T46	41		T53	1
valid_sources[0x05]	1382902	1			T2	2		T46	53		T44	4
valid_sources[0x06]	1491623	1			T2	1		T3	1		T46	32
valid_sources[0x07]	2301975	1			T1	5		T2	5		T46	76
valid_sources[0x08]	2264355	1			T2	6		T3	3		T46	42
valid_sources[0x09]	3764131	1			T2	1		T46	71		T44	4
valid_sources[0x0a]	3878141	1			T1	4		T2	2		T46	34
valid_sources[0x0b]	2347122	1			T2	3		T46	65		T44	1
valid_sources[0x0c]	1384525	1			T1	13		T2	1		T46	56
valid_sources[0x0d]	1385721	1			T3	2		T46	51		T44	3
valid_sources[0x0e]	1390801	1			T2	2		T3	2		T46	62
valid_sources[0x0f]	1375686	1			T2	5		T3	2		T46	50
valid_sources[0x10]	1715536	1			T2	2		T3	1		T46	68
valid_sources[0x11]	1379148	1			T46	48		T44	1		T48	1
valid_sources[0x12]	1377332	1			T2	3		T3	1		T46	69
valid_sources[0x13]	1381327	1			T1	31		T2	4		T46	64
valid_sources[0x14]	1378795	1			T3	1		T46	43		T48	2
valid_sources[0x15]	1383289	1			T46	71		T53	1		T44	1
valid_sources[0x16]	2243801	1			T1	3		T2	5		T46	75
valid_sources[0x17]	2029483	1			T2	3		T3	1		T46	56
valid_sources[0x18]	1374873	1			T2	1		T3	1		T46	26
valid_sources[0x19]	1388701	1			T2	3		T46	65		T44	2
valid_sources[0x1a]	1376546	1			T46	68		T53	1		T44	3
valid_sources[0x1b]	2036285	1			T2	3		T3	1		T46	68
valid_sources[0x1c]	4444843	1			T3	1		T46	63		T44	3
valid_sources[0x1d]	1373123	1			T2	4		T3	1		T46	58
valid_sources[0x1e]	1381956	1			T46	37		T44	3		T48	2
valid_sources[0x1f]	1388908	1			T2	2		T46	60		T48	2
valid_sources[0x20]	2037511	1			T2	6		T46	53		T44	1
valid_sources[0x21]	1380793	1			T2	4		T3	3		T46	53
valid_sources[0x22]	2139429	1			T2	5		T46	76		T44	3
valid_sources[0x23]	1679216	1			T2	3		T3	3		T46	51
valid_sources[0x24]	1384132	1			T3	2		T46	76		T44	1
valid_sources[0x25]	3826565	1			T2	5		T46	77		T48	1
valid_sources[0x26]	1681702	1			T2	1		T46	62		T44	3
valid_sources[0x27]	1384132	1			T2	2		T3	1		T46	95
valid_sources[0x28]	1381149	1			T2	4		T3	1		T46	54
valid_sources[0x29]	1389067	1			T2	2		T46	46		T44	5
valid_sources[0x2a]	1509230	1			T46	79		T44	1		T48	2
valid_sources[0x2b]	1383051	1			T2	2		T3	1		T46	56
valid_sources[0x2c]	4811640	1			T2	2		T3	1		T46	48
valid_sources[0x2d]	1380988	1			T2	4		T46	63		T44	2
valid_sources[0x2e]	1440707	1			T2	2		T3	2		T46	75
valid_sources[0x2f]	1387821	1			T2	2		T3	3		T46	79
valid_sources[0x30]	2253266	1			T2	3		T46	62		T52	1
valid_sources[0x31]	1381546	1			T3	1		T46	48		T44	2
valid_sources[0x32]	1425286	1			T2	8		T46	53		T48	1
valid_sources[0x33]	1384598	1			T1	11		T2	10		T3	3
valid_sources[0x34]	1394817	1			T2	3		T3	3		T46	42
valid_sources[0x35]	1384244	1			T2	1		T46	71		T44	7
valid_sources[0x36]	1471834	1			T2	3		T46	75		T44	3
valid_sources[0x37]	1392761	1			T2	4		T3	2		T46	65
valid_sources[0x38]	1383451	1			T2	1		T46	46		T44	1
valid_sources[0x39]	1385900	1			T2	2		T3	1		T46	53
valid_sources[0x3a]	1379256	1			T2	4		T46	50		T44	6
valid_sources[0x3b]	2312581	1			T2	2		T46	72		T44	1
valid_sources[0x3c]	1507735	1			T2	2		T46	60		T48	1
valid_sources[0x3d]	4331202	1			T1	1		T2	6		T46	67
valid_sources[0x3e]	1387212	1			T2	4		T46	56		T44	1
valid_sources[0x3f]	1854935	1			T2	4		T46	60		T44	5
valid_sources[0x40]	1630775	1			T3	1		T46	59		T44	5
valid_sources[0x41]	1377898	1			T1	5		T46	43		T53	1
valid_sources[0x42]	2527233	1			T2	3		T3	1		T46	51
valid_sources[0x43]	4170975	1			T2	1		T3	3		T46	55
valid_sources[0x44]	1574049	1			T2	3		T3	3		T46	34
valid_sources[0x45]	1378563	1			T2	4		T3	4		T46	64
valid_sources[0x46]	2312716	1			T2	4		T3	1		T46	44
valid_sources[0x47]	1458946	1			T2	2		T3	1		T46	51
valid_sources[0x48]	1384181	1			T2	3		T46	63		T48	1
valid_sources[0x49]	1395472	1			T2	5		T46	77		T53	1
valid_sources[0x4a]	3440143	1			T2	5		T3	1		T46	43
valid_sources[0x4b]	1380260	1			T2	1		T3	2		T46	74
valid_sources[0x4c]	1386679	1			T2	5		T3	3		T46	27
valid_sources[0x4d]	1382653	1			T1	25		T2	1		T46	55
valid_sources[0x4e]	1383441	1			T2	6		T3	2		T46	30
valid_sources[0x4f]	1388747	1			T1	12		T2	1		T3	3
valid_sources[0x50]	1384250	1			T1	14		T2	2		T3	1
valid_sources[0x51]	1737601	1			T2	2		T46	58		T44	2
valid_sources[0x52]	1390670	1			T1	3		T2	6		T3	1
valid_sources[0x53]	3811589	1			T2	2		T3	2		T46	53
valid_sources[0x54]	2280859	1			T2	2		T3	2		T46	34
valid_sources[0x55]	2591743	1			T46	43		T44	2		T48	2
valid_sources[0x56]	1847273	1			T2	7		T46	52		T44	12
valid_sources[0x57]	1379178	1			T3	1		T46	54		T44	2
valid_sources[0x58]	1884396	1			T2	4		T46	89		T44	7
valid_sources[0x59]	1385565	1			T2	2		T3	1		T46	49
valid_sources[0x5a]	1384044	1			T2	3		T3	2		T46	41
valid_sources[0x5b]	1380805	1			T2	6		T3	6		T46	60
valid_sources[0x5c]	2270663	1			T2	4		T3	2		T46	71
valid_sources[0x5d]	1383625	1			T46	66		T48	1		T52	1
valid_sources[0x5e]	1384857	1			T1	41		T2	2		T46	54
valid_sources[0x5f]	1379817	1			T2	3		T3	4		T46	85
valid_sources[0x60]	1385627	1			T2	1		T46	56		T53	1
valid_sources[0x61]	1390548	1			T2	8		T3	3		T46	41
valid_sources[0x62]	1389464	1			T2	2		T3	1		T46	46
valid_sources[0x63]	1535889	1			T1	35		T2	1		T46	85
valid_sources[0x64]	3810152	1			T2	1		T3	3		T46	49
valid_sources[0x65]	1391159	1			T2	1		T3	1		T46	66
valid_sources[0x66]	1749511	1			T2	10		T3	1		T46	47
valid_sources[0x67]	1398893	1			T2	1		T46	62		T48	1
valid_sources[0x68]	1378686	1			T2	2		T46	59		T44	6
valid_sources[0x69]	1389273	1			T2	4		T3	1		T46	48
valid_sources[0x6a]	1388075	1			T2	2		T3	1		T46	49
valid_sources[0x6b]	1393302	1			T46	53		T48	1		T72	2
valid_sources[0x6c]	2205339	1			T2	4		T46	54		T44	4
valid_sources[0x6d]	1371404	1			T1	14		T2	2		T46	66
valid_sources[0x6e]	1388772	1			T2	2		T3	1		T46	47
valid_sources[0x6f]	1388968	1			T2	2		T46	52		T44	4
valid_sources[0x70]	1884537	1			T2	3		T3	1		T46	83
valid_sources[0x71]	2296870	1			T2	4		T3	4		T46	88
valid_sources[0x72]	1509296	1			T2	1		T3	1		T46	51
valid_sources[0x73]	1381942	1			T2	2		T46	38		T44	2
valid_sources[0x74]	1390113	1			T2	4		T3	2		T46	60
valid_sources[0x75]	1770297	1			T2	2		T3	2		T46	43
valid_sources[0x76]	3803564	1			T2	8		T3	1		T46	87
valid_sources[0x77]	1560917	1			T2	2		T46	65		T44	4
valid_sources[0x78]	1381162	1			T2	1		T3	1		T46	42
valid_sources[0x79]	1567374	1			T2	6		T3	3		T46	53
valid_sources[0x7a]	1379406	1			T2	1		T3	1		T46	71
valid_sources[0x7b]	1863858	1			T3	2		T46	71		T44	2
valid_sources[0x7c]	1376892	1			T2	4		T46	68		T44	10
valid_sources[0x7d]	1428518	1			T2	2		T3	1		T46	54
valid_sources[0x7e]	1382515	1			T2	4		T3	3		T46	62
valid_sources[0x7f]	1393989	1			T2	4		T46	49		T44	3
valid_sources[0x80]	1378849	1			T2	2		T3	2		T46	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89783498

1

T2

252

T3

1

T46

3577

values[0x0]

all_enables

biggest_size

62900051

1

T1

24

T2

145

T3

9

values[0x1]

all_enables

biggest_size

54215808

1

T1

19

T2

121

T3

13