Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[kmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

265609329

1

T1

319

T2

171

T3

213

full_word

207404377

1

T1

43

T2

518

T3

23

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	473013436	1			T1	362		T2	689		T3	236
auto[TlIntgErrCmd]	89	1			T45	4		T80	3		T100	8
auto[TlIntgErrData]	85	1			T45	5		T80	5		T100	6
auto[TlIntgErrBoth]	96	1			T45	1		T80	2		T100	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245515894

1

T1

2

T2

414

T3

2

auto[1]

227497812

1

T1

360

T2

275

T3

234

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	155605304	1			T1	2		T2	162		T3	1
auto[TlIntgErrNone]	partial	auto[1]	110003781	1			T1	317		T2	9		T3	212
auto[TlIntgErrNone]	full_word	auto[0]	89910457	1			T2	252		T3	1		T46	3577
auto[TlIntgErrNone]	full_word	auto[1]	117493894	1			T1	43		T2	266		T3	22
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T45	2		T80	2		T100	4
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T45	1		T100	4		T101	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T80	1		T144	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T45	1		T145	1		T146	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T45	1		T80	1		T100	2
auto[TlIntgErrData]	partial	auto[1]	38	1			T45	4		T80	4		T100	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T147	1		T148	1		T144	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T100	1		T147	2		T149	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T100	4		T101	2		T150	1
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T45	1		T80	2		T100	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T150	1		T141	1		T140	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T150	1		T146	1		T143	2