Unified Coverage Report :: Module :: kmac_reg_top

Module : kmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.87	100.00	99.49			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.87	100.00	99.49			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.87	100.00	99.49			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.98	99.35	96.63	100.00		98.94	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.82	96.32	91.89	100.00	100.00	92.73	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_fault_err	100.00	100.00
u_alert_test_recov_operation_err	100.00	100.00
u_cfg_regwen	100.00	100.00
u_cfg_shadowed0_qe	100.00	100.00				100.00
u_cfg_shadowed_en_unsupported_modestrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_fast_process	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_entropy_ready	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_err_processed	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kmac_en	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_kstrength	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_mode	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_endianness	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_msg_mask	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_sideload	98.66	100.00	94.64			100.00	100.00
u_cfg_shadowed_state_endianness	98.66	100.00	94.64			100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_cmd	100.00	100.00
u_cmd_entropy_req	100.00	100.00
u_cmd_hash_cnt_clr	100.00	100.00
u_entropy_period_prescaler	100.00	100.00	100.00			100.00
u_entropy_period_wait_timer	100.00	100.00	100.00			100.00
u_entropy_refresh_hash_cnt	58.89	66.67	50.00			60.00
u_entropy_refresh_threshold_shadowed	98.66	100.00	94.64			100.00	100.00
u_entropy_seed_0	100.00	100.00
u_entropy_seed_1	100.00	100.00
u_entropy_seed_2	100.00	100.00
u_entropy_seed_3	100.00	100.00
u_entropy_seed_4	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_kmac_done	100.00	100.00	100.00			100.00
u_intr_enable_kmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	100.00	100.00	100.00			100.00
u_intr_state_kmac_done	100.00	100.00	100.00			100.00
u_intr_state_kmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_kmac_done	100.00	100.00
u_intr_test_kmac_err	100.00	100.00
u_key_len	100.00	100.00	100.00			100.00
u_key_share0_0	100.00	100.00
u_key_share0_1	100.00	100.00
u_key_share0_10	100.00	100.00
u_key_share0_11	100.00	100.00
u_key_share0_12	100.00	100.00
u_key_share0_13	100.00	100.00
u_key_share0_14	100.00	100.00
u_key_share0_15	100.00	100.00
u_key_share0_2	100.00	100.00
u_key_share0_3	100.00	100.00
u_key_share0_4	100.00	100.00
u_key_share0_5	100.00	100.00
u_key_share0_6	100.00	100.00
u_key_share0_7	100.00	100.00
u_key_share0_8	100.00	100.00
u_key_share0_9	100.00	100.00
u_key_share1_0	100.00	100.00
u_key_share1_1	100.00	100.00
u_key_share1_10	100.00	100.00
u_key_share1_11	100.00	100.00
u_key_share1_12	100.00	100.00
u_key_share1_13	100.00	100.00
u_key_share1_14	100.00	100.00
u_key_share1_15	100.00	100.00
u_key_share1_2	100.00	100.00
u_key_share1_3	100.00	100.00
u_key_share1_4	100.00	100.00
u_key_share1_5	100.00	100.00
u_key_share1_6	100.00	100.00
u_key_share1_7	100.00	100.00
u_key_share1_8	100.00	100.00
u_key_share1_9	100.00	100.00
u_prefix_0	100.00	100.00	100.00			100.00
u_prefix_1	100.00	100.00	100.00			100.00
u_prefix_10	100.00	100.00	100.00			100.00
u_prefix_2	100.00	100.00	100.00			100.00
u_prefix_3	100.00	100.00	100.00			100.00
u_prefix_4	100.00	100.00	100.00			100.00
u_prefix_5	100.00	100.00	100.00			100.00
u_prefix_6	100.00	100.00	100.00			100.00
u_prefix_7	100.00	100.00	100.00			100.00
u_prefix_8	100.00	100.00	100.00			100.00
u_prefix_9	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	91.58	96.18	82.65			87.50	100.00
u_status_alert_fatal_fault	100.00	100.00
u_status_alert_recov_ctrl_update_err	100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_status_sha3_absorb	100.00	100.00
u_status_sha3_idle	100.00	100.00
u_status_sha3_squeeze	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		528	528	100.00
ALWAYS	80	4	4	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	139	3	3	100.00
CONT_ASSIGN	177	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
CONT_ASSIGN	562	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	609	1	1	100.00
CONT_ASSIGN	615	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	646	1	1	100.00
CONT_ASSIGN	679	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	752	1	1	100.00
CONT_ASSIGN	789	1	1	100.00
CONT_ASSIGN	826	1	1	100.00
CONT_ASSIGN	863	1	1	100.00
CONT_ASSIGN	900	1	1	100.00
CONT_ASSIGN	937	1	1	100.00
CONT_ASSIGN	974	1	1	100.00
CONT_ASSIGN	1011	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1085	1	1	100.00
CONT_ASSIGN	1122	1	1	100.00
CONT_ASSIGN	1128	1	1	100.00
CONT_ASSIGN	1143	1	1	100.00
CONT_ASSIGN	1159	1	1	100.00
CONT_ASSIGN	1175	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1390	1	1	100.00
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1446	1	1	100.00
CONT_ASSIGN	1453	1	1	100.00
CONT_ASSIGN	1467	1	1	100.00
CONT_ASSIGN	1474	1	1	100.00
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1495	1	1	100.00
CONT_ASSIGN	1509	1	1	100.00
CONT_ASSIGN	1516	1	1	100.00
CONT_ASSIGN	1530	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1540	1	1	100.00
CONT_ASSIGN	1554	1	1	100.00
CONT_ASSIGN	1561	1	1	100.00
CONT_ASSIGN	1564	1	1	100.00
CONT_ASSIGN	1578	1	1	100.00
CONT_ASSIGN	1585	1	1	100.00
CONT_ASSIGN	1588	1	1	100.00
CONT_ASSIGN	1602	1	1	100.00
CONT_ASSIGN	1609	1	1	100.00
CONT_ASSIGN	1612	1	1	100.00
CONT_ASSIGN	1626	1	1	100.00
CONT_ASSIGN	1633	1	1	100.00
CONT_ASSIGN	1636	1	1	100.00
CONT_ASSIGN	1650	1	1	100.00
CONT_ASSIGN	1657	1	1	100.00
CONT_ASSIGN	1660	1	1	100.00
CONT_ASSIGN	1674	1	1	100.00
CONT_ASSIGN	1681	1	1	100.00
CONT_ASSIGN	1684	1	1	100.00
CONT_ASSIGN	1698	1	1	100.00
CONT_ASSIGN	1705	1	1	100.00
CONT_ASSIGN	1708	1	1	100.00
CONT_ASSIGN	1722	1	1	100.00
CONT_ASSIGN	1729	1	1	100.00
CONT_ASSIGN	1732	1	1	100.00
CONT_ASSIGN	1746	1	1	100.00
CONT_ASSIGN	1753	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1770	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1780	1	1	100.00
CONT_ASSIGN	1794	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1804	1	1	100.00
CONT_ASSIGN	1818	1	1	100.00
CONT_ASSIGN	1825	1	1	100.00
CONT_ASSIGN	1828	1	1	100.00
CONT_ASSIGN	1842	1	1	100.00
CONT_ASSIGN	1849	1	1	100.00
CONT_ASSIGN	1852	1	1	100.00
CONT_ASSIGN	1866	1	1	100.00
CONT_ASSIGN	1873	1	1	100.00
CONT_ASSIGN	1876	1	1	100.00
CONT_ASSIGN	1890	1	1	100.00
CONT_ASSIGN	1897	1	1	100.00
CONT_ASSIGN	1900	1	1	100.00
CONT_ASSIGN	1914	1	1	100.00
CONT_ASSIGN	1921	1	1	100.00
CONT_ASSIGN	1924	1	1	100.00
CONT_ASSIGN	1938	1	1	100.00
CONT_ASSIGN	1945	1	1	100.00
CONT_ASSIGN	1948	1	1	100.00
CONT_ASSIGN	1962	1	1	100.00
CONT_ASSIGN	1969	1	1	100.00
CONT_ASSIGN	1972	1	1	100.00
CONT_ASSIGN	1986	1	1	100.00
CONT_ASSIGN	1993	1	1	100.00
CONT_ASSIGN	1996	1	1	100.00
CONT_ASSIGN	2010	1	1	100.00
CONT_ASSIGN	2017	1	1	100.00
CONT_ASSIGN	2020	1	1	100.00
CONT_ASSIGN	2034	1	1	100.00
CONT_ASSIGN	2041	1	1	100.00
CONT_ASSIGN	2044	1	1	100.00
CONT_ASSIGN	2058	1	1	100.00
CONT_ASSIGN	2065	1	1	100.00
CONT_ASSIGN	2068	1	1	100.00
CONT_ASSIGN	2082	1	1	100.00
CONT_ASSIGN	2089	1	1	100.00
CONT_ASSIGN	2092	1	1	100.00
CONT_ASSIGN	2106	1	1	100.00
CONT_ASSIGN	2113	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2130	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2140	1	1	100.00
CONT_ASSIGN	2154	1	1	100.00
CONT_ASSIGN	2161	1	1	100.00
CONT_ASSIGN	2164	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2185	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2202	1	1	100.00
CONT_ASSIGN	2209	1	1	100.00
CONT_ASSIGN	2212	1	1	100.00
CONT_ASSIGN	2226	1	1	100.00
CONT_ASSIGN	2233	1	1	100.00
CONT_ASSIGN	2236	1	1	100.00
CONT_ASSIGN	2250	1	1	100.00
CONT_ASSIGN	2257	1	1	100.00
CONT_ASSIGN	2260	1	1	100.00
CONT_ASSIGN	2274	1	1	100.00
CONT_ASSIGN	2281	1	1	100.00
CONT_ASSIGN	2284	1	1	100.00
CONT_ASSIGN	2298	1	1	100.00
CONT_ASSIGN	2304	1	1	100.00
CONT_ASSIGN	2336	1	1	100.00
CONT_ASSIGN	2368	1	1	100.00
CONT_ASSIGN	2400	1	1	100.00
CONT_ASSIGN	2432	1	1	100.00
CONT_ASSIGN	2464	1	1	100.00
CONT_ASSIGN	2496	1	1	100.00
CONT_ASSIGN	2528	1	1	100.00
CONT_ASSIGN	2560	1	1	100.00
CONT_ASSIGN	2592	1	1	100.00
CONT_ASSIGN	2624	1	1	100.00
CONT_ASSIGN	2656	1	1	100.00
ALWAYS	2715	62	62	100.00
CONT_ASSIGN	2779	1	1	100.00
ALWAYS	2783	1	1	100.00
CONT_ASSIGN	2848	1	1	100.00
CONT_ASSIGN	2850	1	1	100.00
CONT_ASSIGN	2852	1	1	100.00
CONT_ASSIGN	2854	1	1	100.00
CONT_ASSIGN	2855	1	1	100.00
CONT_ASSIGN	2857	1	1	100.00
CONT_ASSIGN	2859	1	1	100.00
CONT_ASSIGN	2861	1	1	100.00
CONT_ASSIGN	2862	1	1	100.00
CONT_ASSIGN	2864	1	1	100.00
CONT_ASSIGN	2866	1	1	100.00
CONT_ASSIGN	2868	1	1	100.00
CONT_ASSIGN	2869	1	1	100.00
CONT_ASSIGN	2871	1	1	100.00
CONT_ASSIGN	2873	1	1	100.00
CONT_ASSIGN	2874	1	1	100.00
CONT_ASSIGN	2875	1	1	100.00
CONT_ASSIGN	2876	1	1	100.00
CONT_ASSIGN	2878	1	1	100.00
CONT_ASSIGN	2880	1	1	100.00
CONT_ASSIGN	2882	1	1	100.00
CONT_ASSIGN	2884	1	1	100.00
CONT_ASSIGN	2886	1	1	100.00
CONT_ASSIGN	2888	1	1	100.00
CONT_ASSIGN	2890	1	1	100.00
CONT_ASSIGN	2892	1	1	100.00
CONT_ASSIGN	2894	1	1	100.00
CONT_ASSIGN	2896	1	1	100.00
CONT_ASSIGN	2898	1	1	100.00
CONT_ASSIGN	2900	1	1	100.00
CONT_ASSIGN	2901	1	1	100.00
CONT_ASSIGN	2903	1	1	100.00
CONT_ASSIGN	2905	1	1	100.00
CONT_ASSIGN	2907	1	1	100.00
CONT_ASSIGN	2908	1	1	100.00
CONT_ASSIGN	2909	1	1	100.00
CONT_ASSIGN	2911	1	1	100.00
CONT_ASSIGN	2913	1	1	100.00
CONT_ASSIGN	2914	1	1	100.00
CONT_ASSIGN	2915	1	1	100.00
CONT_ASSIGN	2917	1	1	100.00
CONT_ASSIGN	2918	1	1	100.00
CONT_ASSIGN	2920	1	1	100.00
CONT_ASSIGN	2921	1	1	100.00
CONT_ASSIGN	2923	1	1	100.00
CONT_ASSIGN	2924	1	1	100.00
CONT_ASSIGN	2926	1	1	100.00
CONT_ASSIGN	2927	1	1	100.00
CONT_ASSIGN	2929	1	1	100.00
CONT_ASSIGN	2930	1	1	100.00
CONT_ASSIGN	2932	1	1	100.00
CONT_ASSIGN	2933	1	1	100.00
CONT_ASSIGN	2935	1	1	100.00
CONT_ASSIGN	2936	1	1	100.00
CONT_ASSIGN	2938	1	1	100.00
CONT_ASSIGN	2939	1	1	100.00
CONT_ASSIGN	2941	1	1	100.00
CONT_ASSIGN	2942	1	1	100.00
CONT_ASSIGN	2944	1	1	100.00
CONT_ASSIGN	2945	1	1	100.00
CONT_ASSIGN	2947	1	1	100.00
CONT_ASSIGN	2948	1	1	100.00
CONT_ASSIGN	2950	1	1	100.00
CONT_ASSIGN	2951	1	1	100.00
CONT_ASSIGN	2953	1	1	100.00
CONT_ASSIGN	2954	1	1	100.00
CONT_ASSIGN	2956	1	1	100.00
CONT_ASSIGN	2957	1	1	100.00
CONT_ASSIGN	2959	1	1	100.00
CONT_ASSIGN	2960	1	1	100.00
CONT_ASSIGN	2962	1	1	100.00
CONT_ASSIGN	2963	1	1	100.00
CONT_ASSIGN	2965	1	1	100.00
CONT_ASSIGN	2966	1	1	100.00
CONT_ASSIGN	2968	1	1	100.00
CONT_ASSIGN	2969	1	1	100.00
CONT_ASSIGN	2971	1	1	100.00
CONT_ASSIGN	2972	1	1	100.00
CONT_ASSIGN	2974	1	1	100.00
CONT_ASSIGN	2975	1	1	100.00
CONT_ASSIGN	2977	1	1	100.00
CONT_ASSIGN	2978	1	1	100.00
CONT_ASSIGN	2980	1	1	100.00
CONT_ASSIGN	2981	1	1	100.00
CONT_ASSIGN	2983	1	1	100.00
CONT_ASSIGN	2984	1	1	100.00
CONT_ASSIGN	2986	1	1	100.00
CONT_ASSIGN	2987	1	1	100.00
CONT_ASSIGN	2989	1	1	100.00
CONT_ASSIGN	2990	1	1	100.00
CONT_ASSIGN	2992	1	1	100.00
CONT_ASSIGN	2993	1	1	100.00
CONT_ASSIGN	2995	1	1	100.00
CONT_ASSIGN	2996	1	1	100.00
CONT_ASSIGN	2998	1	1	100.00
CONT_ASSIGN	2999	1	1	100.00
CONT_ASSIGN	3001	1	1	100.00
CONT_ASSIGN	3002	1	1	100.00
CONT_ASSIGN	3004	1	1	100.00
CONT_ASSIGN	3005	1	1	100.00
CONT_ASSIGN	3007	1	1	100.00
CONT_ASSIGN	3008	1	1	100.00
CONT_ASSIGN	3010	1	1	100.00
CONT_ASSIGN	3011	1	1	100.00
CONT_ASSIGN	3013	1	1	100.00
CONT_ASSIGN	3014	1	1	100.00
CONT_ASSIGN	3016	1	1	100.00
CONT_ASSIGN	3017	1	1	100.00
CONT_ASSIGN	3019	1	1	100.00
CONT_ASSIGN	3020	1	1	100.00
CONT_ASSIGN	3022	1	1	100.00
CONT_ASSIGN	3023	1	1	100.00
CONT_ASSIGN	3025	1	1	100.00
CONT_ASSIGN	3026	1	1	100.00
CONT_ASSIGN	3028	1	1	100.00
CONT_ASSIGN	3029	1	1	100.00
CONT_ASSIGN	3031	1	1	100.00
CONT_ASSIGN	3032	1	1	100.00
CONT_ASSIGN	3034	1	1	100.00
CONT_ASSIGN	3035	1	1	100.00
CONT_ASSIGN	3037	1	1	100.00
CONT_ASSIGN	3038	1	1	100.00
CONT_ASSIGN	3040	1	1	100.00
CONT_ASSIGN	3041	1	1	100.00
CONT_ASSIGN	3043	1	1	100.00
CONT_ASSIGN	3044	1	1	100.00
CONT_ASSIGN	3046	1	1	100.00
CONT_ASSIGN	3047	1	1	100.00
CONT_ASSIGN	3049	1	1	100.00
CONT_ASSIGN	3050	1	1	100.00
CONT_ASSIGN	3052	1	1	100.00
CONT_ASSIGN	3053	1	1	100.00
CONT_ASSIGN	3055	1	1	100.00
CONT_ASSIGN	3056	1	1	100.00
CONT_ASSIGN	3058	1	1	100.00
CONT_ASSIGN	3059	1	1	100.00
CONT_ASSIGN	3061	1	1	100.00
CONT_ASSIGN	3062	1	1	100.00
CONT_ASSIGN	3064	1	1	100.00
ALWAYS	3068	62	62	100.00
ALWAYS	3134	91	91	100.00
ALWAYS	3419	3	3	100.00
ALWAYS	3427	3	3	100.00
CONT_ASSIGN	3435	1	1	100.00
CONT_ASSIGN	3438	1	1	100.00
CONT_ASSIGN	3453	1	1	100.00
CONT_ASSIGN	3470	1	1	100.00
CONT_ASSIGN	3478	1	1	100.00
CONT_ASSIGN	3479	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
81	1	1
82	1	1
83	1	1
			MISSING_ELSE
89	1	1
107	1	1
108	1	1
110	1	1
111	1	1
112	1	1
113	1	1
139	1	1
146	1	1
147	1	1
			MISSING_ELSE
177	1	1
178	1	1
562	1	1
577	1	1
593	1	1
609	1	1
615	1	1
630	1	1
646	1	1
679	1	1
715	1	1
752	1	1
789	1	1
826	1	1
863	1	1
900	1	1
937	1	1
974	1	1
1011	1	1
1048	1	1
1085	1	1
1122	1	1
1128	1	1
1143	1	1
1159	1	1
1175	1	1
1303	1	1
1390	1	1
1432	1	1
1446	1	1
1453	1	1
1467	1	1
1474	1	1
1488	1	1
1495	1	1
1509	1	1
1516	1	1
1530	1	1
1537	1	1
1540	1	1
1554	1	1
1561	1	1
1564	1	1
1578	1	1
1585	1	1
1588	1	1
1602	1	1
1609	1	1
1612	1	1
1626	1	1
1633	1	1
1636	1	1
1650	1	1
1657	1	1
1660	1	1
1674	1	1
1681	1	1
1684	1	1
1698	1	1
1705	1	1
1708	1	1
1722	1	1
1729	1	1
1732	1	1
1746	1	1
1753	1	1
1756	1	1
1770	1	1
1777	1	1
1780	1	1
1794	1	1
1801	1	1
1804	1	1
1818	1	1
1825	1	1
1828	1	1
1842	1	1
1849	1	1
1852	1	1
1866	1	1
1873	1	1
1876	1	1
1890	1	1
1897	1	1
1900	1	1
1914	1	1
1921	1	1
1924	1	1
1938	1	1
1945	1	1
1948	1	1
1962	1	1
1969	1	1
1972	1	1
1986	1	1
1993	1	1
1996	1	1
2010	1	1
2017	1	1
2020	1	1
2034	1	1
2041	1	1
2044	1	1
2058	1	1
2065	1	1
2068	1	1
2082	1	1
2089	1	1
2092	1	1
2106	1	1
2113	1	1
2116	1	1
2130	1	1
2137	1	1
2140	1	1
2154	1	1
2161	1	1
2164	1	1
2178	1	1
2185	1	1
2188	1	1
2202	1	1
2209	1	1
2212	1	1
2226	1	1
2233	1	1
2236	1	1
2250	1	1
2257	1	1
2260	1	1
2274	1	1
2281	1	1
2284	1	1
2298	1	1
2304	1	1
2336	1	1
2368	1	1
2400	1	1
2432	1	1
2464	1	1
2496	1	1
2528	1	1
2560	1	1
2592	1	1
2624	1	1
2656	1	1
2715	1	1
2716	1	1
2717	1	1
2718	1	1
2719	1	1
2720	1	1
2721	1	1
2722	1	1
2723	1	1
2724	1	1
2725	1	1
2726	1	1
2727	1	1
2728	1	1
2729	1	1
2730	1	1
2731	1	1
2732	1	1
2733	1	1
2734	1	1
2735	1	1
2736	1	1
2737	1	1
2738	1	1
2739	1	1
2740	1	1
2741	1	1
2742	1	1
2743	1	1
2744	1	1
2745	1	1
2746	1	1
2747	1	1
2748	1	1
2749	1	1
2750	1	1
2751	1	1
2752	1	1
2753	1	1
2754	1	1
2755	1	1
2756	1	1
2757	1	1
2758	1	1
2759	1	1
2760	1	1
2761	1	1
2762	1	1
2763	1	1
2764	1	1
2765	1	1
2766	1	1
2767	1	1
2768	1	1
2769	1	1
2770	1	1
2771	1	1
2772	1	1
2773	1	1
2774	1	1
2775	1	1
2776	1	1
2779	1	1
2783	1	1
2848	1	1
2850	1	1
2852	1	1
2854	1	1
2855	1	1
2857	1	1
2859	1	1
2861	1	1
2862	1	1
2864	1	1
2866	1	1
2868	1	1
2869	1	1
2871	1	1
2873	1	1
2874	1	1
2875	1	1
2876	1	1
2878	1	1
2880	1	1
2882	1	1
2884	1	1
2886	1	1
2888	1	1
2890	1	1
2892	1	1
2894	1	1
2896	1	1
2898	1	1
2900	1	1
2901	1	1
2903	1	1
2905	1	1
2907	1	1
2908	1	1
2909	1	1
2911	1	1
2913	1	1
2914	1	1
2915	1	1
2917	1	1
2918	1	1
2920	1	1
2921	1	1
2923	1	1
2924	1	1
2926	1	1
2927	1	1
2929	1	1
2930	1	1
2932	1	1
2933	1	1
2935	1	1
2936	1	1
2938	1	1
2939	1	1
2941	1	1
2942	1	1
2944	1	1
2945	1	1
2947	1	1
2948	1	1
2950	1	1
2951	1	1
2953	1	1
2954	1	1
2956	1	1
2957	1	1
2959	1	1
2960	1	1
2962	1	1
2963	1	1
2965	1	1
2966	1	1
2968	1	1
2969	1	1
2971	1	1
2972	1	1
2974	1	1
2975	1	1
2977	1	1
2978	1	1
2980	1	1
2981	1	1
2983	1	1
2984	1	1
2986	1	1
2987	1	1
2989	1	1
2990	1	1
2992	1	1
2993	1	1
2995	1	1
2996	1	1
2998	1	1
2999	1	1
3001	1	1
3002	1	1
3004	1	1
3005	1	1
3007	1	1
3008	1	1
3010	1	1
3011	1	1
3013	1	1
3014	1	1
3016	1	1
3017	1	1
3019	1	1
3020	1	1
3022	1	1
3023	1	1
3025	1	1
3026	1	1
3028	1	1
3029	1	1
3031	1	1
3032	1	1
3034	1	1
3035	1	1
3037	1	1
3038	1	1
3040	1	1
3041	1	1
3043	1	1
3044	1	1
3046	1	1
3047	1	1
3049	1	1
3050	1	1
3052	1	1
3053	1	1
3055	1	1
3056	1	1
3058	1	1
3059	1	1
3061	1	1
3062	1	1
3064	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3078	1	1
3079	1	1
3080	1	1
3081	1	1
3082	1	1
3083	1	1
3084	1	1
3085	1	1
3086	1	1
3087	1	1
3088	1	1
3089	1	1
3090	1	1
3091	1	1
3092	1	1
3093	1	1
3094	1	1
3095	1	1
3096	1	1
3097	1	1
3098	1	1
3099	1	1
3100	1	1
3101	1	1
3102	1	1
3103	1	1
3104	1	1
3105	1	1
3106	1	1
3107	1	1
3108	1	1
3109	1	1
3110	1	1
3111	1	1
3112	1	1
3113	1	1
3114	1	1
3115	1	1
3116	1	1
3117	1	1
3118	1	1
3119	1	1
3120	1	1
3121	1	1
3122	1	1
3123	1	1
3124	1	1
3125	1	1
3126	1	1
3127	1	1
3128	1	1
3129	1	1
3134	1	1
3135	1	1
3137	1	1
3138	1	1
3139	1	1
3143	1	1
3144	1	1
3145	1	1
3149	1	1
3150	1	1
3151	1	1
3155	1	1
3156	1	1
3160	1	1
3164	1	1
3165	1	1
3166	1	1
3167	1	1
3168	1	1
3169	1	1
3170	1	1
3171	1	1
3172	1	1
3173	1	1
3174	1	1
3175	1	1
3179	1	1
3180	1	1
3181	1	1
3185	1	1
3186	1	1
3187	1	1
3188	1	1
3189	1	1
3190	1	1
3191	1	1
3192	1	1
3196	1	1
3197	1	1
3201	1	1
3205	1	1
3209	1	1
3213	1	1
3217	1	1
3221	1	1
3225	1	1
3229	1	1
3233	1	1
3237	1	1
3241	1	1
3245	1	1
3249	1	1
3253	1	1
3257	1	1
3261	1	1
3265	1	1
3269	1	1
3273	1	1
3277	1	1
3281	1	1
3285	1	1
3289	1	1
3293	1	1
3297	1	1
3301	1	1
3305	1	1
3309	1	1
3313	1	1
3317	1	1
3321	1	1
3325	1	1
3329	1	1
3333	1	1
3337	1	1
3341	1	1
3345	1	1
3349	1	1
3353	1	1
3357	1	1
3361	1	1
3365	1	1
3369	1	1
3373	1	1
3377	1	1
3381	1	1
3385	1	1
3389	1	1
3393	1	1
3397	1	1
3401	1	1
3405	1	1
3419	1	1
3420	1	1
3422	1	1
3427	1	1
3428	1	1
3430	1	1
3435	1	1
3438	1	1
3453	1	1
3470	1	1
3478	1	1
3479	1	1

---

Cond Coverage for Module : kmac_reg_top

	Total	Covered	Percent
Conditions	783	779	99.49
Logical	783	779	99.49
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
70-2783	100.00
2783-3435	99.01

---

Branch Coverage for Module : kmac_reg_top

	Line No.	Total	Covered	Percent
Branches		76	76	100.00
TERNARY	2779	2	2	100.00
IF	80	3	3	100.00
TERNARY	139	3	3	100.00
IF	146	2	2	100.00
CASE	3135	62	62	100.00
IF	3419	2	2	100.00
IF	3427	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	2779	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	80	if ((!rst_ni))
-2-:	82	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T45,T80,T100
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	((tl_i.a_address[(AW - 1):0] inside {[1024:1535]})) ? 
-2-:	139	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T47,T44
0	1	Covered	T1,T3,T47
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	146	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T45,T80,T100
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3135	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T2,T3,T46
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T2,T3,T46
addr_hit[9]	Covered	T2,T3,T46
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T2,T3,T46
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T2,T3,T46
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T2,T3,T46
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T2,T3,T46
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T2,T3,T46
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T2,T3,T46
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T2,T3,T46
addr_hit[27]	Covered	T2,T3,T46
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T2,T3,T46
addr_hit[32]	Covered	T2,T3,T46
addr_hit[33]	Covered	T2,T3,T46
addr_hit[34]	Covered	T2,T3,T46
addr_hit[35]	Covered	T2,T3,T46
addr_hit[36]	Covered	T2,T3,T46
addr_hit[37]	Covered	T2,T3,T46
addr_hit[38]	Covered	T2,T3,T46
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T2,T3,T46
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T2,T3,T46
addr_hit[43]	Covered	T2,T3,T46
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T2,T3,T46
addr_hit[46]	Covered	T2,T3,T46
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T2,T3,T46
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T2,T3,T46
addr_hit[51]	Covered	T2,T3,T46
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T2,T3,T46
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T2,T3,T46
addr_hit[57]	Covered	T2,T3,T46
addr_hit[58]	Covered	T2,T3,T46
addr_hit[59]	Covered	T1,T2,T3
addr_hit[60]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3419	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	3427	if ((!rst_shadowed_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : kmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2147483647	312660501	0	0
reAfterRv	2147483647	312660495	0	0
rePulse	2147483647	205017592	0	0
wePulse	2147483647	107642903	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	312660501	0	0
T1	1435	3	0	0
T2	5283	689	0	0
T3	2905	3	0	0
T44	2789	754	0	0
T45	5086	1331	0	0
T46	155765	14685	0	0
T47	1003	40	0	0
T48	5818	21	0	0
T53	881	22	0	0
T54	1049	38	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	312660495	0	0
T1	1435	3	0	0
T2	5283	689	0	0
T3	2905	3	0	0
T44	2789	754	0	0
T45	5086	1331	0	0
T46	155765	14685	0	0
T47	1003	40	0	0
T48	5818	21	0	0
T53	881	22	0	0
T54	1049	38	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	205017592	0	0
T1	1435	2	0	0
T2	5283	414	0	0
T3	2905	2	0	0
T44	2789	479	0	0
T45	5086	727	0	0
T46	155765	7221	0	0
T47	1003	20	0	0
T48	5818	2	0	0
T53	881	11	0	0
T54	1049	19	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107642903	0	0
T1	1435	1	0	0
T2	5283	275	0	0
T3	2905	1	0	0
T44	2789	275	0	0
T45	5086	604	0	0
T46	155765	7464	0	0
T47	1003	20	0	0
T48	5818	19	0	0
T53	881	11	0	0
T54	1049	19	0	0